Merge "asoc: optimize the power down logic of hph playback widget"
Este cometimento está contido em:
qctecmdr
cometido por
Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
cometimento
2d956849c5
@@ -162,8 +162,6 @@ enum {
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ADC_MODE_HIFI,
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ADC_MODE_NORMAL,
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ADC_MODE_LP,
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ADC_MODE_ULP1,
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ADC_MODE_ULP2,
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};
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static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
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@@ -210,8 +208,6 @@ static int wcd9378_handle_post_irq(void *data)
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wcd9378->tx_swr_dev->slave_irq_pending =
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((sts1 || sts2 || !sts3) ? true : false);
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pr_debug("%s: sts1: 0x%0x, sts2: 0x%0x, sts3: 0x%0x\n", __func__, sts1, sts2, sts3);
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return IRQ_HANDLED;
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}
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@@ -904,33 +900,6 @@ static int wcd9378_get_clk_rate(int mode)
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return rate;
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}
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static int wcd9378_set_swr_clk_rate(struct snd_soc_component *component,
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int rate, int bank)
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{
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u8 mask = (bank ? 0xF0 : 0x0F);
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u8 val = 0;
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switch (rate) {
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case SWR_CLK_RATE_2P4MHZ:
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val = (bank ? 0x30 : 0x03);
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break;
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case SWR_CLK_RATE_4P8MHZ:
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val = (bank ? 0x10 : 0x01);
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break;
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case SWR_CLK_RATE_9P6MHZ:
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default:
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val = 0x00;
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break;
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}
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dev_dbg(component->dev,
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"%s: rate: 0x%0x\n", __func__, val);
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snd_soc_component_update_bits(component, WCD9378_SWR_TX_CLK_RATE,
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mask, val);
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return 0;
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}
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static int wcd9378_get_adc_mode_val(int mode)
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{
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int ret = 0;
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@@ -980,12 +949,10 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
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}
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rate = wcd9378_get_clk_rate(wcd9378->tx_mode[w->shift - ADC1]);
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if (w->shift == ADC2 && !((snd_soc_component_read(component,
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WCD9378_TX_NEW_TX_CH12_MUX) &
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WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10)) {
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if (!wcd9378->bcs_dis) {
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dev_err(component->dev, "%s: mbhc connect port enter\n", __func__);
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wcd9378_tx_connect_port(component, MBHC,
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SWR_CLK_RATE_4P8MHZ, true);
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set_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
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@@ -1004,7 +971,6 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
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MICB_ENABLE, true);
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switch (w->shift) {
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case ADC1:
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dev_dbg(component->dev, "%s ADC1 enter\n", __func__);
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/*SMP MIC0 IT11 USAGE SET*/
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snd_soc_component_update_bits(component, WCD9378_IT11_USAGE,
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WCD9378_IT11_USAGE_IT11_USAGE_MASK, mode_val);
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@@ -1020,7 +986,6 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
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break;
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case ADC2:
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if (wcd9378->sjmic_support) {
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dev_dbg(component->dev, "%s SJ ADC2 enter\n", __func__);
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/*SMP JACK IT31 USAGE SET*/
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snd_soc_component_update_bits(component,
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WCD9378_IT31_USAGE,
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@@ -1030,7 +995,6 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
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WCD9378_PDE34_REQ_PS,
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WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x00);
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} else {
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dev_dbg(component->dev, "%s SM1 ADC2 enter\n", __func__);
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/*SMP MIC1 IT11 USAGE SET*/
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snd_soc_component_update_bits(component,
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WCD9378_SMP_MIC_CTRL1_IT11_USAGE,
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@@ -1049,7 +1013,6 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
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}
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break;
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case ADC3:
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dev_dbg(component->dev, "%s SM2 ADC3 enter\n", __func__);
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/*SMP MIC2 IT11 USAGE SET*/
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snd_soc_component_update_bits(component,
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WCD9378_SMP_MIC_CTRL2_IT11_USAGE,
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@@ -1069,47 +1032,30 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
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}
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/*default delay 800us*/
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usleep_range(800, 810);
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/****ADC START*****/
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wcd9378_set_swr_clk_rate(component, rate, bank);
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wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, true);
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ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
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wcd9378->tx_swr_dev->dev_num,
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true);
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/* Copy clk settings to active bank */
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wcd9378_set_swr_clk_rate(component, rate, !bank);
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wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, true);
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/****ADC END*****/
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switch (w->shift) {
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case ADC1:
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snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
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WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
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act_ps = snd_soc_component_read(component, WCD9378_PDE11_ACT_PS);
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if (act_ps)
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dev_dbg(component->dev, "%s: tx0 sequencer didnot power on, act_ps: 0x%0x\n",
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__func__, act_ps);
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else
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dev_dbg(component->dev, "%s: tx0 sequencer power on successful, act_ps: 0x%0x\n",
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__func__, act_ps);
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break;
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case ADC2:
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snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
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WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x00);
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break;
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case ADC3:
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snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
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WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
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break;
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};
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if (w->shift == ADC1) {
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act_ps = snd_soc_component_read(component, WCD9378_PDE11_ACT_PS);
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if (act_ps)
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pr_err("%s: tx0 sequencer didnot power on, act_ps: 0x%0x\n",
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__func__, act_ps);
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else
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pr_err("%s: tx0 sequencer power on successful, act_ps: 0x%0x\n",
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__func__, act_ps);
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}
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if (w->shift == ADC2) {
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if (wcd9378->sjmic_support)
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act_ps = snd_soc_component_read(component,
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WCD9378_PDE34_ACT_PS);
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@@ -1118,15 +1064,28 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
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WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS);
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if (act_ps)
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pr_err("%s: tx1 sequencer didnot power on, act_ps: 0x%0x\n",
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dev_dbg(component->dev, "%s: tx1 sequencer didnot power on, act_ps: 0x%0x\n",
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__func__, act_ps);
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else
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pr_err("%s: tx1 sequencer power on successful, act_ps: 0x%0x\n",
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dev_dbg(component->dev, "%s: tx1 sequencer power on successful, act_ps: 0x%0x\n",
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__func__, act_ps);
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}
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break;
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case ADC3:
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snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
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WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
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act_ps = snd_soc_component_read(component,
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WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS);
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if (act_ps)
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dev_dbg(component->dev, "%s: tx2 sequencer didnot power on, act_ps: 0x%0x\n",
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__func__, act_ps);
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else
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dev_dbg(component->dev, "%s: tx2 sequencer power on successful, act_ps: 0x%0x\n",
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__func__, act_ps);
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break;
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};
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break;
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case SND_SOC_DAPM_POST_PMD:
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/****ADC START****/
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wcd9378_tx_connect_port(component, w->shift, 0, false);
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if (w->shift == ADC2 &&
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test_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask)) {
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@@ -1135,8 +1094,6 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
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clear_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
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}
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/****ADC END****/
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switch (w->shift) {
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case ADC1:
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/*Normal TXFE Startup*/
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@@ -1176,19 +1133,12 @@ static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
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/*default delay 800us*/
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usleep_range(800, 810);
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rate = wcd9378_get_clk_rate(wcd9378->tx_mode[w->shift - ADC1]);
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wcd9378_set_swr_clk_rate(component, rate, bank);
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wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, false);
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ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
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wcd9378->tx_swr_dev->dev_num,
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false);
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wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, false);
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wcd9378_set_swr_clk_rate(component, rate, !bank);
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if (wcd9378->va_amic_en)
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wcd9378_micbias_control(component, w->shift,
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MICB_PULLUP_DISABLE, true);
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@@ -1388,15 +1338,6 @@ static int wcd9378_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
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(WCD_RX1 << 0x10));
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break;
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case SND_SOC_DAPM_POST_PMD:
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if (wcd9378->update_wcd_event)
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wcd9378->update_wcd_event(wcd9378->handle,
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SLV_BOLERO_EVT_RX_MUTE,
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(WCD_RX1 << 0x10 | 0x1));
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if (wcd9378->update_wcd_event && wcd9378->comp1_enable)
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wcd9378->update_wcd_event(wcd9378->handle,
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SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
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(WCD_RX1 << 0x10));
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/*HPHL DISABLE*/
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snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
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WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
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@@ -1497,12 +1438,11 @@ static int wcd9378_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
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act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
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if (act_ps)
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pr_err("%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
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dev_dbg(component->dev, "%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
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__func__, act_ps);
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else
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pr_err("%s: hph sequencer power on successful, act_ps: 0x%0x\n",
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dev_dbg(component->dev, "%s: hph sequencer power on successful, act_ps: 0x%0x\n",
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__func__, act_ps);
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break;
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case SND_SOC_DAPM_POST_PMD:
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if (wcd9378->update_wcd_event)
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@@ -1515,17 +1455,9 @@ static int wcd9378_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
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SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
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(WCD_RX1 << 0x10));
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if (!wcd9378->comp1_enable)
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/*PA delay is 24250us*/
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usleep_range(24300, 24310);
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else
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/*COMP delay is 11250us*/
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usleep_range(11300, 11310);
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blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
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WCD_EVENT_POST_HPHL_PA_OFF,
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&wcd9378->mbhc->wcd_mbhc);
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break;
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default:
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break;
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@@ -1542,6 +1474,7 @@ static int wcd9378_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
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snd_soc_dapm_to_component(w->dapm);
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struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
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int ret;
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int act_ps = 0;
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dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
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w->name, event);
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@@ -1559,6 +1492,14 @@ static int wcd9378_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
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wcd9378->update_wcd_event(wcd9378->handle,
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SLV_BOLERO_EVT_RX_MUTE,
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(WCD_RX2 << 0x10));
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act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
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if (act_ps)
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dev_dbg(component->dev, "%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
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__func__, act_ps);
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else
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dev_dbg(component->dev, "%s: hph sequencer power on successful, act_ps: 0x%0x\n",
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__func__, act_ps);
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break;
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case SND_SOC_DAPM_POST_PMD:
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if (wcd9378->update_wcd_event)
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@@ -1571,17 +1512,9 @@ static int wcd9378_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
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SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
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(WCD_RX2 << 0x10));
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if (!wcd9378->comp2_enable)
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/*PA delay is 24250us*/
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usleep_range(24300, 24310);
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else
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/*COMP delay is 11250us*/
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usleep_range(11300, 11310);
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blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
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WCD_EVENT_POST_HPHR_PA_OFF,
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&wcd9378->mbhc->wcd_mbhc);
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break;
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default:
|
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break;
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@@ -1600,6 +1533,7 @@ static int wcd9378_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
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struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
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int ret = 0;
|
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int bank = 0;
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int act_ps = 0;
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dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
|
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w->name, event);
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@@ -1634,6 +1568,14 @@ static int wcd9378_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
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SLV_BOLERO_EVT_RX_MUTE,
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(WCD_RX3 << 0x10));
|
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}
|
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|
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act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
|
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if (act_ps)
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dev_dbg(component->dev, "%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
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__func__, act_ps);
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else
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dev_dbg(component->dev, "%s: sa sequencer power on successful, act_ps: 0x%0x\n",
|
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__func__, act_ps);
|
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break;
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case SND_SOC_DAPM_POST_PMD:
|
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if (wcd9378->aux_rx_path & AUX_RX_PATH_RX1) {
|
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@@ -1697,10 +1639,10 @@ static int wcd9378_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
|
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|
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act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
|
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if (act_ps)
|
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pr_err("%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
|
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dev_dbg(component->dev, "%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
|
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__func__, act_ps);
|
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else
|
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pr_err("%s: sa sequencer power on successful, act_ps: 0x%0x\n",
|
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dev_dbg(component->dev, "%s: sa sequencer power on successful, act_ps: 0x%0x\n",
|
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__func__, act_ps);
|
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|
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break;
|
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@@ -1775,6 +1717,7 @@ static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, boo
|
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{
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u16 clk_scale_reg = 0;
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u8 clk_rst = 0x00, scale_rst = 0x00;
|
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u8 swr_base_clk = 0, swr_clk_scale = 0;
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struct wcd9378_priv *wcd9378 = NULL;
|
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struct swr_device *swr_dev = NULL;
|
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|
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@@ -1782,23 +1725,24 @@ static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, boo
|
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if (!wcd9378)
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return -EINVAL;
|
||||
|
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if (path == RX_PATH)
|
||||
if (path == RX_PATH) {
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swr_dev = wcd9378->rx_swr_dev;
|
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else
|
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swr_base_clk = wcd9378->swr_base_clk;
|
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swr_clk_scale = wcd9378->swr_clk_scale;
|
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} else {
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swr_dev = wcd9378->tx_swr_dev;
|
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swr_base_clk = SWR_BASECLK_19P2MHZ;
|
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swr_clk_scale = SWR_CLKSCALE_DIV2;
|
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}
|
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|
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clk_scale_reg = (bank ? SWRS_SCP_BUSCLOCK_SCALE_BANK1 :
|
||||
SWRS_SCP_BUSCLOCK_SCALE_BANK0);
|
||||
|
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if (enable) {
|
||||
pr_debug("%s: bank: %d base_clk: 0x%0x, clk_scale_reg: 0x%0x, swr_clk_scale: 0x%0x\n",
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||||
__func__, bank, wcd9378->swr_base_clk,
|
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clk_scale_reg, wcd9378->swr_clk_scale);
|
||||
|
||||
swr_write(swr_dev, swr_dev->dev_num,
|
||||
SWRS_SCP_BASE_CLK_BASE, &wcd9378->swr_base_clk);
|
||||
SWRS_SCP_BASE_CLK_BASE, &swr_base_clk);
|
||||
swr_write(swr_dev, swr_dev->dev_num,
|
||||
clk_scale_reg, &wcd9378->swr_clk_scale);
|
||||
clk_scale_reg, &swr_clk_scale);
|
||||
} else {
|
||||
swr_write(swr_dev, swr_dev->dev_num,
|
||||
SWRS_SCP_BASE_CLK_BASE, &clk_rst);
|
||||
@@ -1883,6 +1827,12 @@ static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
|
||||
snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
|
||||
WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x03);
|
||||
|
||||
if (!wcd9378->comp1_enable || !wcd9378->comp2_enable)
|
||||
/*PA delay is 24250us*/
|
||||
usleep_range(24300, 24310);
|
||||
else
|
||||
/*COMP delay is 11250us*/
|
||||
usleep_range(11300, 11310);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
@@ -1993,8 +1943,6 @@ static int wcd9378_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
|
||||
|
||||
wcd9378_rx_connect_port(component, LO, true);
|
||||
}
|
||||
|
||||
set_bit(WCD_AUX_EN, &wcd9378->status_mask);
|
||||
break;
|
||||
case SND_SOC_DAPM_POST_PMD:
|
||||
if (aux_rx1) {
|
||||
@@ -2004,8 +1952,6 @@ static int wcd9378_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
|
||||
WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x00);
|
||||
wcd9378_rx_connect_port(component, LO, true);
|
||||
}
|
||||
|
||||
clear_bit(WCD_AUX_EN, &wcd9378->status_mask);
|
||||
break;
|
||||
};
|
||||
return 0;
|
||||
@@ -2290,7 +2236,6 @@ int wcd9378_swr_dmic_register_notifier(struct snd_soc_component *component,
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(wcd9378_swr_dmic_register_notifier);
|
||||
|
||||
/*TBD: NEED TO CHECK AND UPDATE*/
|
||||
static int wcd9378_event_notify(struct notifier_block *block,
|
||||
unsigned long val,
|
||||
void *data)
|
||||
|
||||
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