samsung-sm8650/android_kernel_samsung_sm8650-modules
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

cnss2: Add GCC register read for debugging

Browse Source 
Read GCC spare register after SOC reset to check device
status.

Change-Id: If25d8e42fcf6921744b1907e1abd4ef16ac95148
CRs-Fixed: 3290178
This commit is contained in:
Naman Padhiar
2022-09-28 12:22:28 +05:30
committed by Madan Koyyalamudi
parent 1296d41e40
commit 2d912a8ca2
2 changed files with 52 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

50
cnss2/pci.c
View File

@@ -1691,6 +1691,50 @@ static int cnss_pci_check_mhi_state_bit(struct cnss_pci_data *pci_priv,
return -EINVAL;
}
static cnss_rddm_trigger_debug(struct cnss_pci_data *pci_priv)
{
int read_val, ret;
switch (pci_priv->device_id) {
case QCA6490_DEVICE_ID:
case KIWI_DEVICE_ID:
case MANGO_DEVICE_ID:
break;
default:
cnss_pr_err("RDDM Trigger debug not supported");
return -EOPNOTSUPP;
}
cnss_pr_err("Write GCC Spare with ACE55 Pattern");
cnss_pci_reg_write(pci_priv, GCC_GCC_SPARE_REG_1, 0xACE55);
ret = cnss_pci_reg_read(pci_priv, GCC_GCC_SPARE_REG_1, &read_val);
cnss_pr_err("Read back GCC Spare: 0x%x, ret: %d", read_val, ret);
ret = cnss_pci_reg_read(pci_priv, GCC_PRE_ARES_DEBUG_TIMER_VAL,
&read_val);
cnss_pr_err("Warm reset allowed check: 0x%x, ret: %d", read_val, ret);
return ret;
}
static cnss_rddm_trigger_check(struct cnss_pci_data *pci_priv)
{
int read_val, ret;
switch (pci_priv->device_id) {
case QCA6490_DEVICE_ID:
case KIWI_DEVICE_ID:
case MANGO_DEVICE_ID:
break;
default:
cnss_pr_err("RDDM Trigger check not supported");
return -EOPNOTSUPP;
}
ret = cnss_pci_reg_read(pci_priv, GCC_GCC_SPARE_REG_1, &read_val);
cnss_pr_err("Read GCC spare to check reset status: 0x%x, ret: %d",
read_val, ret);
return ret;
}
static void cnss_pci_set_mhi_state_bit(struct cnss_pci_data *pci_priv,
enum cnss_mhi_state mhi_state)
{
@@ -1808,12 +1852,14 @@ retry_mhi_suspend:
mutex_unlock(&pci_priv->mhi_ctrl->pm_mutex);
break;
case CNSS_MHI_TRIGGER_RDDM:
cnss_rddm_trigger_debug(pci_priv);
ret = mhi_force_rddm_mode(pci_priv->mhi_ctrl);
if (ret) {
cnss_pr_err("Failed to trigger RDDM, err = %d\n", ret);
cnss_pr_dbg("Sending host reset req\n");
ret = cnss_mhi_force_reset(pci_priv);
cnss_rddm_trigger_check(pci_priv);
}
break;
case CNSS_MHI_RDDM_DONE:
@@ -5035,16 +5081,18 @@ void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic)
cnss_pci_dump_misc_reg(pci_priv);
cnss_pci_dump_shadow_reg(pci_priv);
cnss_rddm_trigger_debug(pci_priv);
ret = mhi_download_rddm_image(pci_priv->mhi_ctrl, in_panic);
if (ret) {
cnss_fatal_err("Failed to download RDDM image, err = %d\n",
ret);
if (!cnss_pci_assert_host_sol(pci_priv))
return;
cnss_rddm_trigger_check(pci_priv);
cnss_pci_dump_debug_reg(pci_priv);
return;
}
cnss_rddm_trigger_check(pci_priv);
fw_image = pci_priv->mhi_ctrl->fbc_image;
rddm_image = pci_priv->mhi_ctrl->rddm_image;
dump_data->nentries = 0;

3
cnss2/reg.h
View File

@@ -343,4 +343,7 @@
#define PCIE_SCRATCH_0_SOC_PCIE_REG 0x1E04040
#define PCIE_SCRATCH_1_SOC_PCIE_REG 0x1E04044
#define PCIE_SCRATCH_2_SOC_PCIE_REG 0x1E0405C
#define GCC_GCC_SPARE_REG_1 0x1E40310
#define GCC_PRE_ARES_DEBUG_TIMER_VAL 0x1E40270
#endif