cnss2: Add GCC register read for debugging
Read GCC spare register after SOC reset to check device status. Change-Id: If25d8e42fcf6921744b1907e1abd4ef16ac95148 CRs-Fixed: 3290178
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committed by
Madan Koyyalamudi

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1296d41e40
commit
2d912a8ca2
@@ -343,4 +343,7 @@
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#define PCIE_SCRATCH_0_SOC_PCIE_REG 0x1E04040
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#define PCIE_SCRATCH_1_SOC_PCIE_REG 0x1E04044
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#define PCIE_SCRATCH_2_SOC_PCIE_REG 0x1E0405C
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#define GCC_GCC_SPARE_REG_1 0x1E40310
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#define GCC_PRE_ARES_DEBUG_TIMER_VAL 0x1E40270
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#endif
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