samsung-sm8650/android_kernel_samsung_sm8650-modules
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Merge "disp: msm: sde: cache cwb enc mask to use during seamless transitions"

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This commit is contained in:
qctecmdr
2022-10-20 12:29:12 -07:00
committed by Gerrit - the friendly Code Review server
parent 22a3c5a842 09b2c937c2
commit 2d49ae68e6
3 changed files with 22 additions and 0 deletions
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7
msm/dsi/dsi_ctrl.c
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@@ -338,6 +338,13 @@ static int dsi_ctrl_debugfs_deinit(struct dsi_ctrl *dsi_ctrl)
#else #else
static int dsi_ctrl_debugfs_init(struct dsi_ctrl *dsi_ctrl, struct dentry *parent) static int dsi_ctrl_debugfs_init(struct dsi_ctrl *dsi_ctrl, struct dentry *parent)
{ {
char dbg_name[DSI_DEBUG_NAME_LEN];
snprintf(dbg_name, DSI_DEBUG_NAME_LEN, "dsi%d_ctrl",
dsi_ctrl->cell_index);
sde_dbg_reg_register_base(dbg_name,
dsi_ctrl->hw.base,
msm_iomap_size(dsi_ctrl->pdev, "dsi_ctrl"));
return 0; return 0;
} }
static int dsi_ctrl_debugfs_deinit(struct dsi_ctrl *dsi_ctrl) static int dsi_ctrl_debugfs_deinit(struct dsi_ctrl *dsi_ctrl)

2
msm/sde/sde_crtc.h
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@@ -508,6 +508,7 @@ struct sde_line_insertion_param {
* @input_fence_timeout_ns : Cached input fence timeout, in ns * @input_fence_timeout_ns : Cached input fence timeout, in ns
* @num_dim_layers: Number of dim layers * @num_dim_layers: Number of dim layers
* @cwb_enc_mask : encoder mask populated during atomic_check if CWB is enabled * @cwb_enc_mask : encoder mask populated during atomic_check if CWB is enabled
* @cached_cwb_enc_mask : cached encoder mask populated during atomic_check if CWB is enabled
* @dim_layer: Dim layer configs * @dim_layer: Dim layer configs
* @num_ds: Number of destination scalers to be configured * @num_ds: Number of destination scalers to be configured
* @num_ds_enabled: Number of destination scalers enabled * @num_ds_enabled: Number of destination scalers enabled
@@ -546,6 +547,7 @@ struct sde_crtc_state {
uint64_t input_fence_timeout_ns; uint64_t input_fence_timeout_ns;
uint32_t num_dim_layers; uint32_t num_dim_layers;
uint32_t cwb_enc_mask; uint32_t cwb_enc_mask;
uint32_t cached_cwb_enc_mask;
struct sde_hw_dim_layer dim_layer[SDE_MAX_DIM_LAYERS]; struct sde_hw_dim_layer dim_layer[SDE_MAX_DIM_LAYERS];
uint32_t num_ds; uint32_t num_ds;
uint32_t num_ds_enabled; uint32_t num_ds_enabled;

13
msm/sde/sde_encoder.c
View File

@@ -930,6 +930,7 @@ void sde_encoder_set_clone_mode(struct drm_encoder *drm_enc,
} }
} }
sde_crtc_state->cached_cwb_enc_mask = sde_crtc_state->cwb_enc_mask;
sde_crtc_state->cwb_enc_mask = 0; sde_crtc_state->cwb_enc_mask = 0;
} }
@@ -2605,6 +2606,8 @@ static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
struct sde_encoder_virt *sde_enc; struct sde_encoder_virt *sde_enc;
struct sde_kms *sde_kms; struct sde_kms *sde_kms;
struct drm_connector *conn; struct drm_connector *conn;
struct drm_crtc_state *crtc_state;
struct sde_crtc_state *sde_crtc_state;
struct sde_connector_state *c_state; struct sde_connector_state *c_state;
struct msm_display_mode *msm_mode; struct msm_display_mode *msm_mode;
struct sde_crtc *sde_crtc; struct sde_crtc *sde_crtc;
@@ -2669,6 +2672,16 @@ static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
if (ret) if (ret)
return; return;
crtc_state = sde_crtc->base.state;
sde_crtc_state = to_sde_crtc_state(crtc_state);
if ((sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_VIRTUAL) &&
((sde_crtc_state->cached_cwb_enc_mask & drm_encoder_mask(drm_enc)))) {
SDE_EVT32(DRMID(drm_enc), sde_crtc_state->cwb_enc_mask,
sde_crtc_state->cached_cwb_enc_mask);
sde_crtc_state->cwb_enc_mask = sde_crtc_state->cached_cwb_enc_mask;
sde_encoder_set_clone_mode(drm_enc, crtc_state);
}
/* reserve dynamic resources now, indicating non test-only */ /* reserve dynamic resources now, indicating non test-only */
ret = sde_rm_reserve(&sde_kms->rm, drm_enc, drm_enc->crtc->state, conn->state, false); ret = sde_rm_reserve(&sde_kms->rm, drm_enc, drm_enc->crtc->state, conn->state, false);
if (ret) { if (ret) {