From 520a2893dfb128b23bd3602e3b41b0a741536798 Mon Sep 17 00:00:00 2001 From: Maheshwar Ajja Date: Wed, 14 Dec 2022 09:49:38 -0800 Subject: [PATCH] video: iris33: ensure AON spare register to become zero Poll for AON spare register BIT(0) to become zero before asserting XO reset from video driver to ensure CVP/EVA driver is not asserting XO reset around the same time. Asserting XO reset by both driver at the same time may result in unpredictable behavior. Change-Id: I71a0bd0175ef7701c9a855abbf3c2e741d937dfb Signed-off-by: Maheshwar Ajja --- driver/variant/iris33/src/msm_vidc_iris33.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/driver/variant/iris33/src/msm_vidc_iris33.c b/driver/variant/iris33/src/msm_vidc_iris33.c index 70421da0af..162f8164c7 100644 --- a/driver/variant/iris33/src/msm_vidc_iris33.c +++ b/driver/variant/iris33/src/msm_vidc_iris33.c @@ -457,9 +457,13 @@ static int __power_off_iris33_controller(struct msm_vidc_core *core) if (rc) return rc; - rc = __read_register(core, AON_WRAPPER_SPARE, &value); - if (rc) - return rc; + /* poll AON spare register bit0 to become zero with 50ms timeout */ + rc = __read_register_with_poll_timeout(core, AON_WRAPPER_SPARE, + 0x1, 0x0, 1000, 50 * 1000); + if (rc) + d_vpr_e("%s: AON spare register is not zero\n", __func__); + + /* enable bit(1) to avoid cvp noc xo reset */ rc = __write_register(core, AON_WRAPPER_SPARE, value|0x2); if (rc) return rc; @@ -473,7 +477,7 @@ static int __power_off_iris33_controller(struct msm_vidc_core *core) rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_CORE_SW_RESET, 0x0, BIT(0)); if (rc) - return rc; + d_vpr_e("%s: MVP_NOC_CORE_SW_RESET failed\n", __func__); /* De-assert video_cc XO reset */ usleep_range(80, 100); @@ -481,6 +485,11 @@ static int __power_off_iris33_controller(struct msm_vidc_core *core) if (rc) d_vpr_e("%s: deassert video_xo_reset failed\n", __func__); + /* reset AON spare register */ + rc = __write_register(core, AON_WRAPPER_SPARE, 0x0); + if (rc) + return rc; + /* Enable MVP NoC clock */ rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL, 0x0, BIT(0));