fw-api: peach: E3.0: E3R44: WCSS_VERSION 2544 Add peach hw header files
Add HW header files to bring-in support for Peach WIFI. Change-Id: I73ee0a2c4f22a90013b441ecd5e666d673d77ae0 CRs-Fixed: 3580269
这个提交包含在：
Prakash Manjunathappa
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_
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#define _RECEIVED_TRIGGER_INFO_DETAILS_H_
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#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5
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struct received_trigger_info_details {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t trigger_type : 4,
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ax_trigger_source : 1,
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ax_trigger_type : 4,
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trigger_source_sta_full_aid : 13,
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frame_control_valid : 1,
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qos_control_valid : 1,
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he_control_info_valid : 1,
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__reserved_g_0005_trigger_subtype : 4,
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txop_sharing_mode : 2,
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tid_aggregation_limit_is_zero : 1;
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uint32_t phy_ppdu_id : 16,
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lsig_response_length : 12,
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reserved_1a : 4;
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uint32_t frame_control : 16,
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qos_control : 16;
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uint32_t sw_peer_id : 16,
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txop_sharing_allocation_duration : 9,
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reserved_3a : 7;
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uint32_t he_control : 32;
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#else
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uint32_t tid_aggregation_limit_is_zero : 1,
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txop_sharing_mode : 2,
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__reserved_g_0005_trigger_subtype : 4,
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he_control_info_valid : 1,
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qos_control_valid : 1,
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frame_control_valid : 1,
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trigger_source_sta_full_aid : 13,
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ax_trigger_type : 4,
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ax_trigger_source : 1,
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trigger_type : 4;
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uint32_t reserved_1a : 4,
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lsig_response_length : 12,
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phy_ppdu_id : 16;
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uint32_t qos_control : 16,
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frame_control : 16;
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uint32_t reserved_3a : 7,
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txop_sharing_allocation_duration : 9,
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sw_peer_id : 16;
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uint32_t he_control : 32;
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#endif
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};
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#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0
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#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3
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#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f
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#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4
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#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4
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#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010
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#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5
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#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8
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#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0
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#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9
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#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21
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#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00
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#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22
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#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22
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#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000
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#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23
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#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23
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#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000
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#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24
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#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24
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#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25
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#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28
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#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB 29
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#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB 30
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#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31
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#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31
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#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004
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#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
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#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15
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#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
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#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004
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#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16
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#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27
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#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000
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#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
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#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 28
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#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31
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#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0xf0000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008
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#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0
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#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15
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#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff
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#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008
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#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16
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#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31
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#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000
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#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c
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#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0
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#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15
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#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff
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#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c
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#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16
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#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24
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#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000
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#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c
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#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 25
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#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31
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#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xfe000000
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#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010
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#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0
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#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31
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#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff
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#endif
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