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cnss2: Dynamically use shadow regs for time_sync

For kiwi target the current code is using shadow_reg indexes 0,1. Change
the logic to use next two shadow registers of what is used by the host.

Change-Id: Ice95be0f2106078b8f799ca1182d1d8702b564c6
CRs-Fixed: 3218660
Mohit Khanna 2 ani în urmă
părinte
comite
2c3d91eed9
4 a modificat fișierele cu 16 adăugiri și 6 ștergeri
  1. 1 0
      cnss2/main.h
  2. 8 3
      cnss2/pci.c
  3. 5 2
      cnss2/qmi.c
  4. 2 1
      cnss2/reg.h

+ 1 - 0
cnss2/main.h

@@ -551,6 +551,7 @@ struct cnss_plat_data {
 	u16 hang_event_data_len;
 	u32 hang_data_addr_offset;
 	enum cnss_driver_mode driver_mode;
+	uint32_t num_shadow_regs_v3;
 };
 
 #if IS_ENABLED(CONFIG_ARCH_QCOM)

+ 8 - 3
cnss2/pci.c

@@ -2010,15 +2010,20 @@ static void cnss_pci_clear_time_sync_counter(struct cnss_pci_data *pci_priv)
 			   TIME_SYNC_CLEAR);
 }
 
+
 static void cnss_pci_time_sync_reg_update(struct cnss_pci_data *pci_priv,
 					  u32 low, u32 high)
 {
-	u32 time_reg_low = PCIE_SHADOW_REG_VALUE_0;
-	u32 time_reg_high = PCIE_SHADOW_REG_VALUE_1;
+	u32 time_reg_low;
+	u32 time_reg_high;
 
 	switch (pci_priv->device_id) {
 	case KIWI_DEVICE_ID:
-		/* Forward compatibility */
+		/* Use the next two shadow registers after host's usage */
+		time_reg_low = PCIE_SHADOW_REG_VALUE_0 +
+				(pci_priv->plat_priv->num_shadow_regs_v3 *
+				 SHADOW_REG_LEN_BYTES);
+		time_reg_high = time_reg_low + SHADOW_REG_LEN_BYTES;
 		break;
 	default:
 		time_reg_low = PCIE_SHADOW_REG_VALUE_34;

+ 5 - 2
cnss2/qmi.c

@@ -1582,8 +1582,6 @@ int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv,
 		       sizeof(struct wlfw_shadow_reg_v2_cfg_s_v01)
 		       * req->shadow_reg_v2_len);
 	} else {
-		cnss_pr_dbg("Shadow reg v3 len: %d\n",
-			    config->num_shadow_reg_v3_cfg);
 		req->shadow_reg_v3_valid = 1;
 		if (config->num_shadow_reg_v3_cfg >
 		    MAX_NUM_SHADOW_REG_V3)
@@ -1591,6 +1589,11 @@ int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv,
 		else
 			req->shadow_reg_v3_len = config->num_shadow_reg_v3_cfg;
 
+		plat_priv->num_shadow_regs_v3 = req->shadow_reg_v3_len;
+
+		cnss_pr_dbg("Shadow reg v3 len: %d\n",
+			    plat_priv->num_shadow_regs_v3);
+
 		memcpy(req->shadow_reg_v3, config->shadow_reg_v3_cfg,
 		       sizeof(struct wlfw_shadow_reg_v3_cfg_s_v01)
 		       * req->shadow_reg_v3_len);

+ 2 - 1
cnss2/reg.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CNSS_REG_H
@@ -52,6 +52,7 @@
 #define CE_REG_INTERVAL				0x2000
 
 #define SHADOW_REG_COUNT			36
+#define SHADOW_REG_LEN_BYTES			4
 #define PCIE_SHADOW_REG_VALUE_0			0x8FC
 #define PCIE_SHADOW_REG_VALUE_1			0x900
 #define PCIE_SHADOW_REG_VALUE_34		0x984