qcacmn: Replace A_TARGET_ACCESS_BEGIN/END_RET apis

Macros should not alter the execution of function bodies.

Change-Id: I54c90230c5c0f43cb20412110f4eb7aa568e654d
CRs-Fixed: 986480

hif/src/ce/ce_diag.c

@@ -191,10 +191,12 @@ hif_diag_read_mem(struct hif_opaque_softc *hif_ctx, uint32_t address,
 			 * to
 			 *    CE address space
 			 */
-			A_TARGET_ACCESS_BEGIN_RET(scn);
+			if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
+				return ATH_ISR_NOSCHED;
 			ce_phy_addr =
 				TARG_CPU_SPACE_TO_CE_SPACE(scn->mem, address);
-			A_TARGET_ACCESS_END_RET(scn);
+			if (Q_TARGET_ACCESS_END(scn) < 0)
+				return ATH_ISR_SCHED;
 
 			status =
 				ce_send(ce_diag, NULL, ce_phy_addr, nbytes,
@@ -273,9 +275,11 @@ QDF_STATUS hif_diag_read_access(struct hif_opaque_softc *hif_ctx,
 		return hif_diag_read_mem(hif_ctx, address, (uint8_t *) data,
 					 sizeof(uint32_t));
 	} else {
-		A_TARGET_ACCESS_BEGIN_RET(scn);
+		if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
+			return ATH_ISR_NOSCHED;
 		*data = A_TARGET_READ(scn, address);
-		A_TARGET_ACCESS_END_RET(scn);
+		if (Q_TARGET_ACCESS_END(scn) < 0)
+			return ATH_ISR_SCHED;
 
 		return QDF_STATUS_SUCCESS;
 	}
@@ -340,9 +344,11 @@ QDF_STATUS hif_diag_write_mem(struct hif_opaque_softc *hif_ctx,
 	 * to
 	 *    CE address space
 	 */
-	A_TARGET_ACCESS_BEGIN_RET(scn);
+	if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
+		return ATH_ISR_NOSCHED;
 	ce_phy_addr = TARG_CPU_SPACE_TO_CE_SPACE(scn->mem, address);
-	A_TARGET_ACCESS_END_RET(scn);
+	if (Q_TARGET_ACCESS_END(scn) < 0)
+		return ATH_ISR_SCHED;
 
 	remaining_bytes = orig_nbytes;
 	CE_data = CE_data_base;
@@ -448,9 +454,11 @@ QDF_STATUS hif_diag_write_access(struct hif_opaque_softc *hif_ctx,
 					  (uint8_t *) &data_buf,
 					  sizeof(uint32_t));
 	} else {
-		A_TARGET_ACCESS_BEGIN_RET(scn);
+		if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
+			return ATH_ISR_NOSCHED;
 		A_TARGET_WRITE(scn, address, data);
-		A_TARGET_ACCESS_END_RET(scn);
+		if (Q_TARGET_ACCESS_END(scn) < 0)
+			return ATH_ISR_SCHED;
 
 		return QDF_STATUS_SUCCESS;
 	}

hif/src/ce/ce_service.c

@@ -291,12 +291,14 @@ ce_send_nolock(struct CE_handle *copyeng,
 	uint64_t dma_addr = buffer;
 	struct hif_softc *scn = CE_state->scn;
 
-	A_TARGET_ACCESS_BEGIN_RET(scn);
+	if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
+		return ATH_ISR_NOSCHED;
 	if (unlikely(CE_RING_DELTA(nentries_mask,
 				write_index, sw_index - 1) <= 0)) {
 		OL_ATH_CE_PKT_ERROR_COUNT_INCR(scn, CE_RING_DELTA_FAIL);
 		status = QDF_STATUS_E_FAILURE;
-		A_TARGET_ACCESS_END_RET(scn);
+		if (Q_TARGET_ACCESS_END(scn) < 0)
+			return ATH_ISR_SCHED;
 		return status;
 	}
 	{
@@ -359,7 +361,8 @@ ce_send_nolock(struct CE_handle *copyeng,
 		src_ring->write_index = write_index;
 		status = QDF_STATUS_SUCCESS;
 	}
-	A_TARGET_ACCESS_END_RET(scn);
+	if (Q_TARGET_ACCESS_END(scn) < 0)
+		return ATH_ISR_SCHED;
 
 	return status;
 }
@@ -1032,10 +1035,12 @@ ce_completed_send_next_nolock(struct CE_state *CE_state,
 		 * the SW has really caught up to the HW, or if the cached
 		 * value of the HW index has become stale.
 		 */
-		A_TARGET_ACCESS_BEGIN_RET(scn);
+		if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
+			return ATH_ISR_NOSCHED;
 		src_ring->hw_index =
 			CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, ctrl_addr);
-		A_TARGET_ACCESS_END_RET(scn);
+		if (Q_TARGET_ACCESS_END(scn) < 0)
+			return ATH_ISR_SCHED;
 	}
 	read_index = src_ring->hw_index;
 

hif/src/hif_main.c

@@ -153,7 +153,8 @@ irqreturn_t hif_fw_interrupt_handler(int irq, void *arg)
 	struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn);
 	uint32_t fw_indicator_address, fw_indicator;
 
-	A_TARGET_ACCESS_BEGIN_RET(scn);
+	if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
+		return ATH_ISR_NOSCHED;
 
 	fw_indicator_address = hif_state->fw_indicator_address;
 	/* For sudden unplug this will return ~0 */
@@ -163,7 +164,8 @@ irqreturn_t hif_fw_interrupt_handler(int irq, void *arg)
 		/* ACK: clear Target-side pending event */
 		A_TARGET_WRITE(scn, fw_indicator_address,
 			       fw_indicator & ~FW_IND_EVENT_PENDING);
-		A_TARGET_ACCESS_END_RET(scn);
+		if (Q_TARGET_ACCESS_END(scn) < 0)
+			return ATH_ISR_SCHED;
 
 		if (hif_state->started) {
 			hif_fw_event_handler(hif_state);
@@ -177,7 +179,8 @@ irqreturn_t hif_fw_interrupt_handler(int irq, void *arg)
 				 __func__));
 		}
 	} else {
-		A_TARGET_ACCESS_END_RET(scn);
+		if (Q_TARGET_ACCESS_END(scn) < 0)
+			return ATH_ISR_SCHED;
 	}
 
 	return ATH_ISR_SCHED;

hif/src/pcie/hif_io32_pci.h

@@ -74,10 +74,6 @@
 
 #if CONFIG_ATH_PCIE_MAX_PERF
 
-#define A_TARGET_ACCESS_BEGIN_RET(scn) \
-	do {struct hif_softc *unused = scn; \
-	    unused = unused; } while (0)
-
 #define A_TARGET_ACCESS_BEGIN_RET_EXT(scn, val) \
 	do {struct hif_softc *unused = scn; \
 	    unused = unused; } while (0)
@@ -86,10 +82,6 @@
 	do {struct hif_softc *unused = scn; \
 	    unused = unused; } while (0)
 
-#define A_TARGET_ACCESS_END_RET(scn)	\
-	do {struct hif_softc *unused = scn; \
-		unused = unused; } while (0)
-
 #define A_TARGET_ACCESS_END_RET_EXT(scn, val) \
 	do {struct hif_softc *unused = scn; \
 	    unused = unused; } while (0)
@@ -108,24 +100,12 @@ do { \
 		val = -1; \
 } while (0)
 
-#define A_TARGET_ACCESS_BEGIN_RET(scn) \
-do { \
-	if (Q_TARGET_ACCESS_BEGIN(scn) < 0) \
-		return ATH_ISR_NOSCHED; \
-} while (0)
-
 #define A_TARGET_ACCESS_BEGIN_RET_PTR(scn) \
 do { \
 	if (Q_TARGET_ACCESS_BEGIN(scn) < 0) \
 		return NULL; \
 } while (0)
 
-#define A_TARGET_ACCESS_END_RET(scn)	\
-do { \
-	if (Q_TARGET_ACCESS_END(scn) < 0) \
-		return ATH_ISR_NOSCHED; \
-} while (0)
-
 #define A_TARGET_ACCESS_END_RET_EXT(scn, val) \
 do { \
 	if (Q_TARGET_ACCESS_END(scn) < 0) \

hif/src/pcie/if_pci.c

@@ -565,9 +565,11 @@ int hif_check_fw_reg(struct hif_opaque_softc *hif_ctx)
 	void __iomem *mem = sc->mem;
 	uint32_t val;
 
-	A_TARGET_ACCESS_BEGIN_RET(scn);
+	if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
+		return ATH_ISR_NOSCHED;
 	val = hif_read32_mb(mem + FW_INDICATOR_ADDRESS);
-	A_TARGET_ACCESS_END_RET(scn);
+	if (Q_TARGET_ACCESS_END(scn) < 0)
+		return ATH_ISR_SCHED;
 
 	HIF_INFO_MED("%s: FW_INDICATOR register is 0x%x", __func__, val);
 

hif/src/snoc/hif_io32_snoc.h

@@ -49,8 +49,6 @@
  */
 #define A_TARGET_ACCESS_BEGIN_RET_PTR(scn)
 #define A_TARGET_ACCESS_END_RET_PTR(scn)
-#define A_TARGET_ACCESS_BEGIN_RET(scn)
-#define A_TARGET_ACCESS_END_RET(scn)
 #define A_TARGET_ACCESS_BEGIN_RET_EXT(scn, val)
 #define A_TARGET_ACCESS_END_RET_EXT(scn, val)