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qcacmn: Add support for PPE

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Add the PPE related DP APIs

Change-Id: I25aeff73fef21a7a8ad0f0e6e8aa6c537a233029
CRs-Fixed: 3045340
This commit is contained in:
Neelansh Mittal
2021-12-03 19:41:17 +05:30
committed by Madan Koyyalamudi
parent bfde0ca01b
commit 2c06a656a5
5 changed files with 468 additions and 3 deletions
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50
dp/wifi3.0/be/dp_be.h
View File

@@ -107,6 +107,12 @@
/* get ppt_id from CMEM_OFFSET */
#define DP_CMEM_OFFSET_TO_PPT_ID(offset) \
((offset) / DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)
/* The MAX PPE PRI2TID */
#ifdef WLAN_SUPPORT_PPEDS
#define DP_TX_INT_PRI2TID_MAX 15
#endif
/**
* struct dp_spt_page_desc - secondary page table page descriptors
* @next: pointer to next linked SPT page Desc
@@ -169,6 +175,34 @@ struct dp_tx_bank_profile {
union hal_tx_bank_config bank_config;
};
#ifdef WLAN_SUPPORT_PPEDS
/**
* struct dp_ppe_vp_tbl_entry - PPE Virtual table entry
* @is_configured: Boolean that the entry is configured.
*/
struct dp_ppe_vp_tbl_entry {
bool is_configured;
};
/**
* struct dp_ppe_vp_profile - PPE direct switch profiler per vdev
* @vp_num: Virtual port number
* @ppe_vp_num_idx: Index to the PPE VP table entry
* @search_idx_reg_num: Address search Index register number
* @drop_prec_enable: Drop precedance enable
* @to_fw: To FW exception enable/disable.
* @use_ppe_int_pri: Use PPE INT_PRI to TID mapping table
*/
struct dp_ppe_vp_profile {
uint8_t vp_num;
uint8_t ppe_vp_num_idx;
uint8_t search_idx_reg_num;
uint8_t drop_prec_enable;
uint8_t to_fw;
uint8_t use_ppe_int_pri;
};
#endif
/**
* struct dp_soc_be - Extended DP soc for BE targets
* @soc: dp soc structure
@@ -184,6 +218,12 @@ struct dp_tx_bank_profile {
* @mld_peer_hash: peer hash table for ML peers
* Associated peer with this MAC address)
* @mld_peer_hash_lock: lock to protect mld_peer_hash
* @reo2ppe_ring: REO2PPE ring
* @ppe2tcl_ring: PPE2TCL ring
* @ppe_release_ring: PPE release ring
* @ppe_vp_tbl: PPE VP table
* @ppe_vp_tbl_lock: PPE VP table lock
* @num_ppe_vp_entries : Number of PPE VP entries
*/
struct dp_soc_be {
struct dp_soc soc;
@@ -202,6 +242,9 @@ struct dp_soc_be {
struct dp_srng reo2ppe_ring;
struct dp_srng ppe2tcl_ring;
struct dp_srng ppe_release_ring;
struct dp_ppe_vp_tbl_entry *ppe_vp_tbl;
qdf_mutex_t ppe_vp_tbl_lock;
uint8_t num_ppe_vp_entries;
#endif
#ifdef WLAN_FEATURE_11BE_MLO
#ifdef WLAN_MLO_MULTI_CHIP
@@ -242,12 +285,13 @@ struct dp_pdev_be {
* @vdev: dp vdev structure
* @bank_id: bank_id to be used for TX
* @vdev_id_check_en: flag if HW vdev_id check is enabled for vdev
* @ppe_vp_enabled: flag to check if PPE VP is enabled for vdev
* @ppe_vp_profile: PPE VP profile
*/
struct dp_vdev_be {
struct dp_vdev vdev;
int8_t bank_id;
uint8_t vdev_id_check_en;
#ifdef WLAN_MLO_MULTI_CHIP
/* partner list used for Intra-BSS */
uint8_t partner_vdev_list[WLAN_MAX_MLO_CHIPS][WLAN_MAX_MLO_LINKS_PER_SOC];
@@ -259,6 +303,10 @@ struct dp_vdev_be {
bool mcast_primary;
#endif
#endif
#endif
unsigned long ppe_vp_enabled;
#ifdef WLAN_SUPPORT_PPEDS
struct dp_ppe_vp_profile ppe_vp_profile;
#endif
};

118
hal/wifi3.0/be/hal_be_tx.h
View File

@@ -27,6 +27,12 @@
/* MAX_TCL_BANK reserved for FW use */
#define HAL_TX_NUM_RESERVED_BANKS 1
/*
* Number of Priority to TID mapping
*/
#define HAL_BE_TX_MAP0_PRI2TID_MAX 10
#define HAL_BE_TX_MAP1_PRI2TID_MAX 6
enum hal_be_tx_ret_buf_manager {
HAL_BE_WBM_SW0_BM_ID = 5,
HAL_BE_WBM_SW1_BM_ID = 6,
@@ -935,4 +941,116 @@ hal_tx_vdev_mismatch_routing_set(hal_soc_handle_t hal_soc_hdl,
{
}
#endif
/*
* hal_tx_get_num_ppe_vp_tbl_entries() - Get the total number of VP table
* @hal_soc: HAL SoC Context
*
* Return: Total number of entries.
*/
static inline
uint32_t hal_tx_get_num_ppe_vp_tbl_entries(hal_soc_handle_t hal_soc_hdl)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
return hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries(hal_soc_hdl);
}
/**
* hal_tx_set_ppe_cmn_cfg()- Set the PPE common config
* @hal_soc: HAL SoC context
* @cmn_cfg: HAL PPE VP common config
*
* Return: void
*/
static inline void
hal_tx_set_ppe_cmn_cfg(hal_soc_handle_t hal_soc_hdl,
union hal_tx_cmn_config_ppe *cmn_cfg)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
hal_soc->ops->hal_tx_set_ppe_cmn_cfg(hal_soc_hdl, cmn_cfg);
}
/**
* hal_tx_populate_ppe_vp_entry - Populate ppe VP entry
* @hal_soc: HAL SoC context
* @vp_cfg: HAL PPE VP config
* @ppe_vp_idx: PPE VP index
*
* Return: void
*/
static inline void
hal_tx_populate_ppe_vp_entry(hal_soc_handle_t hal_soc_hdl,
union hal_tx_ppe_vp_config *vp_cfg,
int ppe_vp_idx)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
hal_soc->ops->hal_tx_set_ppe_vp_entry(hal_soc_hdl, vp_cfg, ppe_vp_idx);
}
/**
* hal_tx_set_int_pri2id - Set the prit2tid table.
* @hal_soc: HAL SoC context
* @pri2tid: Reference to SW INT_PRI to TID table
*
* Return: void
*/
static inline void
hal_tx_set_int_pri2tid(hal_soc_handle_t hal_soc_hdl,
uint32_t val, uint8_t map_no)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
hal_soc->ops->hal_tx_set_ppe_pri2tid(hal_soc_hdl, val, map_no);
}
/**
* hal_tx_update_int_pri2id - Populate the prit2tid table.
* @hal_soc: HAL SoC context
* @pri: INT_PRI value
* @tid: Wi-Fi TID
*
* Return: void
*/
static inline void
hal_tx_update_int_pri2tid(hal_soc_handle_t hal_soc_hdl,
uint8_t pri, uint8_t tid)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
hal_soc->ops->hal_tx_update_ppe_pri2tid(hal_soc_hdl, pri, tid);
}
/**
* hal_tx_dump_ppe_vp_entry - Dump the PPE VP entry
* @hal_soc_hdl: HAL SoC context
*
* Return: void
*/
static inline void
hal_tx_dump_ppe_vp_entry(hal_soc_handle_t hal_soc_hdl)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
hal_soc->ops->hal_tx_dump_ppe_vp_entry(hal_soc_hdl);
}
/**
* hal_tx_enable_pri2tid_map- Enable the priority to tid mapping
* @hal_soc_hdl: HAL SoC context
* @val: True/False value
*
* Return: void
*/
static inline void
hal_tx_enable_pri2tid_map(hal_soc_handle_t hal_soc_hdl, bool val,
uint8_t ppe_vp_idx)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
hal_soc->ops->hal_tx_enable_pri2tid_map(hal_soc_hdl, val,
ppe_vp_idx);
}
#endif /* _HAL_BE_TX_H_ */

22
hal/wifi3.0/hal_internal.h
View File

@@ -139,6 +139,12 @@ typedef struct hal_buf_info *hal_buf_info_t;
struct rx_msdu_desc_info;
typedef struct rx_msdu_desc_info *rx_msdu_desc_info_t;
/**
* Opaque hanlder for PPE VP config.
*/
union hal_tx_ppe_vp_config;
union hal_tx_cmn_config_ppe;
/* TBD: This should be movded to shared HW header file */
enum hal_srng_ring_id {
/* UMAC rings */
@@ -778,6 +784,22 @@ struct hal_hw_txrx_ops {
void (*hal_tx_init_cmd_credit_ring)(hal_soc_handle_t hal_soc_hdl,
hal_ring_handle_t hal_ring_hdl);
uint32_t (*hal_tx_comp_get_buffer_source)(void *hal_desc);
uint32_t (*hal_tx_get_num_ppe_vp_tbl_entries)(
hal_soc_handle_t hal_soc_hdl);
void (*hal_tx_set_ppe_cmn_cfg)(hal_soc_handle_t hal_soc_hdl,
union hal_tx_cmn_config_ppe *cmn_cfg);
void (*hal_tx_set_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl,
union hal_tx_ppe_vp_config *vp_cfg,
int ppe_vp_idx);
void (*hal_tx_set_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl,
uint32_t val,
uint8_t map_no);
void (*hal_tx_update_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl,
uint8_t pri,
uint8_t tid);
void (*hal_tx_dump_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl);
void (*hal_tx_enable_pri2tid_map)(hal_soc_handle_t hal_soc_hdl,
bool value, uint8_t ppe_vp_idx);
/* rx */
uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *);

53
hal/wifi3.0/qcn9224/hal_9224.c
View File

@@ -691,6 +691,7 @@ typedef struct rx_msdu_end_compact_qca9224 hal_rx_msdu_end_t;
#include <hal_be_generic_api.h>
#define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
#define HAL_PPE_VP_ENTRIES_MAX 32
/**
* hal_get_link_desc_size_9224(): API to get the link desc size
*
@@ -1478,6 +1479,28 @@ static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs,
sizeof(pkt_hdr_tlv->rx_pkt_hdr));
}
/*
* hal_tx_dump_ppe_vp_entry_9224()
* @hal_soc_hdl: HAL SoC handle
*
* Return: void
*/
static inline
void hal_tx_dump_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl)
{
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
uint32_t reg_addr, reg_val = 0, i;
for (i = 0; i < HAL_PPE_VP_ENTRIES_MAX; i++) {
reg_addr =
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(
MAC_TCL_REG_REG_BASE,
i);
reg_val = HAL_REG_READ(soc, reg_addr);
hal_verbose_debug("%d: 0x%x\n", i, reg_val);
}
}
/**
* hal_rx_dump_pkt_tlvs_9224(): API to print RX Pkt TLVS QCN9224
* @hal_soc_hdl: hal_soc handle
@@ -1676,6 +1699,18 @@ static uint32_t hal_qcn9224_get_reo_qdesc_size(uint32_t ba_window_size, int tid)
sizeof(struct rx_reo_queue_1k);
}
/*
* hal_tx_dump_ppe_vp_entry_9224()
* @hal_soc_hdl: HAL SoC handle
*
* Return: Number of PPE VP entries
*/
static
uint32_t hal_tx_get_num_ppe_vp_tbl_entries_9224(hal_soc_handle_t hal_soc_hdl)
{
return HAL_PPE_VP_ENTRIES_MAX;
}
static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
{
/* init and setup */
@@ -1689,9 +1724,23 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9224;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9224;
hal_soc->ops->hal_tx_comp_get_status =
hal_tx_comp_get_status_generic_be;
hal_tx_comp_get_status_generic_be;
hal_soc->ops->hal_tx_init_cmd_credit_ring =
hal_tx_init_cmd_credit_ring_9224;
hal_tx_init_cmd_credit_ring_9224;
hal_soc->ops->hal_tx_set_ppe_cmn_cfg =
hal_tx_set_ppe_cmn_config_9224;
hal_soc->ops->hal_tx_set_ppe_vp_entry =
hal_tx_set_ppe_vp_entry_9224;
hal_soc->ops->hal_tx_set_ppe_pri2tid =
hal_tx_set_ppe_pri2tid_map_9224;
hal_soc->ops->hal_tx_update_ppe_pri2tid =
hal_tx_update_ppe_pri2tid_9224;
hal_soc->ops->hal_tx_dump_ppe_vp_entry =
hal_tx_dump_ppe_vp_entry_9224;
hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries =
hal_tx_get_num_ppe_vp_tbl_entries_9224;
hal_soc->ops->hal_tx_enable_pri2tid_map =
hal_tx_enable_pri2tid_map_9224;
/* rx */
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be;

228
hal/wifi3.0/qcn9224/hal_9224_tx.h
View File

@@ -26,6 +26,7 @@
#include "hal_rx.h"
#include "hal_tx.h"
#include "hal_api_mon.h"
#include <hal_be_tx.h>
#define DSCP_TID_TABLE_SIZE 24
#define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
@@ -226,4 +227,231 @@ struct tx_fes_setup_compact_9224 {
};
#endif
#endif /* QCA_MONITOR_2_0_SUPPORT */
/**
* hal_tx_set_ppe_cmn_config_9224() - Set the PPE common config register
* @hal_soc_hdl: HAL SoC handle
* @cmn_cfg: Common PPE config
*
* Based on the PPE2TCL descriptor below errors, if the below register
* values are set then the packets are forward to Tx rule handler if 1'0b
* or to TCL exit base if 1'1b.
*
* Return: void
*/
static inline
void hal_tx_set_ppe_cmn_config_9224(hal_soc_handle_t hal_soc_hdl,
union hal_tx_cmn_config_ppe *cmn_cfg)
{
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
union hal_tx_cmn_config_ppe *cfg =
(union hal_tx_cmn_config_ppe *)cmn_cfg;
uint32_t reg_addr, reg_val = 0;
reg_addr = HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(MAC_TCL_REG_REG_BASE);
reg_val = HAL_REG_READ(soc, reg_addr);
reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK;
reg_val |=
(cfg->drop_prec_err &
HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK) <<
HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_SHFT;
reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK;
reg_val |=
(cfg->fake_mac_hdr &
HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK) <<
HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_SHFT;
reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK;
reg_val |=
(cfg->cpu_code_inv &
HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK) <<
HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_SHFT;
reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK;
reg_val |=
(cfg->l3_l4_err &
HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK) <<
HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_SHFT;
HAL_REG_WRITE(soc, reg_addr, reg_val);
}
/**
* hal_tx_set_ppe_vp_entry_9224() - Set the PPE VP entry
* @hal_soc_hdl: HAL SoC handle
* @vp_cfg: PPE VP config
* @ppe_vp_idx : PPE VP index to the table
*
* Return: void
*/
static inline
void hal_tx_set_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl,
union hal_tx_ppe_vp_config *cfg,
int ppe_vp_idx)
{
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
uint32_t reg_addr, reg_val = 0;
reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
ppe_vp_idx);
/*
* Drop precedence is enabled by default.
*/
reg_val = HAL_REG_READ(soc, reg_addr);
reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_BMSK;
reg_val |= (cfg->vp_num &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_SHFT;
reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_BMSK;
reg_val |= (cfg->pmac_id &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_SHFT;
reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_BMSK;
reg_val |= (cfg->bank_id &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_SHFT;
reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_BMSK;
reg_val |= (cfg->vdev_id &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_SHFT;
reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_BMSK;
reg_val |=
(cfg->search_idx_reg_num &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_SHFT;
reg_val &=
~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK;
reg_val |=
(cfg->use_ppe_int_pri &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT;
reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_BMSK;
reg_val |= (cfg->to_fw &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_SHFT;
reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_BMSK;
reg_val |= (cfg->drop_prec_enable &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_SHFT;
HAL_REG_WRITE(soc, reg_addr, reg_val);
}
/**
* hal_tx_set_ppe_pri2tid_map1_9224()
* @hal_soc_hdl: HAL SoC handle
* @val : PRI to TID value
* @map_no: Map number
*
* Return: void
*/
static inline
void hal_tx_set_ppe_pri2tid_map_9224(hal_soc_handle_t hal_soc_hdl,
uint32_t val, uint8_t map_no)
{
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
uint32_t reg_addr, reg_val = 0;
if (map_no == 0)
reg_addr =
HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE);
else
reg_addr =
HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE);
reg_val |= val;
HAL_REG_WRITE(soc, reg_addr, reg_val);
}
/**
* hal_tx_set_ppe_pri2tid_map1_9224()
* @hal_soc_hdl: HAL SoC handle
* @val : PRI to TID value
* @map_no: Map number
*
* Return: void
*/
static inline
void hal_tx_enable_pri2tid_map_9224(hal_soc_handle_t hal_soc_hdl,
bool val, uint8_t ppe_vp_idx)
{
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
uint32_t reg_addr, reg_val = 0;
reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
ppe_vp_idx);
/*
* Drop precedence is enabled by default.
*/
reg_val = HAL_REG_READ(soc, reg_addr);
reg_val &=
~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK;
reg_val |=
(val &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT;
HAL_REG_WRITE(soc, reg_addr, reg_val);
}
/**
* hal_tx_update_ppe_pri2tid_9224()
* @hal_soc_hdl: HAL SoC handle
* @pri: INT_PRI
* @tid: Wi-Fi TID
*
* Return: void
*/
static inline
void hal_tx_update_ppe_pri2tid_9224(hal_soc_handle_t hal_soc_hdl,
uint8_t pri, uint8_t tid)
{
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
uint32_t reg_addr, reg_val = 0, mask, shift;
/*
* INT_PRI 0..9 is in MAP0 register and INT_PRI 10..15
* is in MAP1 register.
*/
switch (pri) {
case 0 ... 9:
reg_addr =
HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE);
mask =
(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_BMSK << (0x3 * pri));
shift = HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_SHFT + (pri * 0x3);
break;
case 10 ... 15:
pri = pri - 10;
reg_addr =
HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE);
mask =
(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_BMSK << (0x3 * pri));
shift =
HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_SHFT + (pri * 0x3);
break;
default:
return;
}
reg_val = HAL_REG_READ(soc, reg_addr);
reg_val &= ~mask;
reg_val |= (pri << shift) & mask;
HAL_REG_WRITE(soc, reg_addr, reg_val);
}
#endif /* _HAL_9224_TX_H_ */