FF: Upto PC665: Merge tag 'camera-kernel.lnx.5.0-211101.1' into 6.0

* tag 'camera-kernel.lnx.5.0-211101.1':
  msm: camera: cdm: Fix incorrect condition in cdm code
  msm: camera: isp: Add YUV format as supported format
  msm: camera: isp: Force all IFE lite RDIs to line based
  msm: camera: isp: Additional fixes for KMD internal recovery
  msm: camera: cdm: handle dead lock scenario
  msm: camera: sensor: Remove NULL set for regulator phandle
  msm: camera: isp: Rearrange the rt-wrapper-base property
  msm: camera: isp: Handle error event notification to HW manager
  msm: camera: cdm: Fix cdm bl submit function
  msm: camera: isp: Update right out resource for PDAF parsed outport
  msm: camera: isp: Add SOF Retiming Disable Support
  msm: camera: isp: Enable line smoothing in RDI path for CSID 780
  msm: camera: isp: Add support for RDI LCR
  msm: camera: isp: Add new CDM BL Type
  msm: camera: csid: Fix excessive logging in CSID
  msm: camera: common: Update the ctx memory request logic
  msm: camera: csiphy: Add proper check for combo mode
  msm: camera: common: Fix kernel code and add checks
  msm: camera: isp: Add recovery support for custom AEB use-case
  msm: camera: cre: add degug fs entry to update clock rate
  msm: camera: core: Delete request from pending list in case of error
  msm: camera: csiphy: Update the csiphy bringup sequence
  msm: camera: csiphy: Enable PN9 infinite loop for test
  msm: camera: isp: Update reapply field in config args
  msm: camera: isp: Add common utility functions
  msm: camera: isp: Split event handler based on HW type
  msm: camera: isp: Apply scratch only on SOF trigger
  msm: camera: common: Add wrapper for presil locking
  msm: camera: isp: Fix BW voting corruption in top layer
  msm: camera: isp: Handle RUP for enabled CSID CAMIF IRQs
  msm: camera: reqmgr: Fix the crm driver
  msm: camera: cdm: Fix cdm driver for bufffer excursion
  msm: camera: common: fix map check failure for presil buffer send
  msm: camera: cpas: Add support for Diwali Camera
  msm: camera: uapi: Add new event causes
  msm: camera: isp: Add bw info dump on clk/bw update error
  msm: camera: common: Make msg_cb for cam_subdev generic
  msm: camera: req_mgr: Rearrange state change sequence
  msm: camera: isp: Add header file VFE and CSID for Diwali
  msm: camera: csiphy: Extend CSIPHY hw block support
  msm: camera: icp: send freq to ICP firmware
  msm: camera: cci: Increase HW block support for CCI
  msm: camera: isp: shdr enable pdaf occur overflow
  msm: camera: cdm: Correct the CDM iommu handle
  msm: camera: isp: Update last applied MUP for scratch
  msm: camera: reqmgr: Only do self correction after initial sync
  msm: camera: common: Add presil compilation and probe support
  msm: camera: ife: Program image addr for once in RDI batch mode
  msm: camera: icp: add mechanism to send/receive buffer for presil

Change-Id: Ib959b746db64825cc735fa80ddd5e79200c102a8
Signed-off-by: Abhijit Trivedi <[email protected]>

Kbuild

@@ -34,6 +34,10 @@ ifeq ($(CONFIG_ARCH_SHIMA), y)
 include $(CAMERA_KERNEL_ROOT)/config/shima.mk
 endif
 
+ifeq ($(CONFIG_ARCH_DIWALI), y)
+include $(CAMERA_KERNEL_ROOT)/config/diwali.mk
+endif
+
 # List of all camera-kernel headers
 cam_include_dirs := $(shell dirname `find $(CAMERA_KERNEL_ROOT) -name '*.h'` | uniq)
 
@@ -90,6 +94,8 @@ ifeq (,$(filter $(CONFIG_CAM_PRESIL),y m))
 	camera-y += drivers/cam_utils/cam_io_util.o
 else
 	camera-y += drivers/cam_presil/presil/cam_presil_io_util.o
+	camera-y += drivers/cam_presil/presil/cam_presil_hw_access.o
+	camera-y += drivers/cam_presil/presil_framework_dev/cam_presil_framework_dev.o
 	ccflags-y += -DCONFIG_CAM_PRESIL=1
 endif
 

config/diwali.mk

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Settings for compiling diwali camera architecture
+
+# Localized KCONFIG settings
+CONFIG_SPECTRA_ISP := y
+CONFIG_SPECTRA_ICP := y
+CONFIG_SPECTRA_JPEG := y
+CONFIG_SPECTRA_SENSOR := y
+
+# Flags to pass into C preprocessor
+ccflags-y += -DCONFIG_SPECTRA_ISP=1
+ccflags-y += -DCONFIG_SPECTRA_ICP=1
+ccflags-y += -DCONFIG_SPECTRA_JPEG=1
+ccflags-y += -DCONFIG_SPECTRA_SENSOR=1

drivers/cam_cdm/cam_cdm.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_CDM_H_
@@ -132,14 +132,6 @@
 	 CAM_CDM_IRQ_STATUS_ERROR_OVER_FLOW_MASK | \
 	 CAM_CDM_IRQ_STATUS_ERROR_AHB_BUS_MASK)
 
-
-struct cam_cdm_pid_mid_data {
-	int cdm_pid;
-	int cdm_mid;
-	int ope_cdm_pid;
-	int ope_cdm_mid;
-};
-
 /* Structure to store hw version info */
 struct cam_version_reg {
 	uint32_t hw_version;
@@ -383,7 +375,6 @@ struct cam_cdm_common_regs {
 	const struct cam_cdm_icl_regs *icl_reg;
 	uint32_t spare;
 	uint32_t priority_group_bit_offset;
-	struct cam_cdm_pid_mid_data *cdm_pid_mid_info;
 };
 
 /**
@@ -570,6 +561,8 @@ struct cam_cdm_private_dt_data {
 	uint8_t priority_group;
 	uint32_t fifo_depth[CAM_CDM_BL_FIFO_MAX];
 	uint32_t dt_num_supported_clients;
+	uint32_t pid;
+	uint32_t mid;
 	const char *dt_cdm_client_name[CAM_PER_CDM_MAX_REGISTERED_CLIENTS];
 };
 

drivers/cam_cdm/cam_cdm_core_common.c

@@ -180,12 +180,10 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw,
 			(struct cam_cdm_bl_cb_request_entry *)data;
 
 		client_idx = CAM_CDM_GET_CLIENT_IDX(node->client_hdl);
-		mutex_lock(&cdm_hw->hw_mutex);
 		client = core->clients[client_idx];
 		if ((!client) || (client->handle != node->client_hdl)) {
 			CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x", client,
 				node->client_hdl);
-			mutex_unlock(&cdm_hw->hw_mutex);
 			return;
 		}
 		cam_cdm_get_client_refcount(client);
@@ -204,7 +202,6 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw,
 		}
 		mutex_unlock(&client->lock);
 		cam_cdm_put_client_refcount(client);
-		mutex_unlock(&cdm_hw->hw_mutex);
 		return;
 	} else if (status == CAM_CDM_CB_STATUS_HW_RESET_DONE ||
 			status == CAM_CDM_CB_STATUS_HW_FLUSH ||
@@ -242,7 +239,6 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw,
 
 	for (i = 0; i < CAM_PER_CDM_MAX_REGISTERED_CLIENTS; i++) {
 		if (core->clients[i] != NULL) {
-			mutex_lock(&cdm_hw->hw_mutex);
 			client = core->clients[i];
 			cam_cdm_get_client_refcount(client);
 			mutex_lock(&client->lock);
@@ -265,7 +261,6 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw,
 			}
 			mutex_unlock(&client->lock);
 			cam_cdm_put_client_refcount(client);
-			mutex_unlock(&cdm_hw->hw_mutex);
 		}
 	}
 }
@@ -285,27 +280,18 @@ static int cam_cdm_stream_handle_init(void *hw_priv, bool init)
 			return rc;
 		}
 
-		if (core->arbitration !=
-			CAM_CDM_ARBITRATION_PRIORITY_BASED) {
-			rc = cam_hw_cdm_alloc_genirq_mem(
-				hw_priv);
-			if (rc) {
-				CAM_ERR(CAM_CDM,
-					"Genirqalloc failed");
-				cam_hw_cdm_deinit(hw_priv,
-					NULL, 0);
-			}
+		rc = cam_hw_cdm_alloc_genirq_mem(hw_priv);
+		if (rc) {
+			CAM_ERR(CAM_CDM, "Genirqalloc failed");
+			cam_hw_cdm_deinit(hw_priv, NULL, 0);
 		}
 	} else {
 		rc = cam_hw_cdm_deinit(hw_priv, NULL, 0);
 		if (rc)
 			CAM_ERR(CAM_CDM, "Deinit failed in streamoff");
 
-		if (core->arbitration !=
-			CAM_CDM_ARBITRATION_PRIORITY_BASED) {
-			if (cam_hw_cdm_release_genirq_mem(hw_priv))
-				CAM_ERR(CAM_CDM, "Genirq release fail");
-		}
+		if (cam_hw_cdm_release_genirq_mem(hw_priv))
+			CAM_ERR(CAM_CDM, "Genirq release fail");
 	}
 
 	return rc;
@@ -509,7 +495,7 @@ int cam_cdm_process_cmd(void *hw_priv,
 			break;
 		}
 		cam_cdm_get_client_refcount(client);
-		if ((req->data->flag == true) &&
+		if (req->data->flag &&
 			(!client->data.cam_cdm_callback)) {
 			CAM_ERR(CAM_CDM,
 				"CDM request cb without registering cb");

drivers/cam_cdm/cam_cdm_hw_core.c

@@ -28,8 +28,13 @@
 #include "cam_req_mgr_workq.h"
 #include "cam_common_util.h"
 
-#define CAM_CDM_BL_FIFO_WAIT_TIMEOUT 2000
-#define CAM_CDM_DBG_GEN_IRQ_USR_DATA 0xff
+#define CAM_CDM_BL_FIFO_WAIT_TIMEOUT         2000
+#define CAM_CDM_DBG_GEN_IRQ_USR_DATA         0xff
+#define CAM_CDM_MAX_BL_LENGTH                0x100000
+#define CAM_CDM_FIFO_LEN_REG_LEN_MASK        0xFFFFF
+#define CAM_CDM_FIFO_LEN_REG_TAG_MASK        0xFF
+#define CAM_CDM_FIFO_LEN_REG_TAG_SHIFT       24
+#define CAM_CDM_FIFO_LEN_REG_ARB_SHIFT       20
 
 static void cam_hw_cdm_work(struct work_struct *work);
 
@@ -675,8 +680,7 @@ int cam_hw_cdm_wait_for_bl_fifo(
 	bl_fifo = &core->bl_fifo[fifo_idx];
 
 	do {
-		if (cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo(
-				cdm_hw, fifo_idx, &pending_bl)) {
+		if (cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo(cdm_hw, fifo_idx, &pending_bl)) {
 			CAM_ERR(CAM_CDM, "Failed to read CDM pending BL's");
 			rc = -EIO;
 			break;
@@ -737,6 +741,10 @@ bool cam_hw_cdm_bl_write(
 {
 	struct cam_cdm *cdm_core = (struct cam_cdm *)cdm_hw->core_info;
 
+	CAM_DBG(CAM_CDM, "%s%d Base: 0x%x, Len: %u, Tag: %u, set_arb: %u, fifo_idx: %u",
+		cdm_hw->soc_info.label_name, cdm_hw->soc_info.index,
+		src, len, tag, set_arb, fifo_idx);
+
 	if (cam_cdm_write_hw_reg(cdm_hw,
 		cdm_core->offsets->bl_fifo_reg[fifo_idx]->bl_fifo_base,
 		src)) {
@@ -745,8 +753,9 @@ bool cam_hw_cdm_bl_write(
 	}
 	if (cam_cdm_write_hw_reg(cdm_hw,
 		cdm_core->offsets->bl_fifo_reg[fifo_idx]->bl_fifo_len,
-		((len & 0xFFFFF) | ((tag & 0xFF) << 24)) |
-		((set_arb) ? (1 << 20) : (0)))) {
+		((len & CAM_CDM_FIFO_LEN_REG_LEN_MASK) |
+			((tag & CAM_CDM_FIFO_LEN_REG_TAG_MASK) << CAM_CDM_FIFO_LEN_REG_TAG_SHIFT)) |
+			((set_arb) ? (1 << CAM_CDM_FIFO_LEN_REG_ARB_SHIFT) : (0)))) {
 		CAM_ERR(CAM_CDM, "Failed to write CDM BL len");
 		return true;
 	}
@@ -906,103 +915,16 @@ end:
 	return rc;
 }
 
-static int cam_hw_cdm_arb_submit_bl(struct cam_hw_info *cdm_hw,
-	struct cam_cdm_hw_intf_cmd_submit_bl *req, int i,
-	uint32_t fifo_idx, dma_addr_t hw_vaddr_ptr)
-{
-	struct cam_cdm_bl_request *cdm_cmd = req->data;
-	struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info;
-	uintptr_t cpu_addr;
-	struct cam_cdm_bl_cb_request_entry *node;
-	int rc = 0;
-	size_t len = 0;
-
-	node = kzalloc(sizeof(
-		struct cam_cdm_bl_cb_request_entry),
-		GFP_KERNEL);
-	if (!node)
-		return -ENOMEM;
-
-	node->request_type = CAM_HW_CDM_BL_CB_CLIENT;
-	node->client_hdl = req->handle;
-	node->cookie = req->data->cookie;
-	node->bl_tag = core->bl_fifo[fifo_idx].bl_tag -
-		1;
-	node->userdata = req->data->userdata;
-	list_add_tail(&node->entry,
-		&core->bl_fifo[fifo_idx]
-		.bl_request_list);
-	cdm_cmd->cmd[i].arbitrate = true;
-	rc = cam_mem_get_cpu_buf(
-		cdm_cmd->cmd[i].bl_addr.mem_handle,
-		&cpu_addr, &len);
-	if (rc || !cpu_addr) {
-		CAM_ERR(CAM_OPE, "get cmd buffailed %x",
-			cdm_cmd->cmd[i].bl_addr
-			.mem_handle);
-		return rc;
-	}
-	core->ops->cdm_write_genirq(
-		((uint32_t *)cpu_addr +
-		cdm_cmd->cmd[i].offset / 4 +
-		cdm_cmd->cmd[i].len / 4),
-		core->bl_fifo[fifo_idx].bl_tag - 1,
-		1, fifo_idx);
-	rc = cam_hw_cdm_bl_write(cdm_hw,
-		(uint32_t)hw_vaddr_ptr +
-		cdm_cmd->cmd[i].offset,
-		cdm_cmd->cmd[i].len + 7,
-		core->bl_fifo[fifo_idx].bl_tag - 1,
-		1, fifo_idx);
-	if (rc) {
-		CAM_ERR(CAM_CDM,
-			"CDM hw bl write failed tag=%d",
-			core->bl_fifo[fifo_idx].bl_tag -
-			1);
-			list_del_init(&node->entry);
-			kfree(node);
-			return -EIO;
-	}
-
-	if (cam_presil_mode_enabled()) {
-		CAM_DBG(CAM_PRESIL,
-			"Sending CDM arb cmd buffer:%d with iommu_hdl:%d",
-			cdm_cmd->cmd[i].bl_addr.mem_handle, core->iommu_hdl.non_secure);
-
-		rc = cam_mem_mgr_send_buffer_to_presil(core->iommu_hdl.non_secure,
-			cdm_cmd->cmd[i].bl_addr.mem_handle);
-		if (rc) {
-			CAM_ERR(CAM_PRESIL,
-				"Failed to send CDM arb cmd buffer i:%d mem_handle:%d rc:%d",
-				i, cdm_cmd->cmd[i].bl_addr.mem_handle, rc);
-			return rc;
-		}
-	}
-
-	rc = cam_hw_cdm_commit_bl_write(cdm_hw,
-		fifo_idx);
-	if (rc) {
-		CAM_ERR(CAM_CDM,
-			"CDM hw commit failed tag=%d",
-			core->bl_fifo[fifo_idx].bl_tag -
-			1);
-			list_del_init(&node->entry);
-			kfree(node);
-			return -EIO;
-	}
-
-	return 0;
-}
-
 int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
 	struct cam_cdm_hw_intf_cmd_submit_bl *req,
 	struct cam_cdm_client *client)
 {
-	int i, rc;
+	unsigned int i;
+	int rc = 0;
 	struct cam_cdm_bl_request *cdm_cmd = req->data;
 	struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info;
 	struct cam_cdm_bl_fifo *bl_fifo = NULL;
-	uint32_t pending_bl = 0, fifo_idx = 0;
+	uint32_t fifo_idx = 0;
 	int write_count = 0;
 
 	fifo_idx = CAM_CDM_GET_BLFIFO_IDX(client->handle);
@@ -1025,7 +947,6 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
 			bl_fifo->bl_depth);
 	}
 
-
 	mutex_lock(&core->bl_fifo[fifo_idx].fifo_lock);
 	mutex_lock(&client->lock);
 
@@ -1036,24 +957,13 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
 		return -EAGAIN;
 	}
 
-	rc = cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo(cdm_hw,
-		fifo_idx, &pending_bl);
-
-	if (rc) {
-		CAM_ERR(CAM_CDM, "Cannot read the current BL depth");
-		mutex_unlock(&client->lock);
-		mutex_unlock(&core->bl_fifo[fifo_idx].fifo_lock);
-		return rc;
-	}
-
 	for (i = 0; i < req->data->cmd_arrary_count ; i++) {
 		dma_addr_t hw_vaddr_ptr = 0;
 		size_t len = 0;
 
-		if ((!cdm_cmd->cmd[i].len) &&
-			(cdm_cmd->cmd[i].len > 0x100000)) {
+		if ((!cdm_cmd->cmd[i].len) || (cdm_cmd->cmd[i].len > CAM_CDM_MAX_BL_LENGTH)) {
 			CAM_ERR(CAM_CDM,
-				"cmd len(%d) is invalid cnt=%d total cnt=%d",
+				"cmd len=: %d is invalid_ent: %d, num_cmd_ent: %d",
 				cdm_cmd->cmd[i].len, i,
 				req->data->cmd_arrary_count);
 			rc = -EINVAL;
@@ -1074,29 +984,32 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
 				(req->data->cmd_arrary_count - i), fifo_idx);
 			if (write_count < 0) {
 				CAM_ERR(CAM_CDM,
-					"wait for bl fifo failed %d:%d",
-					i, req->data->cmd_arrary_count);
+					"wait for bl fifo failed for ent: %u", i);
 				rc = -EIO;
 				break;
 			}
 		}
 
 		if (req->data->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE) {
-			rc = cam_mem_get_io_buf(
-				cdm_cmd->cmd[i].bl_addr.mem_handle,
+			rc = cam_mem_get_io_buf(cdm_cmd->cmd[i].bl_addr.mem_handle,
 				core->iommu_hdl.non_secure, &hw_vaddr_ptr,
 				&len, NULL);
+			if (rc) {
+				CAM_ERR(CAM_CDM,
+					"Getting a hwva from mem_hdl failed. rc: %d, cmd_ent: %u",
+					rc, i);
+				rc = -EINVAL;
+				break;
+			}
 		} else if (req->data->type == CAM_CDM_BL_CMD_TYPE_HW_IOVA) {
 			if (!cdm_cmd->cmd[i].bl_addr.hw_iova) {
-				CAM_ERR(CAM_CDM,
-					"Hw bl hw_iova is invalid %d:%d",
-					i, req->data->cmd_arrary_count);
+				CAM_ERR(CAM_CDM, "hw_iova is null for ent: %d", i);
 				rc = -EINVAL;
 				break;
 			}
+
 			rc = 0;
-			hw_vaddr_ptr =
-				(dma_addr_t)cdm_cmd->cmd[i].bl_addr.hw_iova;
+			hw_vaddr_ptr = (dma_addr_t)cdm_cmd->cmd[i].bl_addr.hw_iova;
 			len = cdm_cmd->cmd[i].len + cdm_cmd->cmd[i].offset;
 		} else {
 			CAM_ERR(CAM_CDM,
@@ -1106,11 +1019,8 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
 			break;
 		}
 
-		if ((!rc) && (hw_vaddr_ptr) && (len) &&
-			(len >= cdm_cmd->cmd[i].offset)) {
-
-			if ((len - cdm_cmd->cmd[i].offset) <
-				cdm_cmd->cmd[i].len) {
+		if ((hw_vaddr_ptr) && (len) && (len >= cdm_cmd->cmd[i].offset)) {
+			if ((len - cdm_cmd->cmd[i].offset) < cdm_cmd->cmd[i].len) {
 				CAM_ERR(CAM_CDM,
 					"Not enough buffer cmd offset: %u cmd length: %u",
 					cdm_cmd->cmd[i].offset,
@@ -1119,134 +1029,99 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
 				break;
 			}
 
-			CAM_DBG(CAM_CDM, "Got the HW VA");
-			if (core->bl_fifo[fifo_idx].bl_tag >=
-				(bl_fifo->bl_depth - 1))
-				core->bl_fifo[fifo_idx].bl_tag = 0;
-			if (core->arbitration ==
-				CAM_CDM_ARBITRATION_PRIORITY_BASED &&
-				(req->data->flag == true) &&
-				(i == (req->data->cmd_arrary_count -
-				1))) {
-				CAM_DBG(CAM_CDM,
-					"GenIRQ in same bl, will sumbit later");
-			} else {
-				rc = cam_hw_cdm_bl_write(cdm_hw,
-					((uint32_t)hw_vaddr_ptr +
-						cdm_cmd->cmd[i].offset),
-					(cdm_cmd->cmd[i].len - 1),
-					core->bl_fifo[fifo_idx].bl_tag,
-					cdm_cmd->cmd[i].arbitrate,
-					fifo_idx);
-				if (rc) {
-					CAM_ERR(CAM_CDM,
-						"Hw bl write failed %d:%d",
-						i, req->data->cmd_arrary_count);
-					rc = -EIO;
-					break;
-				}
-			}
-		} else {
-			CAM_ERR(CAM_CDM,
-				"Sanity check failed for hdl=%x len=%zu:%d",
-				cdm_cmd->cmd[i].bl_addr.mem_handle, len,
-				cdm_cmd->cmd[i].offset);
-			CAM_ERR(CAM_CDM, "Sanity check failed for %d:%d",
-				i, req->data->cmd_arrary_count);
-			rc = -EINVAL;
-			break;
-		}
+			CAM_DBG(CAM_CDM, "Got the hwva: %pK, type: %u",
+				hw_vaddr_ptr, req->data->type);
 
-		if (!rc) {
-			CAM_DBG(CAM_CDM,
-				"write BL done cnt=%d with tag=%d total_cnt=%d",
-				i, core->bl_fifo[fifo_idx].bl_tag,
-				req->data->cmd_arrary_count);
+			rc = cam_hw_cdm_bl_write(cdm_hw,
+				((uint32_t)hw_vaddr_ptr + cdm_cmd->cmd[i].offset),
+				(cdm_cmd->cmd[i].len - 1),
+				core->bl_fifo[fifo_idx].bl_tag,
+				cdm_cmd->cmd[i].arbitrate,
+				fifo_idx);
+			if (rc) {
+				CAM_ERR(CAM_CDM, "Hw bl write failed %d:%d",
+					i, req->data->cmd_arrary_count);
+				rc = -EIO;
+				break;
+			}
 
-			if (core->arbitration ==
-				CAM_CDM_ARBITRATION_PRIORITY_BASED &&
-				(req->data->flag == true) &&
-				(i == (req->data->cmd_arrary_count -
-				1))) {
-				CAM_DBG(CAM_CDM,
-					"GenIRQ in same blcommit later");
-			} else {
-				CAM_DBG(CAM_CDM, "Now commit the BL");
-				if (cam_hw_cdm_commit_bl_write(cdm_hw,
-					fifo_idx)) {
-					CAM_ERR(CAM_CDM,
-						"commit failed BL %d tag=%d",
-						i, core->bl_fifo[fifo_idx]
-						.bl_tag);
-					rc = -EIO;
-					break;
-				}
-				write_count--;
-				CAM_DBG(CAM_CDM, "commit success BL %d tag=%d",
+			if (cam_hw_cdm_commit_bl_write(cdm_hw, fifo_idx)) {
+				CAM_ERR(CAM_CDM, "Commit failed for BL: %d Tag: %u",
 					i, core->bl_fifo[fifo_idx].bl_tag);
+				rc = -EIO;
+				break;
 			}
+
+			CAM_DBG(CAM_CDM, "Commit success for BL: %d of %d, Tag: %u", (i + 1),
+				req->data->cmd_arrary_count,
+				core->bl_fifo[fifo_idx].bl_tag);
+
+			write_count--;
 			core->bl_fifo[fifo_idx].bl_tag++;
+			core->bl_fifo[fifo_idx].bl_tag %= (bl_fifo->bl_depth - 1);
 
 			if (cdm_cmd->cmd[i].enable_debug_gen_irq) {
 				if (write_count == 0) {
 					write_count =
-						cam_hw_cdm_wait_for_bl_fifo(
-						cdm_hw, 1, fifo_idx);
+						cam_hw_cdm_wait_for_bl_fifo(cdm_hw, 1, fifo_idx);
 					if (write_count < 0) {
-						CAM_ERR(CAM_CDM,
-						"wait for bl fifo failed %d:%d",
-						i, req->data->cmd_arrary_count);
+						CAM_ERR(CAM_CDM, "wait for bl fifo failed %d:%d",
+							i, req->data->cmd_arrary_count);
 						rc = -EIO;
 						break;
 					}
 				}
 
-				rc = cam_hw_cdm_submit_debug_gen_irq(cdm_hw,
-					fifo_idx);
-				if (rc == 0) {
+				rc = cam_hw_cdm_submit_debug_gen_irq(cdm_hw, fifo_idx);
+				if (!rc) {
+					CAM_DBG(CAM_CDM,
+						"Commit success for Dbg_GenIRQ_BL, Tag: %d",
+						core->bl_fifo[fifo_idx].bl_tag);
 					write_count--;
 					core->bl_fifo[fifo_idx].bl_tag++;
+					core->bl_fifo[fifo_idx].bl_tag %= (bl_fifo->bl_depth - 1);
+				} else {
+					CAM_WARN(CAM_CDM,
+						"Failed in submitting the debug gen entry. rc: %d",
+						rc);
+					continue;
 				}
-				if (core->bl_fifo[fifo_idx].bl_tag >=
-						(bl_fifo->bl_depth -
-						1))
-					core->bl_fifo[fifo_idx].bl_tag = 0;
 			}
 
-			if ((!rc) && (req->data->flag == true) &&
-				(i == (req->data->cmd_arrary_count -
-				1))) {
+			if (req->data->flag && (i == (req->data->cmd_arrary_count - 1))) {
 
 				if (write_count == 0) {
 					write_count =
-						cam_hw_cdm_wait_for_bl_fifo(
-						cdm_hw, 1, fifo_idx);
+						cam_hw_cdm_wait_for_bl_fifo(cdm_hw, 1, fifo_idx);
 					if (write_count < 0) {
-						CAM_ERR(CAM_CDM,
-						"wait for bl fifo failed %d:%d",
-						i, req->data->cmd_arrary_count);
+						CAM_ERR(CAM_CDM, "wait for bl fifo failed %d:%d",
+							i, req->data->cmd_arrary_count);
 						rc = -EIO;
 						break;
 					}
 				}
 
-				if (core->arbitration !=
-					CAM_CDM_ARBITRATION_PRIORITY_BASED) {
+				if (core->arbitration == CAM_CDM_ARBITRATION_PRIORITY_BASED)
+					cdm_cmd->gen_irq_arb = true;
+				else
+					cdm_cmd->gen_irq_arb = false;
 
-					rc = cam_hw_cdm_submit_gen_irq(
-						cdm_hw, req, fifo_idx,
-						cdm_cmd->gen_irq_arb);
-					if (rc == 0)
-						core->bl_fifo[fifo_idx]
-						.bl_tag++;
-					break;
+				rc = cam_hw_cdm_submit_gen_irq(cdm_hw, req, fifo_idx,
+					cdm_cmd->gen_irq_arb);
+				if (!rc) {
+					CAM_DBG(CAM_CDM, "Commit success for GenIRQ_BL, Tag: %d",
+						core->bl_fifo[fifo_idx].bl_tag);
+					core->bl_fifo[fifo_idx].bl_tag++;
+					core->bl_fifo[fifo_idx].bl_tag %= (bl_fifo->bl_depth - 1);
 				}
-
-				rc = cam_hw_cdm_arb_submit_bl(cdm_hw, req, i,
-					fifo_idx, hw_vaddr_ptr);
-				if (rc)
-					break;
 			}
+		} else {
+			CAM_ERR(CAM_CDM,
+				"Sanity check failed for cdm_cmd: %d, Hdl: 0x%x, len: %zu, offset: 0x%x, num_cmds: %d",
+				i, cdm_cmd->cmd[i].bl_addr.mem_handle, len, cdm_cmd->cmd[i].offset,
+				req->data->cmd_arrary_count);
+			rc = -EINVAL;
+			break;
 		}
 	}
 	mutex_unlock(&client->lock);
@@ -1359,6 +1234,7 @@ static void cam_hw_cdm_work(struct work_struct *work)
 			return;
 		}
 
+		mutex_lock(&cdm_hw->hw_mutex);
 		mutex_lock(&core->bl_fifo[fifo_idx].fifo_lock);
 
 		if (atomic_read(&core->bl_fifo[fifo_idx].work_record))
@@ -1372,6 +1248,7 @@ static void cam_hw_cdm_work(struct work_struct *work)
 				core->arbitration);
 			mutex_unlock(&core->bl_fifo[fifo_idx]
 					.fifo_lock);
+			mutex_unlock(&cdm_hw->hw_mutex);
 			return;
 		}
 
@@ -1410,6 +1287,7 @@ static void cam_hw_cdm_work(struct work_struct *work)
 		}
 		mutex_unlock(&core->bl_fifo[payload->fifo_idx]
 			.fifo_lock);
+		mutex_unlock(&cdm_hw->hw_mutex);
 	}
 
 	if (payload->irq_status &
@@ -1434,11 +1312,7 @@ static void cam_hw_cdm_work(struct work_struct *work)
 		mutex_lock(&cdm_hw->hw_mutex);
 		for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++)
 			mutex_lock(&core->bl_fifo[i].fifo_lock);
-		/*
-		 * First pause CDM, If it fails still proceed
-		 * to dump debug info
-		 */
-		cam_hw_cdm_pause_core(cdm_hw, true);
+
 		cam_hw_cdm_dump_core_debug_registers(cdm_hw, true);
 
 		if (payload->irq_status &
@@ -1463,8 +1337,7 @@ static void cam_hw_cdm_work(struct work_struct *work)
 				kfree(node);
 			}
 		}
-		/* Resume CDM back */
-		cam_hw_cdm_pause_core(cdm_hw, false);
+
 		for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++)
 			mutex_unlock(&core->bl_fifo[i].fifo_lock);
 
@@ -1487,25 +1360,24 @@ static void cam_hw_cdm_iommu_fault_handler(struct cam_smmu_pf_info *pf_info)
 {
 	struct cam_hw_info *cdm_hw = NULL;
 	struct cam_cdm *core = NULL;
-	struct cam_cdm_pid_mid_data *pid_mid_info = NULL;
+	struct cam_cdm_private_dt_data *pvt_data;
 	int i;
 
+	if (!pf_info) {
+		CAM_ERR(CAM_CDM, "pf_info is null");
+		return;
+	}
+
 	if (pf_info->token) {
 		cdm_hw = (struct cam_hw_info *)pf_info->token;
 		core = (struct cam_cdm *)cdm_hw->core_info;
-		pid_mid_info = core->offsets->cmn_reg->cdm_pid_mid_info;
+		pvt_data = (struct cam_cdm_private_dt_data *) cdm_hw->soc_info.soc_private;
 		CAM_ERR_RATE_LIMIT(CAM_CDM, "Page fault iova addr %pK\n",
 			(void *)pf_info->iova);
 
-		if (pid_mid_info) {
-			/*
-			 * If its CDM or OPE CDM then only handle the pf for CDM
-			 * else return.
-			 */
-			if (((pf_info->pid == pid_mid_info->cdm_pid) &&
-				(pf_info->mid == pid_mid_info->cdm_mid)) ||
-				((pf_info->pid == pid_mid_info->ope_cdm_pid) &&
-				(pf_info->mid == pid_mid_info->ope_cdm_mid)))
+		/* Check if the PID and MID are valid, if not handle the pf */
+		if ((pvt_data->pid >= 0) && (pvt_data->mid >= 0)) {
+			if (((pf_info->pid == pvt_data->pid) && (pf_info->mid == pvt_data->mid)))
 				goto handle_cdm_pf;
 			else
 				return;
@@ -1524,9 +1396,9 @@ handle_cdm_pf:
 				cdm_hw->soc_info.index);
 		for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++)
 			mutex_unlock(&core->bl_fifo[i].fifo_lock);
-		mutex_unlock(&cdm_hw->hw_mutex);
 		cam_cdm_notify_clients(cdm_hw, CAM_CDM_CB_STATUS_PAGEFAULT,
 			(void *)pf_info->iova);
+		mutex_unlock(&cdm_hw->hw_mutex);
 		clear_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status);
 	} else {
 		CAM_ERR(CAM_CDM, "Invalid token");
@@ -1549,10 +1421,10 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data)
 	CAM_DBG(CAM_CDM, "Got irq hw_version 0x%x from %s%u",
 		cdm_core->hw_version, soc_info->label_name,
 		soc_info->index);
-	spin_lock(&cdm_hw->hw_lock);
+	cam_hw_util_hw_lock(cdm_hw);
 	if (cdm_hw->hw_state == CAM_HW_STATE_POWER_DOWN) {
 		CAM_DBG(CAM_CDM, "CDM is in power down state");
-		spin_unlock(&cdm_hw->hw_lock);
+		cam_hw_util_hw_unlock(cdm_hw);
 		return IRQ_HANDLED;
 	}
 	if (cdm_core->hw_version >= CAM_CDM_VERSION_2_1) {
@@ -1593,7 +1465,8 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data)
 		CAM_ERR(CAM_CDM, "Failed to read %s%u HW IRQ data",
 				soc_info->label_name,
 				soc_info->index);
-	spin_unlock(&cdm_hw->hw_lock);
+
+	cam_hw_util_hw_unlock(cdm_hw);
 
 	for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo_irq; i++) {
 		if (!irq_status[i])
@@ -1930,9 +1803,11 @@ int cam_hw_cdm_handle_error_info(
 
 	if (node != NULL) {
 		if (node->request_type == CAM_HW_CDM_BL_CB_CLIENT) {
+			mutex_lock(&cdm_hw->hw_mutex);
 			cam_cdm_notify_clients(cdm_hw,
 					CAM_CDM_CB_STATUS_HW_ERROR,
 					(void *)node);
+			mutex_unlock(&cdm_hw->hw_mutex);
 		} else if (node->request_type == CAM_HW_CDM_BL_CB_INTERNAL) {
 			CAM_ERR(CAM_CDM, "Invalid node=%pK %d", node,
 					node->request_type);
@@ -2109,7 +1984,7 @@ int cam_hw_cdm_init(void *hw_priv,
 	struct cam_hw_soc_info *soc_info = NULL;
 	struct cam_cdm *cdm_core = NULL;
 	int rc, i, reset_hw_hdl = 0x0;
-	unsigned long flags;
+	unsigned long flags = 0;
 
 	if (!hw_priv)
 		return -EINVAL;
@@ -2124,9 +1999,9 @@ int cam_hw_cdm_init(void *hw_priv,
 			soc_info->label_name, soc_info->index);
 		goto end;
 	}
-	spin_lock_irqsave(&cdm_hw->hw_lock, flags);
+	flags = cam_hw_util_hw_lock_irqsave(cdm_hw);
 	cdm_hw->hw_state = CAM_HW_STATE_POWER_UP;
-	spin_unlock_irqrestore(&cdm_hw->hw_lock, flags);
+	cam_hw_util_hw_unlock_irqrestore(cdm_hw, flags);
 
 	CAM_DBG(CAM_CDM, "Enable soc done for %s%d",
 		soc_info->label_name, soc_info->index);
@@ -2167,9 +2042,9 @@ int cam_hw_cdm_init(void *hw_priv,
 
 disable_return:
 	rc = -EIO;
-	spin_lock_irqsave(&cdm_hw->hw_lock, flags);
+	flags = cam_hw_util_hw_lock_irqsave(cdm_hw);
 	cdm_hw->hw_state = CAM_HW_STATE_POWER_DOWN;
-	spin_unlock_irqrestore(&cdm_hw->hw_lock, flags);
+	cam_hw_util_hw_unlock_irqrestore(cdm_hw, flags);
 	cam_soc_util_disable_platform_resource(soc_info, true, true);
 end:
 	return rc;
@@ -2185,7 +2060,7 @@ int cam_hw_cdm_deinit(void *hw_priv,
 	int rc = 0, i;
 	uint32_t reset_val = 1;
 	long time_left;
-	unsigned long                             flags;
+	unsigned long flags = 0;
 
 	if (!hw_priv)
 		return -EINVAL;
@@ -2247,9 +2122,9 @@ int cam_hw_cdm_deinit(void *hw_priv,
 	for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++)
 		mutex_unlock(&cdm_core->bl_fifo[i].fifo_lock);
 
-	spin_lock_irqsave(&cdm_hw->hw_lock, flags);
+	flags = cam_hw_util_hw_lock_irqsave(cdm_hw);
 	cdm_hw->hw_state = CAM_HW_STATE_POWER_DOWN;
-	spin_unlock_irqrestore(&cdm_hw->hw_lock, flags);
+	cam_hw_util_hw_unlock_irqrestore(cdm_hw, flags);
 	rc = cam_soc_util_disable_platform_resource(soc_info, true, true);
 	if (rc) {
 		CAM_ERR(CAM_CDM, "disable platform failed for %s%u",
@@ -2303,7 +2178,7 @@ static int cam_hw_cdm_component_bind(struct device *dev,
 	cdm_hw_intf->hw_type = CAM_HW_CDM;
 	cdm_hw->open_count = 0;
 	mutex_init(&cdm_hw->hw_mutex);
-	spin_lock_init(&cdm_hw->hw_lock);
+	cam_hw_util_init_hw_lock(cdm_hw);
 	init_completion(&cdm_hw->hw_complete);
 
 	rc = cam_hw_cdm_soc_get_dt_properties(cdm_hw, msm_cam_hw_cdm_dt_match);

drivers/cam_cdm/cam_cdm_hw_reg_2_1.h

@@ -1,17 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
  */
 
 #include "cam_cdm.h"
 
-struct cam_cdm_pid_mid_data cdm_hw_2_1_pid_mid_data = {
-	.cdm_pid = 2,
-	.cdm_mid = 0,
-	.ope_cdm_pid = 0,
-	.ope_cdm_mid = 2,
-};
-
 struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_1_bl_pending_req0 = {
 	.rb_offset = 0x6c,
 	.rb_mask = 0x1ff,
@@ -233,7 +226,6 @@ static struct cam_cdm_common_regs cdm_hw_2_1_cmn_reg_offset = {
 	.icl_reg = &cdm_2_1_icl,
 	.spare = 0x3fc,
 	.priority_group_bit_offset = 20,
-	.cdm_pid_mid_info = &cdm_hw_2_1_pid_mid_data,
 };
 
 static struct cam_cdm_common_reg_data cdm_hw_2_1_cmn_reg_data = {

drivers/cam_cdm/cam_cdm_intf_api.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_CDM_API_H_
@@ -133,23 +133,23 @@ struct cam_cdm_bl_cmd {
  *
  * @flag : 1 for callback needed and 0 for no callback when this BL
  *            request is done
+ * @gen_irq_arb : enum for setting arbitration in gen_irq
  * @userdata :Input private data which will be returned as part
  *             of callback if request for this bl request in flags.
- * @cookie : Cookie if the callback is gen irq status
  * @type : type of the submitted bl cmd address.
  * @cmd_arrary_count : Input number of BL commands to be submitted to CDM
- * @gen_irq_arb : enum for setting arbitration in gen_irq
+ * @cookie : Cookie if the callback is gen irq status
  * @bl_cmd_array     : Input payload holding the BL cmd's arrary
  *                     to be sumbitted.
  *
  */
 struct cam_cdm_bl_request {
-	int flag;
+	bool flag;
+	bool gen_irq_arb;
 	void *userdata;
-	uint64_t cookie;
 	enum cam_cdm_bl_cmd_addr_type type;
 	uint32_t cmd_arrary_count;
-	bool gen_irq_arb;
+	uint64_t cookie;
 	struct cam_cdm_bl_cmd cmd[1];
 };
 

drivers/cam_cdm/cam_cdm_soc.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/delay.h>
@@ -115,8 +115,15 @@ int cam_cdm_soc_load_dt_private(struct platform_device *pdev,
 	}
 
 	cdm_pvt_data->is_single_ctx_cdm =
-		of_property_read_bool(pdev->dev.of_node,
-			"single-context-cdm");
+		of_property_read_bool(pdev->dev.of_node, "single-context-cdm");
+
+	rc = of_property_read_u32(pdev->dev.of_node, "cam_hw_pid", &cdm_pvt_data->pid);
+	if (rc)
+		cdm_pvt_data->pid = -1;
+
+	rc = of_property_read_u32(pdev->dev.of_node, "cam-hw-mid", &cdm_pvt_data->mid);
+	if (rc)
+		cdm_pvt_data->mid = -1;
 
 	rc = of_property_read_u8(pdev->dev.of_node, "cdm-priority-group",
 			&cdm_pvt_data->priority_group);

drivers/cam_cdm/cam_cdm_util.c

@@ -186,78 +186,78 @@ struct cdm_prefetch_disable_event_cmd {
 	unsigned int mask2;
 } __attribute__((__packed__));
 
-uint32_t cdm_get_cmd_header_size(unsigned int command)
+uint32_t cam_cdm_get_cmd_header_size(unsigned int command)
 {
 	return CDMCmdHeaderSizes[command];
 }
 
-uint32_t cdm_required_size_dmi(void)
+uint32_t cam_cdm_required_size_dmi(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_DMI);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_DMI);
 }
 
-uint32_t cdm_required_size_reg_continuous(uint32_t numVals)
+uint32_t cam_cdm_required_size_reg_continuous(uint32_t numVals)
 {
 	if (!numVals) {
 		CAM_WARN(CAM_CDM, "numVals cant be 0");
 		return 0;
 	}
 
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT) + numVals;
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT) + numVals;
 }
 
-uint32_t cdm_required_size_reg_random(uint32_t numRegVals)
+uint32_t cam_cdm_required_size_reg_random(uint32_t numRegVals)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM) +
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM) +
 		(2 * numRegVals);
 }
 
-uint32_t cdm_required_size_indirect(void)
+uint32_t cam_cdm_required_size_indirect(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_BUFF_INDIRECT);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_BUFF_INDIRECT);
 }
 
-uint32_t cdm_required_size_genirq(void)
+uint32_t cam_cdm_required_size_genirq(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_GEN_IRQ);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_GEN_IRQ);
 }
 
-uint32_t cdm_required_size_wait_event(void)
+uint32_t cam_cdm_required_size_wait_event(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_WAIT_EVENT);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_WAIT_EVENT);
 }
 
-uint32_t cdm_required_size_changebase(void)
+uint32_t cam_cdm_required_size_changebase(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_CHANGE_BASE);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_CHANGE_BASE);
 }
 
-uint32_t cdm_required_size_comp_wait(void)
+uint32_t cam_cdm_required_size_comp_wait(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_COMP_WAIT);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_COMP_WAIT);
 }
 
-uint32_t cdm_required_size_clear_comp_event(void)
+uint32_t cam_cdm_required_size_clear_comp_event(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CLEAR_COMP_WAIT);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CLEAR_COMP_WAIT);
 }
 
-uint32_t cdm_required_size_prefetch_disable(void)
+uint32_t cam_cdm_required_size_prefetch_disable(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_WAIT_PREFETCH_DISABLE);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_WAIT_PREFETCH_DISABLE);
 }
 
-uint32_t cdm_offsetof_dmi_addr(void)
+uint32_t cam_cdm_offsetof_dmi_addr(void)
 {
 	return offsetof(struct cdm_dmi_cmd, addr);
 }
 
-uint32_t cdm_offsetof_indirect_addr(void)
+uint32_t cam_cdm_offsetof_indirect_addr(void)
 {
 	return offsetof(struct cdm_indirect_cmd, addr);
 }
 
-uint32_t *cdm_write_dmi(uint32_t *pCmdBuffer, uint8_t dmiCmd,
+uint32_t *cam_cdm_write_dmi(uint32_t *pCmdBuffer, uint8_t dmiCmd,
 	uint32_t DMIAddr, uint8_t DMISel, uint32_t dmiBufferAddr,
 	uint32_t length)
 {
@@ -269,12 +269,12 @@ uint32_t *cdm_write_dmi(uint32_t *pCmdBuffer, uint8_t dmiCmd,
 	pHeader->DMIAddr = DMIAddr;
 	pHeader->DMISel = DMISel;
 
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_DMI);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_DMI);
 
 	return pCmdBuffer;
 }
 
-uint32_t *cdm_write_regcontinuous(uint32_t *pCmdBuffer, uint32_t reg,
+uint32_t *cam_cdm_write_regcontinuous(uint32_t *pCmdBuffer, uint32_t reg,
 	uint32_t numVals, uint32_t *pVals)
 {
 	uint32_t i;
@@ -287,7 +287,7 @@ uint32_t *cdm_write_regcontinuous(uint32_t *pCmdBuffer, uint32_t reg,
 	pHeader->reserved1 = 0;
 	pHeader->offset = reg;
 
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
 
 	for (i = 0; i < numVals; i++)
 		(((uint32_t *)pCmdBuffer)[i]) = (((uint32_t *)pVals)[i]);
@@ -297,7 +297,7 @@ uint32_t *cdm_write_regcontinuous(uint32_t *pCmdBuffer, uint32_t reg,
 	return pCmdBuffer;
 }
 
-uint32_t *cdm_write_regrandom(uint32_t *pCmdBuffer, uint32_t numRegVals,
+uint32_t *cam_cdm_write_regrandom(uint32_t *pCmdBuffer, uint32_t numRegVals,
 	uint32_t *pRegVals)
 {
 	uint32_t i;
@@ -314,7 +314,7 @@ uint32_t *cdm_write_regrandom(uint32_t *pCmdBuffer, uint32_t numRegVals,
 	pHeader->cmd = CAM_CDM_CMD_REG_RANDOM;
 	pHeader->reserved = 0;
 
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
 	dst = pCmdBuffer;
 	src = pRegVals;
 	for (i = 0; i < numRegVals; i++) {
@@ -325,7 +325,7 @@ uint32_t *cdm_write_regrandom(uint32_t *pCmdBuffer, uint32_t numRegVals,
 	return dst;
 }
 
-uint32_t *cdm_write_indirect(uint32_t *pCmdBuffer, uint32_t indirectBufAddr,
+uint32_t *cam_cdm_write_indirect(uint32_t *pCmdBuffer, uint32_t indirectBufAddr,
 	uint32_t length)
 {
 	struct cdm_indirect_cmd *pHeader =
@@ -335,12 +335,12 @@ uint32_t *cdm_write_indirect(uint32_t *pCmdBuffer, uint32_t indirectBufAddr,
 	pHeader->addr = indirectBufAddr;
 	pHeader->length = length - 1;
 
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_BUFF_INDIRECT);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_BUFF_INDIRECT);
 
 	return pCmdBuffer;
 }
 
-void cdm_write_genirq(uint32_t *pCmdBuffer, uint32_t userdata,
+void cam_cdm_write_genirq(uint32_t *pCmdBuffer, uint32_t userdata,
 		bool bit_wr_enable, uint32_t fifo_idx)
 {
 	struct cdm_genirq_cmd *pHeader = (struct cdm_genirq_cmd *)pCmdBuffer;
@@ -356,7 +356,7 @@ void cdm_write_genirq(uint32_t *pCmdBuffer, uint32_t userdata,
 	pHeader->userdata = (userdata << (8 * fifo_idx));
 }
 
-uint32_t *cdm_write_wait_event(uint32_t *pcmdbuffer, uint32_t iw,
+uint32_t *cam_cdm_write_wait_event(uint32_t *pcmdbuffer, uint32_t iw,
 	uint32_t id, uint32_t mask,
 	uint32_t offset, uint32_t data)
 {
@@ -372,12 +372,12 @@ uint32_t *cdm_write_wait_event(uint32_t *pcmdbuffer, uint32_t iw,
 	pheader->iw_reserved = 0;
 	pheader->offset_reserved = 0;
 
-	pcmdbuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_WAIT_EVENT);
+	pcmdbuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_WAIT_EVENT);
 
 	return pcmdbuffer;
 }
 
-uint32_t *cdm_write_changebase(uint32_t *pCmdBuffer, uint32_t base)
+uint32_t *cam_cdm_write_changebase(uint32_t *pCmdBuffer, uint32_t base)
 {
 	struct cdm_changebase_cmd *pHeader =
 		(struct cdm_changebase_cmd *)pCmdBuffer;
@@ -386,12 +386,12 @@ uint32_t *cdm_write_changebase(uint32_t *pCmdBuffer, uint32_t base)
 
 	pHeader->cmd = CAM_CDM_CMD_CHANGE_BASE;
 	pHeader->base = base;
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_CHANGE_BASE);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_CHANGE_BASE);
 
 	return pCmdBuffer;
 }
 
-uint32_t *cdm_write_wait_comp_event(
+uint32_t *cam_cdm_write_wait_comp_event(
 	uint32_t *pCmdBuffer, uint32_t mask1, uint32_t mask2)
 {
 	struct cdm_wait_comp_event_cmd *pHeader =
@@ -401,12 +401,12 @@ uint32_t *cdm_write_wait_comp_event(
 	pHeader->mask1 = mask1;
 	pHeader->mask2 = mask2;
 
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_COMP_WAIT);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_COMP_WAIT);
 
 	return pCmdBuffer;
 }
 
-uint32_t *cdm_write_clear_comp_event(
+uint32_t *cam_cdm_write_clear_comp_event(
 	uint32_t *pCmdBuffer, uint32_t mask1, uint32_t mask2)
 {
 	struct cdm_clear_comp_event_cmd *pHeader =
@@ -416,12 +416,12 @@ uint32_t *cdm_write_clear_comp_event(
 	pHeader->mask1 = mask1;
 	pHeader->mask2 = mask2;
 
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CLEAR_COMP_WAIT);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CLEAR_COMP_WAIT);
 
 	return pCmdBuffer;
 }
 
-uint32_t *cdm_write_wait_prefetch_disable(
+uint32_t *cam_cdm_write_wait_prefetch_disable(
 	uint32_t                   *pCmdBuffer,
 	uint32_t                    id,
 	uint32_t                    mask1,
@@ -435,36 +435,36 @@ uint32_t *cdm_write_wait_prefetch_disable(
 	pHeader->mask1 = mask1;
 	pHeader->mask2 = mask2;
 
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_WAIT_PREFETCH_DISABLE);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_WAIT_PREFETCH_DISABLE);
 
 	return pCmdBuffer;
 }
 
 
 struct cam_cdm_utils_ops CDM170_ops = {
-	cdm_get_cmd_header_size,
-	cdm_required_size_dmi,
-	cdm_required_size_reg_continuous,
-	cdm_required_size_reg_random,
-	cdm_required_size_indirect,
-	cdm_required_size_genirq,
-	cdm_required_size_wait_event,
-	cdm_required_size_changebase,
-	cdm_required_size_comp_wait,
-	cdm_required_size_clear_comp_event,
-	cdm_required_size_prefetch_disable,
-	cdm_offsetof_dmi_addr,
-	cdm_offsetof_indirect_addr,
-	cdm_write_dmi,
-	cdm_write_regcontinuous,
-	cdm_write_regrandom,
-	cdm_write_indirect,
-	cdm_write_genirq,
-	cdm_write_wait_event,
-	cdm_write_changebase,
-	cdm_write_wait_comp_event,
-	cdm_write_clear_comp_event,
-	cdm_write_wait_prefetch_disable,
+	.cdm_get_cmd_header_size              = cam_cdm_get_cmd_header_size,
+	.cdm_required_size_dmi                = cam_cdm_required_size_dmi,
+	.cdm_required_size_reg_continuous     = cam_cdm_required_size_reg_continuous,
+	.cdm_required_size_reg_random         = cam_cdm_required_size_reg_random,
+	.cdm_required_size_indirect           = cam_cdm_required_size_indirect,
+	.cdm_required_size_genirq             = cam_cdm_required_size_genirq,
+	.cdm_required_size_wait_event         = cam_cdm_required_size_wait_event,
+	.cdm_required_size_changebase         = cam_cdm_required_size_changebase,
+	.cdm_required_size_comp_wait          = cam_cdm_required_size_comp_wait,
+	.cdm_required_size_clear_comp_event   = cam_cdm_required_size_clear_comp_event,
+	.cdm_required_size_prefetch_disable   = cam_cdm_required_size_prefetch_disable,
+	.cdm_offsetof_dmi_addr                = cam_cdm_offsetof_dmi_addr,
+	.cdm_offsetof_indirect_addr           = cam_cdm_offsetof_indirect_addr,
+	.cdm_write_dmi                        = cam_cdm_write_dmi,
+	.cdm_write_regcontinuous              = cam_cdm_write_regcontinuous,
+	.cdm_write_regrandom                  = cam_cdm_write_regrandom,
+	.cdm_write_indirect                   = cam_cdm_write_indirect,
+	.cdm_write_genirq                     = cam_cdm_write_genirq,
+	.cdm_write_wait_event                 = cam_cdm_write_wait_event,
+	.cdm_write_changebase                 = cam_cdm_write_changebase,
+	.cdm_write_wait_comp_event            = cam_cdm_write_wait_comp_event,
+	.cdm_write_clear_comp_event           = cam_cdm_write_clear_comp_event,
+	.cdm_write_wait_prefetch_disable      = cam_cdm_write_wait_prefetch_disable,
 };
 
 int cam_cdm_get_ioremap_from_base(uint32_t hw_base,
@@ -496,7 +496,7 @@ static int cam_cdm_util_reg_cont_write(void __iomem *base_addr,
 	uint32_t *data;
 	struct cdm_regcontinuous_cmd *reg_cont;
 
-	if ((cmd_buf_size < cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT)) ||
+	if ((cmd_buf_size < cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT)) ||
 		(!base_addr)) {
 		CAM_ERR(CAM_CDM, "invalid base addr and data length  %d %pK",
 			cmd_buf_size, base_addr);
@@ -506,18 +506,18 @@ static int cam_cdm_util_reg_cont_write(void __iomem *base_addr,
 	reg_cont = (struct cdm_regcontinuous_cmd *)cmd_buf;
 	if ((!reg_cont->count) || (reg_cont->count > 0x10000) ||
 		(((reg_cont->count * sizeof(uint32_t)) +
-			cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT)) >
+			cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT)) >
 			cmd_buf_size)) {
 		CAM_ERR(CAM_CDM, "buffer size %d is not sufficient for count%d",
 			cmd_buf_size, reg_cont->count);
 		return -EINVAL;
 	}
-	data = cmd_buf + cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
+	data = cmd_buf + cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
 	cam_io_memcpy(base_addr + reg_cont->offset,	data,
 		reg_cont->count * sizeof(uint32_t));
 
 	*used_bytes = (reg_cont->count * sizeof(uint32_t)) +
-		(4 * cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT));
+		(4 * cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT));
 
 	return ret;
 }
@@ -537,13 +537,13 @@ static int cam_cdm_util_reg_random_write(void __iomem *base_addr,
 	reg_random = (struct cdm_regrandom_cmd *) cmd_buf;
 	if ((!reg_random->count) || (reg_random->count > 0x10000) ||
 		(((reg_random->count * (sizeof(uint32_t) * 2)) +
-		cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM)) >
+		cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM)) >
 			cmd_buf_size)) {
 		CAM_ERR(CAM_CDM, "invalid reg_count  %d cmd_buf_size %d",
 			reg_random->count, cmd_buf_size);
 		return -EINVAL;
 	}
-	data = cmd_buf + cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
+	data = cmd_buf + cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
 
 	for (i = 0; i < reg_random->count; i++) {
 		CAM_DBG(CAM_CDM, "reg random: offset %pK, value 0x%x",
@@ -554,7 +554,7 @@ static int cam_cdm_util_reg_random_write(void __iomem *base_addr,
 	}
 
 	*used_bytes = ((reg_random->count * (sizeof(uint32_t) * 2)) +
-		(4 * cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM)));
+		(4 * cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM)));
 
 	return 0;
 }
@@ -569,12 +569,12 @@ static int cam_cdm_util_swd_dmi_write(uint32_t cdm_cmd_type,
 
 	swd_dmi = (struct cdm_dmi_cmd *)cmd_buf;
 
-	if (cmd_buf_size < (cdm_required_size_dmi() + swd_dmi->length + 1)) {
+	if (cmd_buf_size < (cam_cdm_required_size_dmi() + swd_dmi->length + 1)) {
 		CAM_ERR(CAM_CDM, "invalid CDM_SWD_DMI length %d",
 			swd_dmi->length + 1);
 		return -EINVAL;
 	}
-	data = cmd_buf + cdm_required_size_dmi();
+	data = cmd_buf + cam_cdm_required_size_dmi();
 
 	if (cdm_cmd_type == CAM_CDM_CMD_SWD_DMI_64) {
 		for (i = 0; i < (swd_dmi->length + 1)/8; i++) {
@@ -597,7 +597,7 @@ static int cam_cdm_util_swd_dmi_write(uint32_t cdm_cmd_type,
 			data += 1;
 		}
 	}
-	*used_bytes = (4 * cdm_required_size_dmi()) + swd_dmi->length + 1;
+	*used_bytes = (4 * cam_cdm_required_size_dmi()) + swd_dmi->length + 1;
 
 	return 0;
 }
@@ -681,8 +681,8 @@ int cam_cdm_util_cmd_buf_write(void __iomem **current_device_base,
 				change_base_cmd->base,
 				current_device_base);
 			cmd_buf_size -= (4 *
-				cdm_required_size_changebase());
-			cmd_buf += cdm_required_size_changebase();
+				cam_cdm_required_size_changebase());
+			cmd_buf += cam_cdm_required_size_changebase();
 			}
 			break;
 		default:
@@ -949,8 +949,8 @@ static uint32_t cam_cdm_util_dump_reg_cont_cmd_v2(
 	struct cam_cdm_cmd_dump_header *hdr;
 
 	p_regcont_cmd = (struct cdm_regcontinuous_cmd *)temp_ptr;
-	temp_ptr += cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
-	ret = cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
+	temp_ptr += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
+	ret = cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
 
 	min_len = (sizeof(uint32_t) * p_regcont_cmd->count) +
 		sizeof(struct cam_cdm_cmd_dump_header) +
@@ -1000,8 +1000,8 @@ static uint32_t cam_cdm_util_dump_reg_random_cmd_v2(
 	struct cam_cdm_cmd_dump_header *hdr;
 
 	p_regrand_cmd = (struct cdm_regrandom_cmd *)temp_ptr;
-	temp_ptr += cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
-	ret = cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
+	temp_ptr += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
+	ret = cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
 
 	min_len = (2 * sizeof(uint32_t) * p_regrand_cmd->count) +
 		sizeof(struct cam_cdm_cmd_dump_header) + sizeof(uint32_t);
@@ -1063,7 +1063,7 @@ int cam_cdm_util_dump_cmd_bufs_v2(
 		case CAM_CDM_CMD_DMI:
 		case CAM_CDM_CMD_DMI_32:
 		case CAM_CDM_CMD_DMI_64:
-			buf_now += cdm_get_cmd_header_size(CAM_CDM_CMD_DMI);
+			buf_now += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_DMI);
 			break;
 		case CAM_CDM_CMD_REG_CONT:
 			buf_now += cam_cdm_util_dump_reg_cont_cmd_v2(buf_now,
@@ -1074,27 +1074,27 @@ int cam_cdm_util_dump_cmd_bufs_v2(
 				dump_info);
 			break;
 		case CAM_CDM_CMD_BUFF_INDIRECT:
-			buf_now += cdm_get_cmd_header_size(
+			buf_now += cam_cdm_get_cmd_header_size(
 				CAM_CDM_CMD_BUFF_INDIRECT);
 			break;
 		case CAM_CDM_CMD_GEN_IRQ:
-			buf_now += cdm_get_cmd_header_size(
+			buf_now += cam_cdm_get_cmd_header_size(
 				CAM_CDM_CMD_GEN_IRQ);
 			break;
 		case CAM_CDM_CMD_WAIT_EVENT:
-			buf_now += cdm_get_cmd_header_size(
+			buf_now += cam_cdm_get_cmd_header_size(
 				CAM_CDM_CMD_WAIT_EVENT);
 			break;
 		case CAM_CDM_CMD_CHANGE_BASE:
-			buf_now += cdm_get_cmd_header_size(
+			buf_now += cam_cdm_get_cmd_header_size(
 				CAM_CDM_CMD_CHANGE_BASE);
 			break;
 		case CAM_CDM_CMD_PERF_CTRL:
-			buf_now += cdm_get_cmd_header_size(
+			buf_now += cam_cdm_get_cmd_header_size(
 				CAM_CDM_CMD_PERF_CTRL);
 			break;
 		case CAM_CDM_CMD_COMP_WAIT:
-			buf_now += cdm_get_cmd_header_size(
+			buf_now += cam_cdm_get_cmd_header_size(
 				CAM_CDM_CMD_COMP_WAIT);
 			break;
 		default:

drivers/cam_cdm/cam_cdm_virtual_core.c

@@ -160,8 +160,7 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw,
 			CAM_DBG(CAM_CDM,
 				"write BL success for cnt=%d with tag=%d",
 				i, core->bl_tag);
-			if ((true == req->data->flag) &&
-				(i == req->data->cmd_arrary_count)) {
+			if (req->data->flag && (i == req->data->cmd_arrary_count)) {
 				struct cam_cdm_bl_cb_request_entry *node;
 
 				node = kzalloc(sizeof(

drivers/cam_core/cam_context.h

@@ -257,9 +257,9 @@ struct cam_context {
 	uint32_t                       max_hw_update_entries;
 	uint32_t                       max_in_map_entries;
 	uint32_t                       max_out_map_entries;
-	struct cam_hw_update_entry    *hw_update_entry;
-	struct cam_hw_fence_map_entry *in_map_entries;
-	struct cam_hw_fence_map_entry *out_map_entries;
+	struct cam_hw_update_entry    **hw_update_entry;
+	struct cam_hw_fence_map_entry **in_map_entries;
+	struct cam_hw_fence_map_entry **out_map_entries;
 	cam_ctx_mini_dump_cb_func      mini_dump_cb;
 	int                            img_iommu_hdl;
 };

drivers/cam_core/cam_context_utils.c

@@ -35,20 +35,45 @@ static inline int cam_context_validate_thread(void)
 
 static void cam_context_free_mem_hw_entries(struct cam_context *ctx)
 {
-	kfree(ctx->out_map_entries);
-	kfree(ctx->in_map_entries);
-	kfree(ctx->hw_update_entry);
-	ctx->out_map_entries = NULL;
-	ctx->in_map_entries = NULL;
-	ctx->hw_update_entry = NULL;
+	int  i;
+
+	if (ctx->out_map_entries) {
+		for (i = 0; i < ctx->req_size; i++) {
+			kfree(ctx->out_map_entries[i]);
+			ctx->out_map_entries[i] = NULL;
+		}
+
+		kfree(ctx->out_map_entries);
+		ctx->out_map_entries = NULL;
+	}
+
+	if (ctx->in_map_entries) {
+		for (i = 0; i < ctx->req_size; i++) {
+			kfree(ctx->in_map_entries[i]);
+			ctx->in_map_entries[i] = NULL;
+		}
+
+		kfree(ctx->in_map_entries);
+		ctx->in_map_entries = NULL;
+	}
+
+	if (ctx->hw_update_entry) {
+		for (i = 0; i < ctx->req_size; i++) {
+			kfree(ctx->hw_update_entry[i]);
+			ctx->hw_update_entry[i] = NULL;
+		}
+
+		kfree(ctx->hw_update_entry);
+		ctx->hw_update_entry = NULL;
+	}
 }
 
 static int cam_context_allocate_mem_hw_entries(struct cam_context *ctx)
 {
 	int rc = 0;
+	unsigned int i;
 	struct cam_ctx_request          *req;
 	struct cam_ctx_request          *temp_req;
-	size_t num_entries = 0;
 
 	CAM_DBG(CAM_CTXT,
 		"%s[%d] num: max_hw %u in_map %u out_map %u req %u",
@@ -59,47 +84,75 @@ static int cam_context_allocate_mem_hw_entries(struct cam_context *ctx)
 		ctx->max_out_map_entries,
 		ctx->req_size);
 
-	num_entries = ctx->max_hw_update_entries * ctx->req_size;
-	ctx->hw_update_entry = kcalloc(num_entries,
-		sizeof(struct cam_hw_update_entry),
-		GFP_KERNEL);
+	ctx->hw_update_entry = kcalloc(ctx->req_size,
+		sizeof(struct cam_hw_update_entry *), GFP_KERNEL);
 
 	if (!ctx->hw_update_entry) {
-		CAM_ERR(CAM_CTXT, "%s[%d] no memory", ctx->dev_name, ctx->ctx_id);
-		rc = -ENOMEM;
+		CAM_ERR(CAM_CTXT, "%s[%d] no memory for hw_update_entry",
+			ctx->dev_name, ctx->ctx_id);
 		return -ENOMEM;
 	}
 
-	num_entries = ctx->max_in_map_entries * ctx->req_size;
-	ctx->in_map_entries = kcalloc(num_entries,
-		sizeof(struct cam_hw_fence_map_entry),
+	for (i = 0; i < ctx->req_size; i++) {
+		ctx->hw_update_entry[i] = kcalloc(ctx->max_hw_update_entries,
+			sizeof(struct cam_hw_update_entry), GFP_KERNEL);
+
+		if (!ctx->hw_update_entry[i]) {
+			CAM_ERR(CAM_CTXT, "%s[%d] no memory for hw_update_entry: %u",
+				ctx->dev_name, ctx->ctx_id, i);
+			rc = -ENOMEM;
+			goto free_mem;
+		}
+	}
+
+	ctx->in_map_entries = kcalloc(ctx->req_size, sizeof(struct cam_hw_fence_map_entry *),
 		GFP_KERNEL);
 
 	if (!ctx->in_map_entries) {
-		CAM_ERR(CAM_CTXT, "%s[%d] no memory", ctx->dev_name, ctx->ctx_id);
+		CAM_ERR(CAM_CTXT, "%s[%d] no memory for in_map_entries",
+			ctx->dev_name, ctx->ctx_id);
 		rc = -ENOMEM;
 		goto free_mem;
 	}
 
-	num_entries = ctx->max_out_map_entries * ctx->req_size;
+	for (i = 0; i < ctx->req_size; i++) {
+		ctx->in_map_entries[i] = kcalloc(ctx->max_in_map_entries,
+			sizeof(struct cam_hw_fence_map_entry), GFP_KERNEL);
 
-	ctx->out_map_entries = kcalloc(num_entries,
-		sizeof(struct cam_hw_fence_map_entry),
+		if (!ctx->in_map_entries[i]) {
+			CAM_ERR(CAM_CTXT, "%s[%d] no memory for in_map_entries: %u",
+				ctx->dev_name, ctx->ctx_id, i);
+			rc = -ENOMEM;
+			goto free_mem;
+		}
+	}
+
+	ctx->out_map_entries = kcalloc(ctx->req_size, sizeof(struct cam_hw_fence_map_entry *),
 		GFP_KERNEL);
+
 	if (!ctx->out_map_entries) {
-		CAM_ERR(CAM_CTXT, "%s[%d] no memory", ctx->dev_name, ctx->ctx_id);
+		CAM_ERR(CAM_CTXT, "%s[%d] no memory for out_map_entries",
+			ctx->dev_name, ctx->ctx_id);
+		rc = -ENOMEM;
 		goto free_mem;
 	}
 
-	list_for_each_entry_safe(req, temp_req,
-		&ctx->free_req_list, list) {
+	for (i = 0; i < ctx->req_size; i++) {
+		ctx->out_map_entries[i] = kcalloc(ctx->max_out_map_entries,
+			sizeof(struct cam_hw_fence_map_entry), GFP_KERNEL);
+
+		if (!ctx->out_map_entries[i]) {
+			CAM_ERR(CAM_CTXT, "%s[%d] no memory for out_map_entries: %u",
+				ctx->dev_name, ctx->ctx_id, i);
+			rc = -ENOMEM;
+			goto free_mem;
+		}
+	}
 
-		req->hw_update_entries =
-			&ctx->hw_update_entry[req->index * ctx->max_hw_update_entries];
-		req->in_map_entries =
-			&ctx->in_map_entries[req->index * ctx->max_in_map_entries];
-		req->out_map_entries =
-			&ctx->out_map_entries[req->index * ctx->max_out_map_entries];
+	list_for_each_entry_safe(req, temp_req, &ctx->free_req_list, list) {
+		req->hw_update_entries = ctx->hw_update_entry[req->index];
+		req->in_map_entries = ctx->in_map_entries[req->index];
+		req->out_map_entries = ctx->out_map_entries[req->index];
 	}
 
 	return rc;
@@ -530,6 +583,9 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx,
 			rc = cam_sync_check_valid(
 				req->in_map_entries[j].sync_id);
 			if (rc) {
+				spin_lock(&ctx->lock);
+				list_del_init(&req->list);
+				spin_unlock(&ctx->lock);
 				CAM_ERR(CAM_CTXT,
 					"invalid in map sync object %d",
 					req->in_map_entries[j].sync_id);

drivers/cam_core/cam_hw.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2018, 2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_HW_H_
@@ -30,6 +30,8 @@ enum cam_hw_state {
  * @soc_info:              Platform SOC properties for hardware
  * @node_info:             Private HW data related to nodes
  * @core_info:             Private HW data related to core logic
+ * @presil_hw_lock:        Mutex lock used for presil in place of hw_lock,
+ *                         for drivers like CDM
  *
  */
 struct cam_hw_info {
@@ -41,6 +43,10 @@ struct cam_hw_info {
 	struct cam_hw_soc_info          soc_info;
 	void                           *node_info;
 	void                           *core_info;
+
+#ifdef CONFIG_CAM_PRESIL
+	struct mutex                    presil_hw_lock;
+#endif
 };
 
 #endif /* _CAM_HW_H_ */

drivers/cam_core/cam_hw_intf.h

@@ -7,6 +7,7 @@
 #define _CAM_HW_INTF_H_
 
 #include <linux/types.h>
+#include "cam_hw.h"
 
 /*
  * This file declares Constants, Enums, Structures and APIs to be used as
@@ -86,4 +87,66 @@ struct cam_hw_intf {
 typedef int (*cam_hw_mgr_event_cb_func)(void *priv, uint32_t evt_id,
 	void *evt_data);
 
+#ifdef CONFIG_CAM_PRESIL
+static inline void cam_hw_util_init_hw_lock(struct cam_hw_info *hw_info)
+{
+	mutex_init(&hw_info->presil_hw_lock);
+}
+
+static inline unsigned long cam_hw_util_hw_lock_irqsave(struct cam_hw_info *hw_info)
+{
+	mutex_lock(&hw_info->presil_hw_lock);
+
+	return 0;
+}
+
+static inline void cam_hw_util_hw_unlock_irqrestore(struct cam_hw_info *hw_info,
+	unsigned long flags)
+{
+	mutex_unlock(&hw_info->presil_hw_lock);
+}
+
+static inline void cam_hw_util_hw_lock(struct cam_hw_info *hw_info)
+{
+	mutex_lock(&hw_info->presil_hw_lock);
+}
+
+static inline void cam_hw_util_hw_unlock(struct cam_hw_info *hw_info)
+{
+	mutex_unlock(&hw_info->presil_hw_lock);
+}
+#else
+static inline void cam_hw_util_init_hw_lock(struct cam_hw_info *hw_info)
+{
+	spin_lock_init(&hw_info->hw_lock);
+}
+
+static inline unsigned long cam_hw_util_hw_lock_irqsave(struct cam_hw_info *hw_info)
+{
+	unsigned long flags = 0;
+
+	if (!in_irq())
+		spin_lock_irqsave(&hw_info->hw_lock, flags);
+
+	return flags;
+}
+
+static inline void cam_hw_util_hw_unlock_irqrestore(struct cam_hw_info *hw_info,
+	unsigned long flags)
+{
+	if (!in_irq())
+		spin_unlock_irqrestore(&hw_info->hw_lock, flags);
+}
+
+static inline void cam_hw_util_hw_lock(struct cam_hw_info *hw_info)
+{
+	spin_lock(&hw_info->hw_lock);
+}
+
+static inline void cam_hw_util_hw_unlock(struct cam_hw_info *hw_info)
+{
+	spin_unlock(&hw_info->hw_lock);
+}
+#endif /* CONFIG_CAM_PRESIL */
+
 #endif /* _CAM_HW_INTF_H_ */

drivers/cam_core/cam_hw_mgr_intf.h

@@ -272,6 +272,15 @@ struct cam_hw_stream_setttings {
 	void                           *priv;
 };
 
+/**
+ * enum cam_hw_config_reapply_type
+ */
+enum cam_hw_config_reapply_type {
+	CAM_CONFIG_REAPPLY_NONE,
+	CAM_CONFIG_REAPPLY_IQ,
+	CAM_CONFIG_REAPPLY_IO,
+};
+
 /**
  * struct cam_hw_config_args - Payload for config command
  *
@@ -282,7 +291,8 @@ struct cam_hw_stream_setttings {
  * @num_out_map_entries:       Number of out map entries
  * @priv:                      Private pointer
  * @request_id:                Request ID
- * @reapply:                   True if reapplying after bubble
+ * @reapply_type:              On reapply determines what is to be applied
+ * @init_packet:               Set if INIT packet
  * @cdm_reset_before_apply:    True is need to reset CDM before re-apply bubble
  *                             request
  *
@@ -295,8 +305,8 @@ struct cam_hw_config_args {
 	uint32_t                        num_out_map_entries;
 	void                           *priv;
 	uint64_t                        request_id;
+	enum cam_hw_config_reapply_type reapply_type;
 	bool                            init_packet;
-	bool                            reapply;
 	bool                            cdm_reset_before_apply;
 };
 

drivers/cam_cpas/cam_cpas_hw.c

@@ -933,10 +933,9 @@ static int cam_cpas_axi_consolidate_path_votes(
 
 		if (!path_found) {
 			CAM_ERR(CAM_CPAS,
-				"Client [%s][%d] Consolidated path not found for path=%d, transac=%d",
-				cpas_client->data.identifier,
-				cpas_client->data.cell_index,
-				path_data_type, transac_type);
+				"Client [%s][%d] i=%d num_paths=%d Consolidated path not found for path=%d, transac=%d",
+				cpas_client->data.identifier, cpas_client->data.cell_index, i,
+				axi_vote->num_paths, path_data_type, transac_type);
 			return -EINVAL;
 		}
 	}

drivers/cam_cpas/cpas_top/cam_cpastop_hw.c

@@ -28,6 +28,7 @@
 #include "cpastop_v540_100.h"
 #include "cpastop_v520_100.h"
 #include "cpastop_v545_100.h"
+#include "cpastop_v570_100.h"
 #include "cpastop_v570_200.h"
 #include "cpastop_v680_100.h"
 #include "cpastop_v165_100.h"
@@ -128,7 +129,7 @@ static const uint32_t cam_cpas_hw_version_map
 	},
 	/* for camera_570 */
 	{
-		0,
+		CAM_CPAS_TITAN_570_V100,
 		0,
 		0,
 		0,
@@ -942,6 +943,10 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw,
 		camnoc_info = &cam545_cpas100_camnoc_info;
 		qchannel_info = &cam545_cpas100_qchannel_info;
 		break;
+	case CAM_CPAS_TITAN_570_V100:
+		camnoc_info = &cam570_cpas100_camnoc_info;
+		qchannel_info = &cam570_cpas100_qchannel_info;
+		break;
 	case CAM_CPAS_TITAN_570_V200:
 		camnoc_info = &cam570_cpas200_camnoc_info;
 		qchannel_info = &cam570_cpas200_qchannel_info;

drivers/cam_cpas/cpas_top/cpastop_v570_100.h

@@ -0,0 +1,928 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _CPASTOP_V570_100_H_
+#define _CPASTOP_V570_100_H_
+
+#define TEST_IRQ_ENABLE 0
+
+static struct cam_camnoc_irq_sbm cam_cpas_v570_100_irq_sbm = {
+	.sbm_enable = {
+		.access_type = CAM_REG_TYPE_READ_WRITE,
+		.enable = true,
+		.offset = 0x3840, /* SBM_FAULTINEN0_LOW */
+		.value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
+			0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
+			0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
+			0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
+			0x1000 | /* SBM_FAULTINEN0_LOW_PORT12_MASK */
+			(TEST_IRQ_ENABLE ?
+			0x40 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */
+			0x0),
+	},
+	.sbm_status = {
+		.access_type = CAM_REG_TYPE_READ,
+		.enable = true,
+		.offset = 0x3848, /* SBM_FAULTINSTATUS0_LOW */
+	},
+	.sbm_clear = {
+		.access_type = CAM_REG_TYPE_WRITE,
+		.enable = true,
+		.offset = 0x3880, /* SBM_FLAGOUTCLR0_LOW */
+		.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
+	}
+};
+
+static struct cam_camnoc_irq_err
+	cam_cpas_v570_100_irq_err[] = {
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
+		.enable = false,
+		.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x7008, /* ERL_MAINCTL_LOW */
+			.value = 1,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x7010, /* ERL_ERRVLD_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x7018, /* ERL_ERRCLR_LOW */
+			.value = 1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x1BA0, /* IFE_UBWC_STATS_0_ENCERREN_LOW */
+			.value = 1,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x1B90,
+			/* IFE_UBWC_STATS_0_ENCERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x1B98, /* IFE_UBWC_STATS_0_ENCERRCLR_LOW */
+			.value = 1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_IPE1_BPS_UBWC_DECODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x2520, /* IPE1_BPS_RD_DECERREN_LOW */
+			.value = 1,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x2510, /* IPE1_BPS_RD_DECERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x2518, /* IPE1_BPS_RD_DECERRCLR_LOW */
+			.value = 1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x1F20, /* IPE0_RD_DECERREN_LOW */
+			.value = 1,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x1F10, /* IPE0_RD_DECERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x1F18, /* IPE0_RD_DECERRCLR_LOW */
+			.value = 1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x29A0, /* IPE_BPS_WR_ENCERREN_LOW */
+			.value = 1,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x2990,
+			/* IPE_BPS_WR_ENCERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x2998, /* IPE_BPS_WR_ENCERRCLR_LOW */
+			.value = 1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
+		.enable = false,
+		.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x3888, /* SBM_FLAGOUTSET0_LOW */
+			.value = 0x1,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x3890, /* SBM_FLAGOUTSTATUS0_LOW */
+		},
+		.err_clear = {
+			.enable = false,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
+		.enable = false,
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
+		.enable = false,
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
+		.enable = TEST_IRQ_ENABLE ? true : false,
+		.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x3888, /* SBM_FLAGOUTSET0_LOW */
+			.value = 0x5,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x3890, /* SBM_FLAGOUTSTATUS0_LOW */
+		},
+		.err_clear = {
+			.enable = false,
+		},
+	},
+};
+
+static struct cam_camnoc_specific
+	cam_cpas_v570_100_camnoc_specific[] = {
+	{
+		.port_type = CAM_CAMNOC_CDM,
+		.port_name = "CDM",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6030, /* CDM_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6034, /* CDM_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6038, /* CDM_URGENCY_LOW */
+			.value = 0x3,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6040, /* CDM_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6048, /* CDM_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5008, /* CDM_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5020, /* CDM_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5024, /* CDM_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_IFE_LINEAR,
+		.port_name = "IFE_LINEAR",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6430, /* IFE_LINEAR_PRIORITYLUT_LOW */
+			.value = 0x66665433,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6434, /* IFE_LINEAR_PRIORITYLUT_HIGH */
+			.value = 0x66666666,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6438, /* IFE_LINEAR_URGENCY_LOW */
+			.value = 0x1030,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.offset = 0x6440, /* IFE_LINEAR_DANGERLUT_LOW */
+			.value = 0xFFFFFF00,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.offset = 0x6448, /* IFE_LINEAR_SAFELUT_LOW */
+			.value = 0x000F,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5108, /* IFE_LINEAR_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5120, /* IFE_LINEAR_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5124, /* IFE_LINEAR_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x6420, /* IFE_LINEAR_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_IFE_RDI_RD,
+		.port_name = "IFE_RDI_RD",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6630, /* IFE_RDI_RD_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6634, /* IFE_RDI_RD_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6638, /* IFE_RDI_RD_URGENCY_LOW */
+			.value = 0x3,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.offset = 0x6640, /* IFE_RDI_RD_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.offset = 0x6648, /* IFE_RDI_RD_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5188, /* IFE_RDI_RD_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x51A0, /* IFE_RDI_RD_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x51A4, /* IFE_RDI_RD_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_IFE_RDI_WR,
+		.port_name = "IFE_RDI_WR",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6830, /* IFE_RDI_WR_0_PRIORITYLUT_LOW */
+			.value = 0x66665433,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6834, /* IFE_RDI_WR_0_PRIORITYLUT_HIGH */
+			.value = 0x66666666,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6838, /* IFE_RDI_WR_0_URGENCY_LOW */
+			.value = 0x1030,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.offset = 0x6840, /* IFE_RDI_WR_0_DANGERLUT_LOW */
+			.value = 0xFFFFFF00,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.offset = 0x6848, /* IFE_RDI_WR_0_SAFELUT_LOW */
+			.value = 0x000F,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5208, /* IFE_RDI_WR_0_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5220, /* IFE_RDI_WR_0_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5224, /* IFE_RDI_WR_0_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x6820, /* IFE_RDI_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_IFE_UBWC_STATS,
+		.port_name = "IFE_UBWC_STATS",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6230, /* IFE_UBWC_STATS_0_PRIORITYLUT_LOW */
+			.value = 0x66665433,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6234,
+			/* IFE_UBWC_STATS_0_PRIORITYLUT_HIGH */
+			.value = 0x66666666,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6238, /* IFE_UBWC_STATS_0_URGENCY_LOW */
+			.value = 0x1030,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.offset = 0x6240, /* IFE_UBWC_STATS_0_DANGERLUT_LOW */
+			.value = 0xFFFFFF00,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.offset = 0x6248, /* IFE_UBWC_STATS_0_SAFELUT_LOW */
+			.value = 0x000F,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x1B88, /* IFE_UBWC_STATS_0_ENCCTL_LOW */
+			.value = 1,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5088, /* IFE_UBWC_STATS_0_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x50A0,
+			/* IFE_UBWC_STATS_0_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x50A4,
+			/* IFE_UBWC_STATS_0_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x6220, /* IFE_UBWC_STATS_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_IPE0_RD,
+		.port_name = "IPE0_RD",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6E30, /* IPE0_RD_PRIORITYLUT_LOW */
+			.value = 0x33333333,
+		},
+		.priority_lut_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6E34, /* IPE0_RD_PRIORITYLUT_HIGH */
+			.value = 0x33333333,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6E38, /* IPE0_RD_URGENCY_LOW */
+			.value = 0x3,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6E40, /* IPE0_RD_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6E48, /* IPE0_RD_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x1F08, /* IPE0_RD_DECCTL_LOW */
+			.value = 1,
+		},
+		.qosgen_mainctl = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5388, /* IPE0_RD_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x53A0, /* IPE0_RD_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x53A4, /* IPE0_RD_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_IPE1_BPS_RD,
+		.port_name = "IPE1_BPS_RD",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6A30, /* IPE1_BPS_RD_PRIORITYLUT_LOW */
+			.value = 0x33333333,
+		},
+		.priority_lut_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6A34, /* IPE1_BPS_RD_PRIORITYLUT_HIGH */
+			.value = 0x33333333,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6A38, /* IPE1_BPS_RD_URGENCY_LOW */
+			.value = 0x3,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6A40, /* IPE1_BPS_RD_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6A48, /* IPE1_BPS_RD_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x2508, /* IPE1_BPS_RD_DECCTL_LOW */
+			.value = 1,
+		},
+		.qosgen_mainctl = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5288, /* IPE1_BPS_RD_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		//  TITAN_A_CAMNOC_cam_noc_amm_nrt_niu_0_qosgen_Shaping_Low
+		.qosgen_shaping_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x52A0, /* IPE1_BPS_RD_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x52A4, /* IPE1_BPS_RD_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_IPE_BPS_WR,
+		.port_name = "IPE_BPS_WR",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6C30, /* IPE_BPS_WR_PRIORITYLUT_LOW */
+			.value = 0x33333333,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6C34, /* IPE_BPS_WR_PRIORITYLUT_HIGH */
+			.value = 0x33333333,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6C38, /* IPE_BPS_WR_URGENCY_LOW */
+			.value = 0x30,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6C40, /* IPE_BPS_WR_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6C48, /* IPE_BPS_WR_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x2988, /* IPE_BPS_WR_ENCCTL_LOW */
+			.value = 1,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5308, /* IPE_BPS_WR_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5320, /* IPE_BPS_WR_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5324, /* IPE_BPS_WR_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x6C20, /* IFE_IPE_BPS_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_JPEG,
+		.port_name = "JPEG",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7030, /* JPEG_PRIORITYLUT_LOW */
+			.value = 0x22222222,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7034, /* JPEG_PRIORITYLUT_HIGH */
+			.value = 0x22222222,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7038, /* JPEG_URGENCY_LOW */
+			.value = 0x22,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7040, /* JPEG_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7048, /* JPEG_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5408, /* JPEG_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5420, /* JPEG_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5424, /* JPEG_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x7020, /* IFE_JPEG_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_ICP,
+		.port_name = "ICP",
+		.enable = true,
+		.flag_out_set0_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_WRITE,
+			.masked_value = 0,
+			.offset = 0x7A88,
+			.value = 0x100000,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5488, /* ICP_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x54A0, /* ICP_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x54A4, /* ICP_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+};
+
+static struct cam_camnoc_err_logger_info cam570_cpas100_err_logger_offsets = {
+	.mainctrl     =  0x7008, /* ERRLOGGER_MAINCTL_LOW */
+	.errvld       =  0x7010, /* ERRLOGGER_ERRVLD_LOW */
+	.errlog0_low  =  0x7020, /* ERRLOGGER_ERRLOG0_LOW */
+	.errlog0_high =  0x7024, /* ERRLOGGER_ERRLOG0_HIGH */
+	.errlog1_low  =  0x7028, /* ERRLOGGER_ERRLOG1_LOW */
+	.errlog1_high =  0x702c, /* ERRLOGGER_ERRLOG1_HIGH */
+	.errlog2_low  =  0x7030, /* ERRLOGGER_ERRLOG2_LOW */
+	.errlog2_high =  0x7034, /* ERRLOGGER_ERRLOG2_HIGH */
+	.errlog3_low  =  0x7038, /* ERRLOGGER_ERRLOG3_LOW */
+	.errlog3_high =  0x703c, /* ERRLOGGER_ERRLOG3_HIGH */
+};
+
+static struct cam_cpas_hw_errata_wa_list cam570_cpas100_errata_wa_list = {
+	.camnoc_flush_slave_pending_trans = {
+		.enable = false,
+	},
+};
+
+static struct cam_camnoc_info cam570_cpas100_camnoc_info = {
+	.specific = &cam_cpas_v570_100_camnoc_specific[0],
+	.specific_size = ARRAY_SIZE(cam_cpas_v570_100_camnoc_specific),
+	.irq_sbm = &cam_cpas_v570_100_irq_sbm,
+	.irq_err = &cam_cpas_v570_100_irq_err[0],
+	.irq_err_size = ARRAY_SIZE(cam_cpas_v570_100_irq_err),
+	.err_logger = &cam570_cpas100_err_logger_offsets,
+	.errata_wa_list = &cam570_cpas100_errata_wa_list,
+};
+
+static struct cam_cpas_camnoc_qchannel cam570_cpas100_qchannel_info = {
+	.qchannel_ctrl   = 0x5C,
+	.qchannel_status = 0x60,
+};
+#endif /* _CPASTOP_V570_100_H_ */

drivers/cam_cpas/include/cam_cpas_api.h

@@ -144,6 +144,7 @@ enum cam_cpas_hw_version {
 	CAM_CPAS_TITAN_540_V100 = 0x540100,
 	CAM_CPAS_TITAN_520_V100 = 0x520100,
 	CAM_CPAS_TITAN_545_V100 = 0x545100,
+	CAM_CPAS_TITAN_570_V100 = 0x570100,
 	CAM_CPAS_TITAN_570_V200 = 0x570200,
 	CAM_CPAS_TITAN_680_V100 = 0x680100,
 	CAM_CPAS_TITAN_780_V100 = 0x780100,

drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.c

@@ -33,6 +33,24 @@
 
 static struct cam_cre_hw_mgr *cre_hw_mgr;
 
+static bool cam_cre_debug_clk_update(struct cam_cre_clk_info *hw_mgr_clk_info)
+{
+	if (cre_hw_mgr.cre_debug_clk &&
+		cre_hw_mgr.cre_debug_clk != hw_mgr_clk_info->curr_clk) {
+		hw_mgr_clk_info->base_clk = cre_hw_mgr.cre_debug_clk;
+		hw_mgr_clk_info->curr_clk = cre_hw_mgr.cre_debug_clk;
+		hw_mgr_clk_info->uncompressed_bw = cre_hw_mgr.cre_debug_clk;
+		hw_mgr_clk_info->compressed_bw = cre_hw_mgr.cre_debug_clk;
+		CAM_DBG(CAM_PERF, "bc = %d cc = %d ub %d cb %d",
+			hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk,
+			hw_mgr_clk_info->uncompressed_bw,
+			hw_mgr_clk_info->compressed_bw);
+		return true;
+	}
+
+	return false;
+}
+
 static struct cam_cre_io_buf_info *cam_cre_mgr_get_rsc(
 	struct cam_cre_ctx *ctx_data,
 	struct cam_buf_io_cfg *in_io_buf)
@@ -1200,6 +1218,9 @@ static bool cam_cre_check_clk_update(struct cam_cre_hw_mgr *hw_mgr,
 		clk_info->frame_cycles, clk_info->budget_ns);
 	ctx_data->clk_info.rt_flag = clk_info->rt_flag;
 
+	if (cre_hw_mgr.cre_debug_clk)
+		return cam_cre_debug_clk_update(hw_mgr_clk_info);
+
 	if (busy)
 		rc = cam_cre_update_clk_busy(hw_mgr, ctx_data,
 			hw_mgr_clk_info, clk_info, base_clk);
@@ -2869,6 +2890,15 @@ static int cam_cre_create_debug_fs(void)
 		goto err;
 	}
 
+	dbgfileptr = debugfs_create_file("cre_debug_clk", 0644,
+		cre_hw_mgr.dentry, NULL, &cam_cre_debug_default_clk);
+
+	if (IS_ERR(dbgfileptr)) {
+		if (PTR_ERR(dbgfileptr) == -ENODEV)
+			CAM_WARN(CAM_CRE, "DebugFS not enabled in kernel!");
+		else
+			rc = PTR_ERR(dbgfileptr);
+	}
 	return 0;
 err:
 	debugfs_remove_recursive(cre_hw_mgr->dentry);
@@ -2999,3 +3029,19 @@ cre_ctx_bitmap_failed:
 
 	return rc;
 }
+
+static int cam_cre_set_dbg_default_clk(void *data, u64 val)
+{
+	cre_hw_mgr.cre_debug_clk = val;
+	return 0;
+}
+
+static int cam_cre_get_dbg_default_clk(void *data, u64 *val)
+{
+	*val = cre_hw_mgr.cre_debug_clk;
+	return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(cam_cre_debug_default_clk,
+	cam_cre_get_dbg_default_clk,
+	cam_cre_set_dbg_default_clk, "%16llu");

drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.h

@@ -370,6 +370,7 @@ struct cam_cre_hw_mgr {
 	int32_t       iommu_hdl;
 	int32_t       iommu_sec_hdl;
 	uint32_t      num_cre;
+	uint64_t      cre_debug_clk;
 	bool          secure_mode;
 	void    *ctx_bitmap;
 	size_t   ctx_bitmap_size;

drivers/cam_icp/fw_inc/hfi_intf.h

@@ -141,6 +141,12 @@ int hfi_set_debug_level(u64 icp_dbg_type, uint32_t lvl);
  */
 int hfi_set_fw_dump_level(uint32_t lvl);
 
+/**
+ * hfi_send_freq_info() - set firmware dump level
+ * @freq: icp freq
+ */
+int hfi_send_freq_info(int32_t freq);
+
 /**
  * hfi_enable_ipe_bps_pc() - Enable interframe pc
  * Host sends a command to firmware to enable interframe

drivers/cam_icp/fw_inc/hfi_reg.h

@@ -278,6 +278,7 @@ struct hfi_qtbl {
  * @mutex msg_q_lock: Lock for message queue
  * @msg_q_state: State of message queue
  * @priv: device private data
+ * @dbg_lvl: debug level set to FW
  */
 struct hfi_info {
 	struct hfi_mem_info map;
@@ -291,6 +292,7 @@ struct hfi_info {
 	struct mutex msg_q_lock;
 	bool msg_q_state;
 	void *priv;
+	u64 dbg_lvl;
 };
 
 #endif /* _CAM_HFI_REG_H_ */

drivers/cam_icp/fw_inc/hfi_sys_defs.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- *  Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+ *  Copyright (c) 2017-2019, 2021 The Linux Foundation. All rights reserved.
  */
 
 #ifndef _HFI_DEFS_H_
@@ -169,13 +169,14 @@
 /* System  level property base offset */
 #define HFI_PROPERTY_ICP_COMMON_START  (HFI_DOMAIN_BASE_ICP + 0x0)
 
-#define HFI_PROP_SYS_DEBUG_CFG           (HFI_PROPERTY_ICP_COMMON_START + 0x1)
-#define HFI_PROP_SYS_UBWC_CFG            (HFI_PROPERTY_ICP_COMMON_START + 0x2)
-#define HFI_PROP_SYS_IMAGE_VER           (HFI_PROPERTY_ICP_COMMON_START + 0x3)
-#define HFI_PROP_SYS_SUPPORTED           (HFI_PROPERTY_ICP_COMMON_START + 0x4)
-#define HFI_PROP_SYS_IPEBPS_PC           (HFI_PROPERTY_ICP_COMMON_START + 0x5)
-#define HFI_PROP_SYS_FW_DUMP_CFG         (HFI_PROPERTY_ICP_COMMON_START + 0x8)
-#define HFI_PROPERTY_SYS_UBWC_CONFIG_EX  (HFI_PROPERTY_ICP_COMMON_START + 0x9)
+#define HFI_PROP_SYS_DEBUG_CFG             (HFI_PROPERTY_ICP_COMMON_START + 0x1)
+#define HFI_PROP_SYS_UBWC_CFG              (HFI_PROPERTY_ICP_COMMON_START + 0x2)
+#define HFI_PROP_SYS_IMAGE_VER             (HFI_PROPERTY_ICP_COMMON_START + 0x3)
+#define HFI_PROP_SYS_SUPPORTED             (HFI_PROPERTY_ICP_COMMON_START + 0x4)
+#define HFI_PROP_SYS_IPEBPS_PC             (HFI_PROPERTY_ICP_COMMON_START + 0x5)
+#define HFI_PROP_SYS_FW_DUMP_CFG           (HFI_PROPERTY_ICP_COMMON_START + 0x8)
+#define HFI_PROPERTY_SYS_UBWC_CONFIG_EX    (HFI_PROPERTY_ICP_COMMON_START + 0x9)
+#define HFI_PROPERTY_SYS_ICP_HW_FREQUENCY  (HFI_PROPERTY_ICP_COMMON_START + 0xa)
 
 /* Capabilities reported at sys init */
 #define HFI_CAPS_PLACEHOLDER_1         (HFI_COMMON_BASE + 0x1)

drivers/cam_icp/hfi.c

@@ -38,6 +38,7 @@
 
 static struct hfi_info *g_hfi;
 unsigned int g_icp_mmu_hdl;
+
 static DEFINE_MUTEX(hfi_cmd_q_mutex);
 static DEFINE_MUTEX(hfi_msg_q_mutex);
 
@@ -460,6 +461,9 @@ int hfi_set_debug_level(u64 icp_dbg_type, uint32_t lvl)
 	if (lvl > val)
 		return -EINVAL;
 
+	if (g_hfi)
+		g_hfi->dbg_lvl = lvl;
+
 	size = sizeof(struct hfi_cmd_prop) +
 		sizeof(struct hfi_debug);
 
@@ -517,6 +521,50 @@ int hfi_set_fw_dump_level(uint32_t lvl)
 	return 0;
 }
 
+int hfi_send_freq_info(int32_t freq)
+{
+	uint8_t *prop = NULL;
+	struct hfi_cmd_prop *dbg_prop = NULL;
+	uint32_t size = 0;
+
+	if (!g_hfi) {
+		CAM_ERR(CAM_HFI, "HFI interface not setup");
+		return -ENODEV;
+	}
+
+	if (!(g_hfi->dbg_lvl & HFI_DEBUG_MSG_PERF))
+		return -EINVAL;
+
+	size = sizeof(struct hfi_cmd_prop) + sizeof(freq);
+	prop = kzalloc(size, GFP_KERNEL);
+	if (!prop)
+		return -ENOMEM;
+
+	dbg_prop = (struct hfi_cmd_prop *)prop;
+	dbg_prop->size = size;
+	dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
+	dbg_prop->num_prop = 1;
+	dbg_prop->prop_data[0] = HFI_PROPERTY_SYS_ICP_HW_FREQUENCY;
+	dbg_prop->prop_data[1] = freq;
+
+	CAM_DBG(CAM_HFI, "prop->size = %d\n"
+			 "prop->pkt_type = %d\n"
+			 "prop->num_prop = %d\n"
+			 "prop->prop_data[0] = %d\n"
+			 "prop->prop_data[1] = %d\n"
+			 "dbg_lvl = 0x%x\n",
+			 dbg_prop->size,
+			 dbg_prop->pkt_type,
+			 dbg_prop->num_prop,
+			 dbg_prop->prop_data[0],
+			 dbg_prop->prop_data[1],
+			 g_hfi->dbg_lvl);
+
+	hfi_write_cmd(prop);
+	kfree(prop);
+	return 0;
+}
+
 void hfi_send_system_cmd(uint32_t type, uint64_t data, uint32_t size)
 {
 	switch (type) {

drivers/cam_icp/icp_hw/a5_hw/a5_soc.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/io.h>
@@ -11,6 +11,7 @@
 #include "a5_soc.h"
 #include "cam_soc_util.h"
 #include "cam_debug_util.h"
+#include "hfi_intf.h"
 
 static int cam_a5_get_dt_properties(struct cam_hw_soc_info *soc_info)
 {
@@ -192,6 +193,12 @@ int cam_a5_enable_soc_resources(struct cam_hw_soc_info *soc_info)
 		CAM_SVS_VOTE, true);
 	if (rc)
 		CAM_ERR(CAM_ICP, "enable platform failed");
+	else {
+		int32_t clk_rate = 0;
+
+		clk_rate = clk_get_rate(soc_info->clk[soc_info->src_clk_idx]);
+		hfi_send_freq_info(clk_rate);
+	}
 
 	return rc;
 }
@@ -203,6 +210,8 @@ int cam_a5_disable_soc_resources(struct cam_hw_soc_info *soc_info)
 	rc = cam_soc_util_disable_platform_resource(soc_info, true, true);
 	if (rc)
 		CAM_ERR(CAM_ICP, "disable platform failed");
+	else
+		hfi_send_freq_info(0);
 
 	return rc;
 }
@@ -212,6 +221,7 @@ int cam_a5_update_clk_rate(struct cam_hw_soc_info *soc_info,
 {
 	int32_t src_clk_idx = 0;
 	int32_t clk_rate = 0;
+	int rc = 0;
 
 	if (!soc_info) {
 		CAM_ERR(CAM_ICP, "Invalid args");
@@ -248,5 +258,10 @@ int cam_a5_update_clk_rate(struct cam_hw_soc_info *soc_info,
 		clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx];
 	}
 
-	return cam_soc_util_set_src_clk_rate(soc_info, clk_rate);
+	rc = cam_soc_util_set_src_clk_rate(soc_info, clk_rate);
+	if (rc)
+		return rc;
+
+	hfi_send_freq_info(clk_rate);
+	return 0;
 }

drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c

@@ -45,6 +45,8 @@
 #include "cam_trace.h"
 #include "cam_cpas_api.h"
 #include "cam_common_util.h"
+#include "cam_mem_mgr_api.h"
+#include "cam_presil_hw_access.h"
 
 #define ICP_WORKQ_TASK_CMD_TYPE 1
 #define ICP_WORKQ_TASK_MSG_TYPE 2
@@ -4391,6 +4393,13 @@ static int cam_icp_mgr_config_hw(void *hw_mgr_priv, void *config_hw_args)
 	req_id = frame_info->request_id;
 	idx = cam_icp_clk_idx_from_req_id(ctx_data, req_id);
 
+	if (cam_presil_mode_enabled()) {
+		CAM_INFO(CAM_ICP, "Sending relevant buffers for request: %llu to presil",
+			config_args->request_id);
+		cam_presil_send_buffers_from_packet(frame_info->pkt, hw_mgr->iommu_hdl,
+			hw_mgr->iommu_hdl);
+	}
+
 	cam_icp_mgr_ipe_bps_clk_update(hw_mgr, ctx_data, idx);
 	ctx_data->hfi_frame_process.fw_process_flag[idx] = true;
 	ctx_data->hfi_frame_process.submit_timestamp[idx] = ktime_get();
@@ -4642,10 +4651,14 @@ static int cam_icp_mgr_process_io_cfg(struct cam_icp_hw_mgr *hw_mgr,
 			sync_in_obj[j++] = io_cfg_ptr[i].fence;
 			prepare_args->num_in_map_entries++;
 		} else {
-			prepare_args->out_map_entries[k++].sync_id =
+			prepare_args->out_map_entries[k].sync_id =
 				io_cfg_ptr[i].fence;
+			prepare_args->out_map_entries[k].resource_handle =
+				io_cfg_ptr[i].resource_type;
+			k++;
 			prepare_args->num_out_map_entries++;
 		}
+
 		CAM_DBG(CAM_REQ,
 			"ctx_id: %u req_id: %llu dir[%d]: %u, fence: %u resource_type = %u memh %x",
 			ctx_data->ctx_id, packet->header.request_id, i,
@@ -5066,6 +5079,7 @@ static int cam_icp_mgr_update_hfi_frame_process(
 	ctx_data->hfi_frame_process.frame_info[index].request_id =
 		packet->header.request_id;
 	ctx_data->hfi_frame_process.frame_info[index].io_config = 0;
+        ctx_data->hfi_frame_process.frame_info[index].pkt = packet;
 	rc = cam_icp_process_generic_cmd_buffer(packet, ctx_data, index,
 		&ctx_data->hfi_frame_process.frame_info[index].io_config);
 	if (rc) {
@@ -6038,6 +6052,13 @@ static int cam_icp_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args)
 		goto send_map_info_failed;
 	}
 
+	if (cam_presil_mode_enabled()) {
+		CAM_INFO(CAM_PRESIL, "Sending IO Config buffers to presil: FD %d ",
+			(icp_dev_acquire_info->io_config_cmd_handle >> 16));
+		cam_mem_mgr_send_buffer_to_presil(icp_hw_mgr.iommu_hdl,
+			icp_dev_acquire_info->io_config_cmd_handle);
+	}
+
 	rc = cam_icp_mgr_send_config_io(ctx_data, io_buf_addr);
 	if (rc) {
 		CAM_ERR_RATE_LIMIT(CAM_ICP,
@@ -6529,6 +6550,7 @@ int cam_icp_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl,
 
 	if ((camera_hw_version == CAM_CPAS_TITAN_480_V100) ||
 		(camera_hw_version == CAM_CPAS_TITAN_580_V100) ||
+		(camera_hw_version == CAM_CPAS_TITAN_570_V100) ||
 		(camera_hw_version == CAM_CPAS_TITAN_570_V200) ||
 		(camera_hw_version == CAM_CPAS_TITAN_680_V100) ||
 		(camera_hw_version == CAM_CPAS_TITAN_780_V100)) {

drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h

@@ -145,11 +145,13 @@ struct clk_work_data {
  * @request_id: request id
  * @io_config: the address of io config
  * @hfi_cfg_io_cmd: command struct to be sent to hfi
+ * @pkt: pointer to the packet header of current request
  */
 struct icp_frame_info {
 	uint64_t request_id;
 	dma_addr_t io_config;
 	struct hfi_cmd_ipebps_async hfi_cfg_io_cmd;
+	struct cam_packet *pkt;
 };
 
 /**

drivers/cam_icp/icp_hw/lx7_hw/lx7_soc.c

@@ -9,6 +9,7 @@
 #include "cam_debug_util.h"
 #include "cam_soc_util.h"
 #include "lx7_soc.h"
+#include "hfi_intf.h"
 
 static int __ubwc_config_get(struct device_node *np, char *name, uint32_t *cfg)
 {
@@ -141,6 +142,12 @@ int cam_lx7_soc_resources_enable(struct cam_hw_soc_info *soc_info)
 						CAM_SVS_VOTE, true);
 	if (rc)
 		CAM_ERR(CAM_ICP, "failed to enable soc resources rc=%d", rc);
+	else {
+		int32_t clk_rate = 0;
+
+		clk_rate = clk_get_rate(soc_info->clk[soc_info->src_clk_idx]);
+		hfi_send_freq_info(clk_rate);
+	}
 
 	return rc;
 }
@@ -152,6 +159,8 @@ int cam_lx7_soc_resources_disable(struct cam_hw_soc_info *soc_info)
 	rc = cam_soc_util_disable_platform_resource(soc_info, true, true);
 	if (rc)
 		CAM_ERR(CAM_ICP, "failed to disable soc resources rc=%d", rc);
+	else
+		hfi_send_freq_info(0);
 
 	return rc;
 }
@@ -161,6 +170,7 @@ int cam_lx7_update_clk_rate(struct cam_hw_soc_info *soc_info,
 {
 	int32_t src_clk_idx = 0;
 	int32_t clk_rate = 0;
+	int rc = 0;
 
 	if (!soc_info) {
 		CAM_ERR(CAM_ICP, "Invalid args");
@@ -197,5 +207,10 @@ int cam_lx7_update_clk_rate(struct cam_hw_soc_info *soc_info,
 		clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx];
 	}
 
-	return cam_soc_util_set_src_clk_rate(soc_info, clk_rate);
+	rc = cam_soc_util_set_src_clk_rate(soc_info, clk_rate);
+	if (rc)
+		return rc;
+
+	hfi_send_freq_info(clk_rate);
+	return 0;
 }

drivers/cam_isp/cam_isp_context.h

@@ -103,6 +103,9 @@ enum cam_isp_state_change_trigger {
 	CAM_ISP_STATE_CHANGE_TRIGGER_DONE,
 	CAM_ISP_STATE_CHANGE_TRIGGER_EOF,
 	CAM_ISP_STATE_CHANGE_TRIGGER_FLUSH,
+	CAM_ISP_STATE_CHANGE_TRIGGER_SEC_EVT_SOF,
+	CAM_ISP_STATE_CHANGE_TRIGGER_SEC_EVT_EPOCH,
+	CAM_ISP_STATE_CHANGE_TRIGGER_FRAME_DROP,
 	CAM_ISP_STATE_CHANGE_TRIGGER_MAX
 };
 
@@ -111,13 +114,15 @@ enum cam_isp_state_change_trigger {
  *
  * @dentry:                     Debugfs entry
  * @enable_state_monitor_dump:  Enable isp state monitor dump
- * @enable_cdm_cmd_buff_dump: Enable CDM Command buffer dump
+ * @enable_cdm_cmd_buff_dump:   Enable CDM Command buffer dump
+ * @disable_internal_recovery:  Disable internal kernel recovery
  *
  */
 struct cam_isp_ctx_debug {
 	struct dentry  *dentry;
 	uint32_t        enable_state_monitor_dump;
 	uint8_t         enable_cdm_cmd_buff_dump;
+	bool            disable_internal_recovery;
 };
 
 /**
@@ -153,8 +158,8 @@ struct cam_isp_ctx_irq_ops {
  * @bubble_report:             Flag to track if bubble report is active on
  *                             current request
  * @hw_update_data:            HW update data for this request
+ * @reapply_type:              Determines type of settings to be re-applied
  * @event_timestamp:           Timestamp for different stage of request
- * @reapply:                   True if reapplying after bubble
  * @cdm_reset_before_apply:    For bubble re-apply when buf done not coming set
  *                             to True
  *
@@ -172,10 +177,10 @@ struct cam_isp_ctx_req {
 	uint32_t                  deferred_fence_map_index[CAM_ISP_CTX_RES_MAX];
 	int32_t                               bubble_report;
 	struct cam_isp_prepare_hw_update_data hw_update_data;
+	enum cam_hw_config_reapply_type       reapply_type;
 	ktime_t                               event_timestamp
 		[CAM_ISP_CTX_EVENT_MAX];
 	bool                                  bubble_detected;
-	bool                                  reapply;
 	bool                                  cdm_reset_before_apply;
 };
 
@@ -248,6 +253,7 @@ struct cam_isp_context_event_record {
  * @subscribe_event:           The irq event mask that CRM subscribes to, IFE
  *                             will invoke CRM cb at those event.
  * @last_applied_req_id:       Last applied request id
+ * @recovery_req_id:           Req ID flagged for internal recovery
  * @last_sof_timestamp:        SOF timestamp of the last frame
  * @bubble_frame_cnt:          Count of the frame after bubble
  * @state_monitor_head:        Write index to the state monitoring array
@@ -264,7 +270,6 @@ struct cam_isp_context_event_record {
  * @custom_enabled:            Custom HW enabled for this ctx
  * @use_frame_header_ts:       Use frame header for qtimer ts
  * @support_consumed_addr:     Indicate whether HW has last consumed addr reg
- * @aeb_enabled:               Indicate if stream is for AEB
  * @apply_in_progress          Whether request apply is in progress
  * @use_default_apply:         Use default settings in case of frame skip
  * @init_timestamp:            Timestamp at which this context is initialized
@@ -275,12 +280,14 @@ struct cam_isp_context_event_record {
  * @trigger_id:                ID provided by CRM for each ctx on the link
  * @last_bufdone_err_apply_req_id:  last bufdone error apply request id
  * @v4l2_event_sub_ids         contains individual bits representing subscribed v4l2 ids
+ * @aeb_enabled:               Indicate if stream is for AEB
+ * @do_internal_recovery:      Enable KMD halt/reset/resume internal recovery
  *
  */
 struct cam_isp_context {
 	struct cam_context              *base;
 
-	int64_t                          frame_id;
+	uint64_t                         frame_id;
 	uint32_t                         frame_id_meta;
 	uint32_t                         substate_activated;
 	atomic_t                         process_bubble;
@@ -297,6 +304,7 @@ struct cam_isp_context {
 	int64_t                          reported_req_id;
 	uint32_t                         subscribe_event;
 	int64_t                          last_applied_req_id;
+	uint64_t                         recovery_req_id;
 	uint64_t                         last_sof_timestamp;
 	uint32_t                         bubble_frame_cnt;
 	atomic64_t                       state_monitor_head;
@@ -315,8 +323,8 @@ struct cam_isp_context {
 	bool                                  custom_enabled;
 	bool                                  use_frame_header_ts;
 	bool                                  support_consumed_addr;
-	bool                                  aeb_enabled;
 	atomic_t                              apply_in_progress;
+	atomic_t                              internal_recovery_set;
 	bool                                  use_default_apply;
 	unsigned int                          init_timestamp;
 	uint32_t                              isp_device_type;
@@ -325,6 +333,8 @@ struct cam_isp_context {
 	int32_t                               trigger_id;
 	int64_t                               last_bufdone_err_apply_req_id;
 	uint32_t                              v4l2_event_sub_ids;
+	bool                                  aeb_enabled;
+	bool                                  do_internal_recovery;
 };
 
 /**
@@ -345,6 +355,7 @@ struct cam_isp_context_dump_header {
  * @map_out:                   Output fence mapping
  * @map_in:                    Input fence mapping
  * @io_cfg:                    IO buffer configuration
+ * @reapply_type:              Determines type of settings to be re-applied
  * @request_id:                Request ID
  * @num_fence_map_out:         Number of the output fence map
  * @num_fence_map_in:          Number of input fence map
@@ -358,7 +369,6 @@ struct cam_isp_context_dump_header {
  * @bubble_report:             Flag to track if bubble report is active on
  *                             current request
  * @bubble_detected:           Flag to track if bubble is detected
- * @reapply:                   True if reapplying after bubble
  * @cdm_reset_before_apply:    For bubble re-apply when buf done not coming set
  *                             to True
  *
@@ -367,6 +377,7 @@ struct cam_isp_ctx_req_mini_dump {
 	struct cam_hw_fence_map_entry   *map_out;
 	struct cam_hw_fence_map_entry   *map_in;
 	struct cam_buf_io_cfg           *io_cfg;
+	enum cam_hw_config_reapply_type  reapply_type;
 	uint64_t                         request_id;
 	uint8_t                          num_fence_map_in;
 	uint8_t                          num_fence_map_out;
@@ -375,7 +386,6 @@ struct cam_isp_ctx_req_mini_dump {
 	uint8_t                          num_deferred_acks;
 	bool                             bubble_report;
 	bool                             bubble_detected;
-	bool                             reapply;
 	bool                             cdm_reset_before_apply;
 };
 

drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h

@@ -153,6 +153,7 @@ struct cam_ife_hw_mgr_sfe_info {
  * @dump_on_flush:       Set if reg dump triggered on flush
  * @dump_on_error:       Set if reg dump triggered on error
  * @custom_aeb_mode:     Set if custom AEB stream
+ * @rdi_lcr_en:          To indicate if RDI LCR is enabled
  * @sys_cache_usage:     Per context sys cache usage
  *                       The corresponding index will be set
  *                       for the cache type
@@ -175,6 +176,7 @@ struct cam_ife_hw_mgr_ctx_flags {
 	bool   dump_on_flush;
 	bool   dump_on_error;
 	bool   is_aeb_mode;
+	bool   rdi_lcr_en;
 	bool   sys_cache_usage[CAM_LLCC_MAX];
 };
 
@@ -239,6 +241,8 @@ struct cam_ife_cdm_user_data {
  * @flags                   Flags pertainting to this ctx
  * @bw_config_version       BW Config version
  * @recovery_id:            Unique ID of the current valid scheduled recovery
+ * @current_mup:            Current MUP val, scratch will then apply the same as previously
+ *                          applied request
  *
  */
 struct cam_ife_hw_mgr_ctx {
@@ -294,6 +298,7 @@ struct cam_ife_hw_mgr_ctx {
 	struct cam_ife_cdm_user_data      cdm_userdata;
 	uint32_t                          bw_config_version;
 	atomic_t                          recovery_id;
+	uint32_t                          current_mup;
 };
 
 /**

drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.h

@@ -69,6 +69,7 @@ struct cam_isp_hw_mgr {
  *                       acquired
  * @is_secure            informs whether the resource is in secure mode or not
  * @num_children:        number of the child resource node.
+ * @use_wm_pack:         Flag to indicate if WM is to be used for packing
  *
  */
 struct cam_isp_hw_mgr_res {
@@ -79,6 +80,7 @@ struct cam_isp_hw_mgr_res {
 	struct cam_isp_resource_node    *hw_res[CAM_ISP_HW_SPLIT_MAX];
 	uint32_t                         is_secure;
 	uint32_t                         num_children;
+	bool                             use_wm_pack;
 };
 
 

drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c

@@ -2635,7 +2635,7 @@ static int cam_tfe_mgr_config_hw(void *hw_mgr_priv,
 	hw_update_data = (struct cam_isp_prepare_hw_update_data  *) cfg->priv;
 	hw_update_data->isp_mgr_ctx = ctx;
 
-	if (cfg->reapply && cfg->cdm_reset_before_apply) {
+	if (cfg->reapply_type && cfg->cdm_reset_before_apply) {
 		if (ctx->last_cdm_done_req < cfg->request_id) {
 			cdm_hang_detect =
 				cam_cdm_detect_hang_error(ctx->cdm_handle);
@@ -2699,7 +2699,8 @@ static int cam_tfe_mgr_config_hw(void *hw_mgr_priv,
 
 	for (i = 0; i < cfg->num_hw_update_entries; i++) {
 		cmd = (cfg->hw_update_entries + i);
-		if (cfg->reapply && cmd->flags == CAM_ISP_IQ_BL) {
+		if ((cfg->reapply_type == CAM_CONFIG_REAPPLY_IO) &&
+			(cmd->flags == CAM_ISP_IQ_BL)) {
 			skip++;
 			continue;
 		}
@@ -5309,6 +5310,7 @@ end:
 }
 
 static int cam_tfe_hw_mgr_handle_csid_event(
+	uint32_t                      err_type,
 	struct cam_isp_hw_event_info *event_info)
 {
 	struct cam_isp_hw_error_event_data  error_event_data = {0};
@@ -5317,13 +5319,13 @@ static int cam_tfe_hw_mgr_handle_csid_event(
 	/* this can be extended based on the types of error
 	 * received from CSID
 	 */
-	switch (event_info->err_type) {
+	switch (err_type) {
 	case CAM_ISP_HW_ERROR_CSID_FATAL: {
 
 		if (!g_tfe_hw_mgr.debug_cfg.enable_csid_recovery)
 			break;
 
-		error_event_data.error_type = event_info->err_type;
+		error_event_data.error_type = err_type;
 		error_event_data.error_code = CAM_REQ_MGR_CSID_FATAL_ERROR;
 		cam_tfe_hw_mgr_find_affected_ctx(&error_event_data,
 			event_info->hw_idx,
@@ -5339,13 +5341,20 @@ static int cam_tfe_hw_mgr_handle_csid_event(
 static int cam_tfe_hw_mgr_handle_hw_err(
 	void                                *evt_info)
 {
+	struct cam_isp_hw_error_event_info      *err_evt_info;
 	struct cam_isp_hw_event_info            *event_info = evt_info;
 	struct cam_isp_hw_error_event_data       error_event_data = {0};
 	struct cam_tfe_hw_event_recovery_data    recovery_data = {0};
 	int    rc = -EINVAL;
 	uint32_t core_idx;
 
-	if (event_info->err_type == CAM_TFE_IRQ_STATUS_VIOLATION)
+	if (!event_info->event_data) {
+		CAM_ERR(CAM_ISP, "No error event data failed to process");
+		return rc;
+	}
+
+	err_evt_info = (struct cam_isp_hw_error_event_info *)event_info->event_data;
+	if (err_evt_info->err_type == CAM_TFE_IRQ_STATUS_VIOLATION)
 		error_event_data.error_type = CAM_ISP_HW_ERROR_VIOLATION;
 	else if (event_info->res_type == CAM_ISP_RESOURCE_TFE_IN ||
 		event_info->res_type == CAM_ISP_RESOURCE_PIX_PATH)
@@ -5354,8 +5363,8 @@ static int cam_tfe_hw_mgr_handle_hw_err(
 		error_event_data.error_type = CAM_ISP_HW_ERROR_BUSIF_OVERFLOW;
 
 	spin_lock(&g_tfe_hw_mgr.ctx_lock);
-	if (event_info->err_type == CAM_ISP_HW_ERROR_CSID_FATAL) {
-		rc = cam_tfe_hw_mgr_handle_csid_event(event_info);
+	if (err_evt_info->err_type == CAM_ISP_HW_ERROR_CSID_FATAL) {
+		rc = cam_tfe_hw_mgr_handle_csid_event(err_evt_info->err_type, event_info);
 		spin_unlock(&g_tfe_hw_mgr.ctx_lock);
 		return rc;
 	}
@@ -5381,7 +5390,7 @@ static int cam_tfe_hw_mgr_handle_hw_err(
 
 	if (g_tfe_hw_mgr.debug_cfg.enable_recovery) {
 		/* Trigger for recovery */
-		if (event_info->err_type == CAM_TFE_IRQ_STATUS_VIOLATION)
+		if (err_evt_info->err_type == CAM_TFE_IRQ_STATUS_VIOLATION)
 			recovery_data.error_type = CAM_ISP_HW_ERROR_VIOLATION;
 		else
 			recovery_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW;

drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c

@@ -66,8 +66,8 @@ int cam_isp_add_change_base(
 			hw_entry[num_ent].len    = get_base.cmd.used_bytes;
 			hw_entry[num_ent].offset = kmd_buf_info->offset;
 
-			/* Marking change base as IOCFG to reapply on bubble */
-			hw_entry[num_ent].flags  = CAM_ISP_IOCFG_BL;
+			/* Marking change base as COMMON_CFG */
+			hw_entry[num_ent].flags  = CAM_ISP_COMMON_CFG_BL;
 			CAM_DBG(CAM_ISP,
 				"num_ent=%d handle=0x%x, len=%u, offset=%u",
 				num_ent,
@@ -1238,8 +1238,8 @@ int cam_isp_add_reg_update(
 		prepare->hw_update_entries[num_ent].offset =
 			kmd_buf_info->offset;
 
-		/* Marking reg update as IOCFG to reapply on bubble */
-		prepare->hw_update_entries[num_ent].flags = CAM_ISP_IOCFG_BL;
+		/* Marking reg update as COMMON */
+		prepare->hw_update_entries[num_ent].flags = CAM_ISP_COMMON_CFG_BL;
 		CAM_DBG(CAM_ISP,
 			"num_ent=%d handle=0x%x, len=%u, offset=%u",
 			num_ent,
@@ -1333,7 +1333,7 @@ int cam_isp_add_go_cmd(
 		prepare->hw_update_entries[num_ent].len = reg_update_size;
 		prepare->hw_update_entries[num_ent].offset =
 			kmd_buf_info->offset;
-		prepare->hw_update_entries[num_ent].flags = CAM_ISP_IOCFG_BL;
+		prepare->hw_update_entries[num_ent].flags = CAM_ISP_COMMON_CFG_BL;
 		CAM_DBG(CAM_ISP,
 			"num_ent=%d handle=0x%x, len=%u, offset=%u",
 			num_ent,
@@ -1748,8 +1748,8 @@ int cam_isp_add_csid_reg_update(
 		prepare->hw_update_entries[num_ent].offset =
 			kmd_buf_info->offset;
 
-		/* Marking reg update as IOCFG to reapply on bubble */
-		prepare->hw_update_entries[num_ent].flags = CAM_ISP_IOCFG_BL;
+		/* Marking reg update as COMMON */
+		prepare->hw_update_entries[num_ent].flags = CAM_ISP_COMMON_CFG_BL;
 		CAM_DBG(CAM_ISP,
 			"num_ent=%d handle=0x%x, len=%u, offset=%u",
 			num_ent,
@@ -1846,8 +1846,8 @@ go_cmd_added:
 		prepare->hw_update_entries[num_ent].offset =
 			kmd_buf_info->offset;
 
-		/* Marking go update as IOCFG to reapply on bubble */
-		prepare->hw_update_entries[num_ent].flags = CAM_ISP_IOCFG_BL;
+		/* Marking go update as COMMON */
+		prepare->hw_update_entries[num_ent].flags = CAM_ISP_COMMON_CFG_BL;
 		CAM_DBG(CAM_ISP,
 			"num_ent=%d handle=0x%x, len=%u, offset=%u",
 			num_ent,

drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h

@@ -14,9 +14,10 @@
 #include "cam_packet_util.h"
 #include "cam_cdm_intf_api.h"
 
-/* enum cam_isp_cdm_bl_type - isp cdm packet type*/
+/* enum cam_isp_cdm_bl_type - isp cdm packet type */
 enum cam_isp_cdm_bl_type {
 	CAM_ISP_UNUSED_BL,
+	CAM_ISP_COMMON_CFG_BL,
 	CAM_ISP_IQ_BL,
 	CAM_ISP_IOCFG_BL,
 	CAM_ISP_BL_MAX,

drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c

@@ -11,6 +11,7 @@
 #include "cam_io_util.h"
 #include "cam_irq_controller.h"
 #include "cam_debug_util.h"
+#include "cam_common_util.h"
 
 /**
  * struct cam_irq_evt_handler:
@@ -94,12 +95,13 @@ struct cam_irq_register_obj {
  * @th_list_head:           List of handlers sorted by priority
  * @hdl_idx:                Unique identity of handler assigned on Subscribe.
  *                          Used to Unsubscribe.
- * @lock:                   Lock for use by controller
  * @th_payload:             Payload structure to be passed to top half handler
  * @is_dependent:           Flag to indicate is this controller is dependent on another controller
  * @dependent_controller:   Array of controllers that depend on this controller
  * @delayed_global_clear:   Flag to indicate if this controller issues global clear after dependent
  *                          controllers are handled
+ * @lock:                   Lock to be used by controller, Use mutex lock in presil mode,
+ *                          and spinlock in regular case
  */
 struct cam_irq_controller {
 	const char                     *name;
@@ -113,13 +115,84 @@ struct cam_irq_controller {
 	struct list_head                evt_handler_list_head;
 	struct list_head                th_list_head[CAM_IRQ_PRIORITY_MAX];
 	uint32_t                        hdl_idx;
-	spinlock_t                      lock;
 	struct cam_irq_th_payload       th_payload;
 	bool                            is_dependent;
 	struct cam_irq_controller      *dependent_controller[CAM_IRQ_MAX_DEPENDENTS];
 	bool                            delayed_global_clear;
+
+#ifdef CONFIG_CAM_PRESIL
+	struct mutex                    lock;
+#else
+	spinlock_t                      lock;
+#endif
 };
 
+#ifdef CONFIG_CAM_PRESIL
+static inline void cam_irq_controller_lock_init(struct cam_irq_controller *controller)
+{
+	mutex_init(&controller->lock);
+}
+
+static inline unsigned long cam_irq_controller_lock_irqsave(
+	struct cam_irq_controller *controller)
+{
+	mutex_lock(&controller->lock);
+
+	return 0;
+}
+
+static inline void cam_irq_controller_unlock_irqrestore(
+	struct cam_irq_controller *controller, unsigned long flags)
+{
+	mutex_unlock(&controller->lock);
+}
+
+static inline void cam_irq_controller_lock(struct cam_irq_controller *controller)
+{
+	mutex_lock(&controller->lock);
+}
+
+static inline void cam_irq_controller_unlock(struct cam_irq_controller *controller)
+{
+	mutex_unlock(&controller->lock);
+}
+#else
+static inline void cam_irq_controller_lock_init(struct cam_irq_controller *controller)
+{
+	spin_lock_init(&controller->lock);
+}
+
+static inline unsigned long cam_irq_controller_lock_irqsave(
+	struct cam_irq_controller *controller)
+{
+	unsigned long flags = 0;
+
+	if (!in_irq())
+		spin_lock_irqsave(&controller->lock, flags);
+
+	return flags;
+}
+
+static inline void cam_irq_controller_unlock_irqrestore(
+	struct cam_irq_controller *controller, unsigned long flags)
+{
+	if (!in_irq())
+		spin_unlock_irqrestore(&controller->lock, flags);
+}
+
+static inline void cam_irq_controller_lock(struct cam_irq_controller *controller)
+{
+	spin_lock(&controller->lock);
+}
+
+static inline void cam_irq_controller_unlock(struct cam_irq_controller *controller)
+{
+	spin_unlock(&controller->lock);
+}
+#endif
+
+
+
 int cam_irq_controller_unregister_dependent(void *primary_controller, void *secondary_controller)
 {
 	struct cam_irq_controller *ctrl_primary, *ctrl_secondary;
@@ -200,25 +273,6 @@ int cam_irq_controller_register_dependent(void *primary_controller, void *second
 	return 0;
 }
 
-static inline unsigned long cam_irq_controller_lock(
-	struct cam_irq_controller *controller)
-{
-	unsigned long flags = 0;
-
-	if (!in_irq())
-		spin_lock_irqsave(&controller->lock, flags);
-
-	return flags;
-}
-
-static inline void cam_irq_controller_unlock(
-	struct cam_irq_controller *controller,
-	unsigned long flags)
-{
-	if (!in_irq())
-		spin_unlock_irqrestore(&controller->lock, flags);
-}
-
 static inline void cam_irq_controller_clear_irq(
 	struct cam_irq_controller  *controller,
 	struct cam_irq_evt_handler *evt_handler)
@@ -358,7 +412,7 @@ int cam_irq_controller_init(const char       *name,
 	for (i = 0; i < CAM_IRQ_PRIORITY_MAX; i++)
 		INIT_LIST_HEAD(&controller->th_list_head[i]);
 
-	spin_lock_init(&controller->lock);
+	cam_irq_controller_lock_init(controller);
 
 	controller->hdl_idx = 1;
 	*irq_controller = controller;
@@ -506,7 +560,7 @@ int cam_irq_controller_subscribe_irq(void *irq_controller,
 	if (controller->hdl_idx > 0x3FFFFFFF)
 		controller->hdl_idx = 1;
 
-	flags = cam_irq_controller_lock(controller);
+	flags = cam_irq_controller_lock_irqsave(controller);
 
 	__cam_irq_controller_enable_irq(controller, evt_handler);
 
@@ -515,7 +569,7 @@ int cam_irq_controller_subscribe_irq(void *irq_controller,
 	list_add_tail(&evt_handler->th_list_node,
 		&controller->th_list_head[priority]);
 
-	cam_irq_controller_unlock(controller, flags);
+	cam_irq_controller_unlock_irqrestore(controller, flags);
 
 	return evt_handler->index;
 
@@ -554,7 +608,7 @@ int cam_irq_controller_enable_irq(void *irq_controller, uint32_t handle)
 	if (!controller)
 		return rc;
 
-	flags = cam_irq_controller_lock(controller);
+	flags = cam_irq_controller_lock_irqsave(controller);
 
 	rc = cam_irq_controller_find_event_handle(controller, handle,
 		&evt_handler);
@@ -565,7 +619,7 @@ int cam_irq_controller_enable_irq(void *irq_controller, uint32_t handle)
 	__cam_irq_controller_enable_irq(controller, evt_handler);
 
 end:
-	cam_irq_controller_unlock(controller, flags);
+	cam_irq_controller_unlock_irqrestore(controller, flags);
 
 	return rc;
 }
@@ -580,7 +634,7 @@ int cam_irq_controller_disable_irq(void *irq_controller, uint32_t handle)
 	if (!controller)
 		return rc;
 
-	flags = cam_irq_controller_lock(controller);
+	flags = cam_irq_controller_lock_irqsave(controller);
 
 	rc = cam_irq_controller_find_event_handle(controller, handle,
 		&evt_handler);
@@ -592,7 +646,7 @@ int cam_irq_controller_disable_irq(void *irq_controller, uint32_t handle)
 	cam_irq_controller_clear_irq(controller, evt_handler);
 
 end:
-	cam_irq_controller_unlock(controller, flags);
+	cam_irq_controller_unlock_irqrestore(controller, flags);
 
 	return rc;
 }
@@ -605,7 +659,7 @@ int cam_irq_controller_unsubscribe_irq(void *irq_controller,
 	unsigned long               flags = 0;
 	int                         rc = 0;
 
-	flags = cam_irq_controller_lock(controller);
+	flags = cam_irq_controller_lock_irqsave(controller);
 
 
 	rc = cam_irq_controller_find_event_handle(controller, handle,
@@ -623,7 +677,7 @@ int cam_irq_controller_unsubscribe_irq(void *irq_controller,
 	kfree(evt_handler);
 
 end:
-	cam_irq_controller_unlock(controller, flags);
+	cam_irq_controller_unlock_irqrestore(controller, flags);
 
 	return rc;
 }
@@ -824,9 +878,9 @@ static void cam_irq_controller_read_registers(struct cam_irq_controller *control
 			dep_controller = controller->dependent_controller[j];
 			CAM_DBG(CAM_IRQ_CTRL, "Reading dependent registers for %s",
 				dep_controller->name);
-			spin_lock(&dep_controller->lock);
+			cam_irq_controller_lock(dep_controller);
 			__cam_irq_controller_read_registers(dep_controller);
-			spin_unlock(&dep_controller->lock);
+			cam_irq_controller_unlock(dep_controller);
 		}
 	}
 
@@ -875,11 +929,14 @@ irqreturn_t cam_irq_controller_handle_irq(int irq_num, void *priv, int evt_grp)
 	CAM_DBG(CAM_IRQ_CTRL,
 		"Locking: %s IRQ Controller: [%pK], lock handle: %pK",
 		controller->name, controller, &controller->lock);
-	spin_lock(&controller->lock);
+	cam_irq_controller_lock(controller);
+
 	if (!controller->is_dependent)
 		cam_irq_controller_read_registers(controller);
+
 	cam_irq_controller_process_th(controller, evt_grp);
-	spin_unlock(&controller->lock);
+
+	cam_irq_controller_unlock(controller);
 	CAM_DBG(CAM_IRQ_CTRL,
 		"Unlocked: %s IRQ Controller: %pK, lock handle: %pK",
 		controller->name, controller, &controller->lock);
@@ -899,7 +956,7 @@ int cam_irq_controller_update_irq(void *irq_controller, uint32_t handle,
 	if (!controller)
 		return rc;
 
-	flags = cam_irq_controller_lock(controller);
+	flags = cam_irq_controller_lock_irqsave(controller);
 
 	rc = cam_irq_controller_find_event_handle(controller, handle,
 		&evt_handler);
@@ -918,7 +975,7 @@ int cam_irq_controller_update_irq(void *irq_controller, uint32_t handle,
 	cam_irq_controller_clear_irq(controller, evt_handler);
 
 end:
-	cam_irq_controller_unlock(controller, flags);
+	cam_irq_controller_unlock_irqrestore(controller, flags);
 
 	return rc;
 }

drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h

@@ -63,9 +63,19 @@ enum cam_isp_hw_event_type {
 	CAM_ISP_HW_EVENT_EPOCH,
 	CAM_ISP_HW_EVENT_EOF,
 	CAM_ISP_HW_EVENT_DONE,
+	CAM_ISP_HW_SECONDARY_EVENT,
 	CAM_ISP_HW_EVENT_MAX
 };
 
+/**
+ *  enum cam_isp_hw_secondary-event_type - Collection of the ISP hardware secondary events
+ */
+enum cam_isp_hw_secondary_event_type {
+	CAM_ISP_HW_SEC_EVENT_SOF,
+	CAM_ISP_HW_SEC_EVENT_EPOCH,
+	CAM_ISP_HW_SEC_EVENT_OUT_OF_SYNC_FRAME_DROP,
+	CAM_ISP_HW_SEC_EVENT_EVENT_MAX,
+};
 
 /**
  * enum cam_isp_hw_err_type - Collection of the ISP error types for
@@ -81,6 +91,7 @@ enum cam_isp_hw_err_type {
 	CAM_ISP_HW_ERROR_CSID_FIFO_OVERFLOW = 0x0040,
 	CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW = 0x0080,
 	CAM_ISP_HW_ERROR_CSID_FRAME_SIZE = 0x0100,
+	CAM_ISP_HW_ERROR_CSID_SENSOR_FRAME_DROP = 0x0200,
 };
 
 /**
@@ -96,12 +107,14 @@ enum cam_isp_hw_stop_cmd {
  * struct cam_isp_stop_args - hardware stop arguments
  *
  * @hw_stop_cmd:               Hardware stop command type information
- * @stop_only                  Send stop only to hw drivers. No Deinit to be
+ * @is_internal_stop:          Stop triggered internally for reset & recovery
+ * @stop_only:                 Send stop only to hw drivers. No Deinit to be
  *                             done.
  *
  */
 struct cam_isp_stop_args {
 	enum cam_isp_hw_stop_cmd      hw_stop_cmd;
+	bool                          is_internal_stop;
 	bool                          stop_only;
 };
 
@@ -193,6 +206,7 @@ struct cam_isp_bw_clk_config_info {
  * @reg_dump_buf_desc:     cmd buffer descriptors for reg dump
  * @num_reg_dump_buf:      Count of descriptors in reg_dump_buf_desc
  * @packet                 CSL packet from user mode driver
+ * @mup_val:               MUP value if configured
  * @mup_en                 Flag if dynamic sensor switch is enabled
  *
  */
@@ -206,7 +220,8 @@ struct cam_isp_prepare_hw_update_data {
 	struct cam_cmd_buf_desc               reg_dump_buf_desc[
 						CAM_REG_DUMP_MAX_BUF_ENTRIES];
 	uint32_t                              num_reg_dump_buf;
-	struct cam_packet                     *packet;
+	struct cam_packet                    *packet;
+	uint32_t                              mup_val;
 	bool                                  mup_en;
 };
 
@@ -214,13 +229,11 @@ struct cam_isp_prepare_hw_update_data {
 /**
  * struct cam_isp_hw_sof_event_data - Event payload for CAM_HW_EVENT_SOF
  *
- * @is_secondary_event: Event notified as secondary
  * @timestamp         : Time stamp for the sof event
  * @boot_time         : Boot time stamp for the sof event
  *
  */
 struct cam_isp_hw_sof_event_data {
-	bool           is_secondary_evt;
 	uint64_t       timestamp;
 	uint64_t       boot_time;
 };
@@ -293,6 +306,16 @@ struct cam_isp_hw_error_event_data {
 	bool                 enable_req_dump;
 };
 
+/**
+ * struct cam_isp_hw_secondary_event_data - Event payload for secondary events
+ *
+ * @evt_type     : Event notified as secondary
+ *
+ */
+struct cam_isp_hw_secondary_event_data {
+	enum cam_isp_hw_secondary_event_type  evt_type;
+};
+
 /* enum cam_isp_hw_mgr_command - Hardware manager command type */
 enum cam_isp_hw_mgr_command {
 	CAM_ISP_HW_MGR_CMD_IS_RDI_ONLY_CONTEXT,
@@ -338,15 +361,29 @@ struct cam_isp_hw_cmd_args {
  * struct cam_isp_start_args - isp hardware start arguments
  *
  * @config_args:               Hardware configuration commands.
+ * @is_internal_start:         Start triggered internally for reset & recovery
  * @start_only                 Send start only to hw drivers. No init to
  *                             be done.
  *
  */
 struct cam_isp_start_args {
 	struct cam_hw_config_args hw_config;
+	bool                      is_internal_start;
 	bool                      start_only;
 };
 
+/**
+ * struct cam_isp_lcr_rdi_cfg_args - isp hardware start arguments
+ *
+ * @rdi_lcr_cfg:            RDI LCR cfg received from User space.
+ * @is_init:                Flag to indicate if init packet.
+ *
+ */
+struct cam_isp_lcr_rdi_cfg_args {
+	struct cam_isp_lcr_rdi_config *rdi_lcr_cfg;
+	bool                           is_init;
+};
+
 /**
  * cam_isp_hw_mgr_init()
  *

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid570.h

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _CAM_IFE_CSID_570_H_
+#define _CAM_IFE_CSID_570_H_
+
+#include <linux/module.h>
+#include "camera_main.h"
+#include "cam_ife_csid_dev.h"
+#include "cam_ife_csid_common.h"
+#include "cam_ife_csid_hw_ver1.h"
+
+/* Settings for 570 CSID are leveraged from 480 */
+static struct cam_ife_csid_ver1_reg_info cam_ife_csid_570_reg_info = {
+	.cmn_reg          = &cam_ife_csid_480_cmn_reg_info,
+	.csi2_reg         = &cam_ife_csid_480_csi2_reg_info,
+	.ipp_reg          = &cam_ife_csid_480_ipp_reg_info,
+	.ppp_reg          = &cam_ife_csid_480_ppp_reg_info,
+	.rdi_reg = {
+		&cam_ife_csid_480_rdi_0_reg_info,
+		&cam_ife_csid_480_rdi_1_reg_info,
+		&cam_ife_csid_480_rdi_2_reg_info,
+		NULL,
+		},
+	.tpg_reg = &cam_ife_csid_480_tpg_reg_info,
+	.width_fuse_max_val = 3,
+	.fused_max_width = {5612, 6048, 7308, UINT_MAX},
+};
+#endif /*_CAM_IFE_CSID_570_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid680.h

@@ -1141,7 +1141,7 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.timestamp_strobe_val                    = 0x2,
 	.rst_location_shift_val                  = 4,
 	.rst_mode_shift_val                      = 0,
-	.epoch_div_factor                        = 4,
+	.epoch_div_factor                        = 2,
 	.global_reset                            = 1,
 	.rup_supported                           = 1,
 	.only_master_rup                         = 1,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid780.h

@@ -420,10 +420,12 @@ static struct cam_ife_csid_ver2_path_reg_info
 		/* configurations */
 		.resume_frame_boundary            = 1,
 		.binning_supported                = 0x7,
+		.capabilities                     = CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
 		.start_mode_internal              = 0x0,
 		.start_mode_global                = 0x1,
 		.start_mode_master                = 0x2,
 		.start_mode_slave                 = 0x3,
+		.sof_retiming_dis_shift           = 5,
 		.start_mode_shift                 = 2,
 		.start_master_sel_val             = 0,
 		.start_master_sel_shift           = 4,
@@ -525,6 +527,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch0_cfg_batch_id5_addr        = 0xBF4,
 		.epoch1_cfg_batch_id5_addr        = 0xBF8,
 		/* configurations */
+		.capabilities                     = CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
 		.resume_frame_boundary            = 1,
 		.start_mode_shift                 = 2,
 		.start_mode_internal              = 0x0,
@@ -554,6 +557,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.top_irq_mask                     = 0x10,
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
+		.sof_retiming_dis_shift           = 5,
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -625,6 +629,12 @@ static struct cam_ife_csid_ver2_path_reg_info
 		/* configurations */
 		.resume_frame_boundary            = 1,
 		.overflow_ctrl_en                 = 1,
+		.capabilities                     = CAM_IFE_CSID_CAP_INPUT_LCR |
+							CAM_IFE_CSID_CAP_MIPI10_UNPACK |
+							CAM_IFE_CSID_CAP_MIPI12_UNPACK |
+							CAM_IFE_CSID_CAP_MIPI14_UNPACK |
+							CAM_IFE_CSID_CAP_LINE_SMOOTHING_IN_RDI |
+							CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
 		.overflow_ctrl_mode_val           = 0x8,
 		.offline_mode_supported           = 1,
 		.mipi_pack_supported              = 1,
@@ -648,6 +658,8 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.top_irq_mask                     = 0x100,
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
+		.pix_store_en_shift_val           = 10,
+		.sof_retiming_dis_shift           = 5,
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -719,6 +731,12 @@ static struct cam_ife_csid_ver2_path_reg_info
 		/* configurations */
 		.resume_frame_boundary            = 1,
 		.overflow_ctrl_en                 = 1,
+		.capabilities                     = CAM_IFE_CSID_CAP_INPUT_LCR |
+							CAM_IFE_CSID_CAP_MIPI10_UNPACK |
+							CAM_IFE_CSID_CAP_MIPI12_UNPACK |
+							CAM_IFE_CSID_CAP_MIPI14_UNPACK |
+							CAM_IFE_CSID_CAP_LINE_SMOOTHING_IN_RDI |
+							CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
 		.overflow_ctrl_mode_val           = 0x8,
 		.mipi_pack_supported              = 1,
 		.offline_mode_supported           = 1,
@@ -742,6 +760,8 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.top_irq_mask                     = 0x200,
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
+		.pix_store_en_shift_val           = 10,
+		.sof_retiming_dis_shift           = 5,
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -813,6 +833,12 @@ static struct cam_ife_csid_ver2_path_reg_info
 		/* configurations */
 		.resume_frame_boundary            = 1,
 		.overflow_ctrl_en                 = 1,
+		.capabilities                     = CAM_IFE_CSID_CAP_INPUT_LCR |
+							CAM_IFE_CSID_CAP_MIPI10_UNPACK |
+							CAM_IFE_CSID_CAP_MIPI12_UNPACK |
+							CAM_IFE_CSID_CAP_MIPI14_UNPACK |
+							CAM_IFE_CSID_CAP_LINE_SMOOTHING_IN_RDI |
+							CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
 		.overflow_ctrl_mode_val           = 0x8,
 		.mipi_pack_supported              = 1,
 		.offline_mode_supported           = 1,
@@ -836,6 +862,8 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.top_irq_mask                     = 0x400,
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
+		.pix_store_en_shift_val           = 10,
+		.sof_retiming_dis_shift           = 5,
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -905,8 +933,10 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch0_cfg_batch_id5_addr        = 0x8EC,
 		.epoch1_cfg_batch_id5_addr        = 0x8F0,
 		/* configurations */
+		.capabilities                     = CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
 		.resume_frame_boundary            = 1,
 		.overflow_ctrl_en                 = 1,
+		.capabilities                     = 0,
 		.overflow_ctrl_mode_val           = 0x8,
 		.offline_mode_supported           = 1,
 		.mipi_pack_supported              = 1,
@@ -930,6 +960,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.top_irq_mask                     = 0x800,
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
+		.sof_retiming_dis_shift           = 5,
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -999,8 +1030,10 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch0_cfg_batch_id5_addr       = 0x9EC,
 		.epoch1_cfg_batch_id5_addr       = 0x9F0,
 		/* configurations */
+		.capabilities                    = CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
 		.resume_frame_boundary           = 1,
 		.overflow_ctrl_en                = 1,
+		.capabilities                    = 0,
 		.overflow_ctrl_mode_val          = 0x8,
 		.offline_mode_supported          = 1,
 		.mipi_pack_supported             = 1,
@@ -1022,8 +1055,9 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.camif_irq_mask                  = 0x800000,
 		.rup_aup_mask                    = 0x1000100,
 		.top_irq_mask                    = 0x1000,
-		.epoch0_shift_val                 = 16,
-		.epoch1_shift_val                 = 0,
+		.epoch0_shift_val                = 16,
+		.epoch1_shift_val                = 0,
+		.sof_retiming_dis_shift          = 5,
 };
 
 static struct cam_ife_csid_csi2_rx_reg_info
@@ -1142,6 +1176,7 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.timestamp_stb_sel_shift_val             = 8,
 	.vfr_en_shift_val                        = 0,
 	.mup_shift_val                           = 28,
+	.shdr_slave_ppp_shift                    = 20,
 	.shdr_slave_rdi2_shift                   = 22,
 	.shdr_slave_rdi1_shift                   = 21,
 	.shdr_master_rdi0_shift                  = 5,
@@ -1203,6 +1238,7 @@ static struct cam_ife_csid_ver2_top_reg_info
 	.dual_sync_sel_shift_val        = 8,
 	.dual_en_shift_val              = 0,
 	.master_slave_sel_shift_val     = 1,
+	.rdi_lcr_shift_val              = 16,
 	.master_sel_val                 = 0,
 	.slave_sel_val                  = 1,
 	.io_path_cfg_rst_val            = 1,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.c

@@ -86,6 +86,8 @@ int cam_ife_csid_is_pix_res_format_supported(
 	case CAM_FORMAT_DPCM_14_8_14:
 	case CAM_FORMAT_DPCM_14_10_14:
 	case CAM_FORMAT_DPCM_12_10_12:
+	case CAM_FORMAT_YUV422:
+	case CAM_FORMAT_YUV422_10:
 		rc = 0;
 		break;
 	default:
@@ -96,7 +98,8 @@ int cam_ife_csid_is_pix_res_format_supported(
 
 int cam_ife_csid_get_format_rdi(
 	uint32_t in_format, uint32_t out_format,
-	struct cam_ife_csid_path_format *path_format, bool rpp)
+	struct cam_ife_csid_path_format *path_format, bool rpp,
+	bool mipi_unpacked)
 {
 	int rc = 0;
 
@@ -109,10 +112,17 @@ int cam_ife_csid_get_format_rdi(
 				path_format->decode_fmt = 0x0;
 				path_format->packing_fmt = 0x1;
 			}
+
+			if (mipi_unpacked) {
+				path_format->decode_fmt = 0x0;
+				path_format->packing_fmt = 0x0;
+				path_format->plain_fmt = 0x0;
+			}
 			break;
 		case CAM_FORMAT_PLAIN8:
 			path_format->decode_fmt = 0x0;
 			path_format->plain_fmt = 0x0;
+			path_format->packing_fmt = 0;
 			break;
 		default:
 			rc = -EINVAL;
@@ -129,9 +139,16 @@ int cam_ife_csid_get_format_rdi(
 				path_format->decode_fmt = 0x1;
 				path_format->packing_fmt = 0x1;
 			}
+
+			if (mipi_unpacked) {
+				path_format->decode_fmt = 0x1;
+				path_format->packing_fmt = 0x0;
+				path_format->plain_fmt = 0x0;
+			}
 			break;
 		case CAM_FORMAT_PLAIN8:
 			path_format->decode_fmt = 0x1;
+			path_format->packing_fmt = 0;
 			path_format->plain_fmt = 0x0;
 			break;
 		default:
@@ -149,10 +166,17 @@ int cam_ife_csid_get_format_rdi(
 				path_format->decode_fmt = 0x2;
 				path_format->packing_fmt = 0x1;
 			}
+
+			if (mipi_unpacked) {
+				path_format->decode_fmt = 0x2;
+				path_format->packing_fmt = 0x0;
+				path_format->plain_fmt = 0x1;
+			}
 			break;
 		case CAM_FORMAT_PLAIN16_10:
 			path_format->decode_fmt = 0x2;
 			path_format->plain_fmt = 0x1;
+			path_format->packing_fmt = 0;
 			break;
 		default:
 			rc = -EINVAL;
@@ -168,10 +192,17 @@ int cam_ife_csid_get_format_rdi(
 				path_format->decode_fmt = 0x3;
 				path_format->packing_fmt = 0x1;
 			}
+
+			if (mipi_unpacked) {
+				path_format->decode_fmt = 0x3;
+				path_format->packing_fmt = 0x0;
+				path_format->plain_fmt = 0x1;
+			}
 			break;
 		case CAM_FORMAT_PLAIN16_12:
 			path_format->decode_fmt = 0x3;
 			path_format->plain_fmt = 0x1;
+			path_format->packing_fmt = 0;
 			break;
 		default:
 			rc = -EINVAL;
@@ -187,10 +218,17 @@ int cam_ife_csid_get_format_rdi(
 				path_format->decode_fmt = 0x4;
 				path_format->packing_fmt = 0x1;
 			}
+
+			if (mipi_unpacked) {
+				path_format->decode_fmt = 0x4;
+				path_format->packing_fmt = 0x0;
+				path_format->plain_fmt = 0x1;
+			}
 			break;
 		case CAM_FORMAT_PLAIN16_14:
 			path_format->decode_fmt = 0x4;
 			path_format->plain_fmt = 0x1;
+			path_format->packing_fmt = 0;
 			break;
 		default:
 			rc = -EINVAL;
@@ -206,10 +244,17 @@ int cam_ife_csid_get_format_rdi(
 				path_format->decode_fmt = 0x5;
 				path_format->packing_fmt = 0x1;
 			}
+
+			if (mipi_unpacked) {
+				path_format->decode_fmt = 0x5;
+				path_format->packing_fmt = 0x0;
+				path_format->plain_fmt = 0x1;
+			}
 			break;
 		case CAM_FORMAT_PLAIN16_16:
 			path_format->decode_fmt = 0x5;
 			path_format->plain_fmt = 0x1;
+			path_format->packing_fmt = 0;
 			break;
 		default:
 			rc = -EINVAL;
@@ -225,10 +270,17 @@ int cam_ife_csid_get_format_rdi(
 				path_format->decode_fmt = 0x6;
 				path_format->packing_fmt = 0x1;
 			}
+
+			if (mipi_unpacked) {
+				path_format->decode_fmt = 0x6;
+				path_format->packing_fmt = 0x0;
+				path_format->plain_fmt = 0x2;
+			}
 			break;
 		case CAM_FORMAT_PLAIN32_20:
 			path_format->decode_fmt = 0x6;
 			path_format->plain_fmt = 0x2;
+			path_format->packing_fmt = 0;
 			break;
 		default:
 			rc = -EINVAL;
@@ -239,30 +291,37 @@ int cam_ife_csid_get_format_rdi(
 	case CAM_FORMAT_DPCM_10_6_10:
 		path_format->decode_fmt  = 0x7;
 		path_format->plain_fmt = 0x1;
+		path_format->packing_fmt = 0;
 		break;
 	case CAM_FORMAT_DPCM_10_8_10:
 		path_format->decode_fmt  = 0x8;
 		path_format->plain_fmt = 0x1;
+		path_format->packing_fmt = 0;
 		break;
 	case CAM_FORMAT_DPCM_12_6_12:
 		path_format->decode_fmt  = 0x9;
 		path_format->plain_fmt = 0x1;
+		path_format->packing_fmt = 0;
 		break;
 	case CAM_FORMAT_DPCM_12_8_12:
 		path_format->decode_fmt  = 0xA;
 		path_format->plain_fmt = 0x1;
+		path_format->packing_fmt = 0;
 		break;
 	case CAM_FORMAT_DPCM_14_8_14:
 		path_format->decode_fmt  = 0xB;
 		path_format->plain_fmt = 0x1;
+		path_format->packing_fmt = 0;
 		break;
 	case CAM_FORMAT_DPCM_14_10_14:
 		path_format->decode_fmt  = 0xC;
 		path_format->plain_fmt = 0x1;
+		path_format->packing_fmt = 0;
 		break;
 	case CAM_FORMAT_DPCM_12_10_12:
 		path_format->decode_fmt  = 0xD;
 		path_format->plain_fmt = 0x1;
+		path_format->packing_fmt = 0;
 		break;
 	case CAM_FORMAT_YUV422:
 		path_format->decode_fmt  = 0x1;
@@ -625,6 +684,7 @@ int cam_ife_csid_get_base(struct cam_hw_soc_info *soc_info,
 	struct cam_cdm_utils_ops         *cdm_util_ops = NULL;
 	size_t                           size = 0;
 	uint32_t                          mem_base = 0;
+	struct cam_csid_soc_private      *soc_private;
 
 
 	if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) {
@@ -632,11 +692,17 @@ int cam_ife_csid_get_base(struct cam_hw_soc_info *soc_info,
 		return -EINVAL;
 	}
 
-	if (!cdm_args || !cdm_args->res) {
+	if (!cdm_args || !cdm_args->res || !soc_info) {
 		CAM_ERR(CAM_ISP, "Error, Invalid args");
 		return -EINVAL;
 	}
 
+	soc_private = soc_info->soc_private;
+	if (!soc_private) {
+		CAM_ERR(CAM_ISP, "soc_private is null");
+		return -EINVAL;
+	}
+
 	cdm_util_ops =
 		(struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops;
 
@@ -654,14 +720,19 @@ int cam_ife_csid_get_base(struct cam_hw_soc_info *soc_info,
 	}
 
 	mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE(soc_info, base_id);
-	if (cdm_args->cdm_id == CAM_CDM_RT)
-		mem_base -= CAM_SOC_GET_REG_MAP_CAM_BASE(soc_info, RT_BASE_IDX);
+	if (cdm_args->cdm_id == CAM_CDM_RT) {
+		if (!soc_private->rt_wrapper_base) {
+			CAM_ERR(CAM_ISP, "rt_wrapper_base_addr is null");
+			return -EINVAL;
+		}
+
+		mem_base -= soc_private->rt_wrapper_base;
+	}
 
 	CAM_DBG(CAM_ISP, "core %d mem_base 0x%x, cdm_id:%u",
 		soc_info->index, mem_base, cdm_args->cdm_id);
 
-	cdm_util_ops->cdm_write_changebase(
-	cdm_args->cmd.cmd_buf_addr, mem_base);
+	cdm_util_ops->cdm_write_changebase(cdm_args->cmd.cmd_buf_addr, mem_base);
 	cdm_args->cmd.used_bytes = (size * 4);
 
 	return 0;

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.h

@@ -33,6 +33,16 @@
 
 #define CAM_IFE_CSID_LOG_BUF_LEN                          512
 
+#define CAM_IFE_CSID_CAP_INPUT_LCR                        0x1
+#define CAM_IFE_CSID_CAP_MIPI8_UNPACK                     0x2
+#define CAM_IFE_CSID_CAP_MIPI10_UNPACK                    0x4
+#define CAM_IFE_CSID_CAP_MIPI12_UNPACK                    0x8
+#define CAM_IFE_CSID_CAP_MIPI14_UNPACK                    0x10
+#define CAM_IFE_CSID_CAP_MIPI16_UNPACK                    0x20
+#define CAM_IFE_CSID_CAP_MIPI20_UNPACK                    0x40
+#define CAM_IFE_CSID_CAP_LINE_SMOOTHING_IN_RDI            0x80
+#define CAM_IFE_CSID_CAP_SOF_RETIME_DIS                   0x100
+
 /*
  * Debug values enable the corresponding interrupts and debug logs provide
  * necessary information
@@ -281,9 +291,10 @@ struct cam_ife_csid_debug_info {
  * @fatal_err_detected:     flag to indicate if fatal err detected
  * @rx_enabled:             flag to indicate if rx is enabled
  * @tpg_configured:         flag to indicate if internal_tpg is configured
- * @sfe_inline_shdr:        flag to indicate if sfe is inline shdr
  * @reset_awaited:          flag to indicate if reset is awaited
  * @offline_mode:           flag to indicate if csid in offline mode
+ * @rdi_lcr_en:             flag to indicate if RDI to lcr is enabled
+ * @sfe_en:                 flag to indicate if SFE is enabled
  */
 struct cam_ife_csid_hw_flags {
 	bool                  device_enabled;
@@ -294,13 +305,14 @@ struct cam_ife_csid_hw_flags {
 	bool                  rx_enabled;
 	bool                  tpg_enabled;
 	bool                  tpg_configured;
-	bool                  sfe_inline_shdr;
 	bool                  reset_awaited;
 	bool                  offline_mode;
+	bool                  rdi_lcr_en;
+	bool                  sfe_en;
 };
 
 /*
- * struct cam_ife_csid_hw_flags: place holder for flags
+ * struct am_ife_csid_cid_data: place holder for cid data
  *
  * @vc_dt:        vc_dt structure
  * @cid_cnt:      count of cid acquired
@@ -313,7 +325,7 @@ struct cam_ife_csid_cid_data {
 };
 
 /*
- * struct cam_ife_csid_hw_flags: place holder for flags
+ * struct cam_ife_csid_rx_cfg: place holder for rx cfg
  *
  * @phy_sel:                  Selected phy
  * @lane_type:                type of lane selected
@@ -346,7 +358,8 @@ int cam_ife_csid_is_pix_res_format_supported(
 
 int cam_ife_csid_get_format_rdi(
 	uint32_t in_format, uint32_t out_format,
-	struct cam_ife_csid_path_format *path_format, bool rpp);
+	struct cam_ife_csid_path_format *path_format, bool rpp,
+	bool mipi_unpacked);
 
 int cam_ife_csid_get_format_ipp_ppp(
 	uint32_t in_format,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.c

@@ -2172,7 +2172,7 @@ static int cam_ife_csid_ver1_init_config_rdi_path(
 	mem_base = soc_info->reg_map[0].mem_base;
 	is_rpp = path_cfg->crop_enable || path_cfg->drop_enable;
 	rc = cam_ife_csid_get_format_rdi(path_cfg->in_format,
-		path_cfg->out_format, &path_format, is_rpp);
+		path_cfg->out_format, &path_format, is_rpp, false);
 	if (rc)
 		return rc;
 
@@ -2330,7 +2330,7 @@ static int cam_ife_csid_ver1_init_config_udi_path(
 	mem_base = soc_info->reg_map[0].mem_base;
 	is_rpp = path_cfg->crop_enable || path_cfg->drop_enable;
 	rc = cam_ife_csid_get_format_rdi(path_cfg->in_format,
-		path_cfg->out_format, &path_format, is_rpp);
+		path_cfg->out_format, &path_format, is_rpp, false);
 	if (rc)
 		return rc;
 
@@ -3017,6 +3017,8 @@ int cam_ife_csid_ver1_start(void *hw_priv, void *args,
 		CAM_ERR(CAM_ISP, "CSID:%d start fail res type:%d res id:%d",
 			csid_hw->hw_intf->hw_idx, res->res_type,
 			res->res_id);
+	if (!rc)
+		csid_hw->flags.reset_awaited = false;
 end:
 	return rc;
 }
@@ -3275,6 +3277,7 @@ static int cam_ife_csid_ver1_sof_irq_debug(
 	bool sof_irq_enable = false;
 	struct cam_hw_soc_info                  *soc_info;
 	struct cam_ife_csid_ver1_reg_info *csid_reg;
+	uint32_t data_idx;
 
 	if (*((uint32_t *)cmd_args) == 1)
 		sof_irq_enable = true;
@@ -3287,6 +3290,7 @@ static int cam_ife_csid_ver1_sof_irq_debug(
 		return 0;
 	}
 
+	data_idx = csid_hw->rx_cfg.phy_sel;
 	soc_info = &csid_hw->hw_info->soc_info;
 	csid_reg = (struct cam_ife_csid_ver1_reg_info *)
 			csid_hw->core_info->csid_reg;
@@ -3353,7 +3357,7 @@ static int cam_ife_csid_ver1_sof_irq_debug(
 
 	cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE,
 			CAM_SUBDEV_MESSAGE_IRQ_ERR,
-			(csid_hw->rx_cfg.phy_sel));
+			(void *)&data_idx);
 
 	return 0;
 }
@@ -3875,12 +3879,14 @@ static int cam_ife_csid_ver1_handle_event_err(
 	struct cam_ife_csid_ver1_evt_payload *evt_payload,
 	uint32_t err_type)
 {
+	struct cam_isp_hw_error_event_info err_evt_info;
 	struct cam_isp_hw_event_info event_info = {0};
 	int rc = 0;
 
 	event_info.hw_idx = evt_payload->hw_idx;
-	event_info.err_type = err_type;
+	err_evt_info.err_type = err_type;
 	event_info.hw_type = CAM_ISP_HW_TYPE_CSID;
+	event_info.event_data = (void *)&err_evt_info;
 
 	CAM_DBG(CAM_ISP, "CSID[%d] Error type %d",
 		csid_hw->hw_intf->hw_idx, err_type);
@@ -3948,6 +3954,7 @@ static int cam_ife_csid_ver1_rx_bottom_half_handler(
 	uint32_t                                    event_type = 0;
 	size_t                                      len = 0;
 	struct cam_hw_soc_info                     *soc_info;
+	uint32_t                                    data_idx;
 
 	if (!csid_hw || !evt_payload) {
 		CAM_ERR(CAM_ISP,
@@ -3956,6 +3963,7 @@ static int cam_ife_csid_ver1_rx_bottom_half_handler(
 		return -EINVAL;
 	}
 
+	data_idx = csid_hw->rx_cfg.phy_sel;
 	soc_info = &csid_hw->hw_info->soc_info;
 	csid_reg = (struct cam_ife_csid_ver1_reg_info *)
 			csid_hw->core_info->csid_reg;
@@ -4063,15 +4071,20 @@ static int cam_ife_csid_ver1_rx_bottom_half_handler(
 		CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID[%u] %s",
 			csid_hw->hw_intf->hw_idx, log_buf);
 
-	if (csid_hw->flags.fatal_err_detected) {
-		event_type |= CAM_ISP_HW_ERROR_CSID_FATAL;
-		cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE,
-				CAM_SUBDEV_MESSAGE_IRQ_ERR,
-				(csid_hw->rx_cfg.phy_sel));
+	if (!csid_hw->flags.reset_awaited) {
+		if (csid_hw->flags.fatal_err_detected) {
+			event_type |= CAM_ISP_HW_ERROR_CSID_FATAL;
+			cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE,
+					CAM_SUBDEV_MESSAGE_IRQ_ERR,
+					(void *)&data_idx);
+		}
+
+		if (event_type) {
+			cam_ife_csid_ver1_handle_event_err(csid_hw,
+				evt_payload, event_type);
+			csid_hw->flags.reset_awaited = true;
+		}
 	}
-	if (event_type)
-		cam_ife_csid_ver1_handle_event_err(csid_hw,
-			evt_payload, event_type);
 
 	return IRQ_HANDLED;
 }

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c

@@ -55,6 +55,28 @@ static void cam_ife_csid_ver2_print_debug_reg_status(
 	struct cam_ife_csid_ver2_hw *csid_hw,
 	struct cam_isp_resource_node    *res);
 
+static bool cam_ife_csid_ver2_disable_sof_retime(
+	struct cam_ife_csid_ver2_hw     *csid_hw,
+	struct cam_isp_resource_node    *res)
+{
+	struct cam_ife_csid_ver2_reg_info  *csid_reg = (struct cam_ife_csid_ver2_reg_info *)
+							    csid_hw->core_info->csid_reg;
+	struct cam_ife_csid_ver2_path_cfg  *path_cfg = (struct cam_ife_csid_ver2_path_cfg *)
+							    res->res_priv;
+	const struct cam_ife_csid_ver2_path_reg_info *path_reg = csid_reg->path_reg[res->res_id];
+
+	if (!(path_reg->capabilities & CAM_IFE_CSID_CAP_SOF_RETIME_DIS))
+		return false;
+
+	if (path_cfg->sfe_shdr || path_cfg->lcr_en)
+		return true;
+
+	if (csid_hw->flags.rdi_lcr_en && res->res_id == CAM_IFE_PIX_PATH_RES_PPP)
+		return true;
+
+	return false;
+}
+
 static int cam_ife_csid_ver2_set_debug(
 	struct cam_ife_csid_ver2_hw *csid_hw,
 	uint32_t debug_val)
@@ -134,6 +156,7 @@ static int cam_ife_csid_ver2_sof_irq_debug(
 	struct   cam_ife_csid_ver2_path_cfg    *path_cfg;
 	struct   cam_isp_resource_node         *res;
 	uint32_t irq_mask[CAM_IFE_CSID_IRQ_REG_MAX] = {0};
+	uint32_t data_idx;
 
 	if (*((uint32_t *)cmd_args) == 1)
 		sof_irq_enable = true;
@@ -147,6 +170,7 @@ static int cam_ife_csid_ver2_sof_irq_debug(
 		return 0;
 	}
 
+	data_idx = csid_hw->rx_cfg.phy_sel - 1;
 	csid_reg = (struct cam_ife_csid_ver2_reg_info *)
 			csid_hw->core_info->csid_reg;
 
@@ -185,8 +209,7 @@ static int cam_ife_csid_ver2_sof_irq_debug(
 			csid_hw->rx_cfg.phy_sel - 1);
 
 	cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE,
-			CAM_SUBDEV_MESSAGE_IRQ_ERR,
-			(csid_hw->rx_cfg.phy_sel - 1));
+			CAM_SUBDEV_MESSAGE_IRQ_ERR, (void *)&data_idx);
 
 	return 0;
 }
@@ -897,10 +920,12 @@ static int cam_ife_csid_ver2_handle_event_err(
 	struct cam_ife_csid_ver2_hw  *csid_hw,
 	uint32_t                      irq_status,
 	uint32_t                      err_type,
+	bool                          is_secondary,
 	struct cam_isp_resource_node *res)
 {
-	struct cam_isp_hw_event_info            evt = {0};
-	struct cam_ife_csid_ver2_path_cfg      *path_cfg;
+	struct cam_isp_hw_error_event_info   err_evt_info;
+	struct cam_isp_hw_event_info         evt = {0};
+	struct cam_ife_csid_ver2_path_cfg   *path_cfg;
 
 	if (!csid_hw->event_cb) {
 		CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID[%u] event cb not registered",
@@ -911,24 +936,29 @@ static int cam_ife_csid_ver2_handle_event_err(
 	evt.hw_idx   = csid_hw->hw_intf->hw_idx;
 	evt.reg_val  = irq_status;
 	evt.hw_type  = CAM_ISP_HW_TYPE_CSID;
-	evt.err_type = err_type;
+	evt.is_secondary_evt = is_secondary;
+	err_evt_info.err_type = err_type;
+	evt.event_data = (void *)&err_evt_info;
 
-	if (res) {
-		cam_ife_csid_ver2_print_debug_reg_status(csid_hw, res);
-		path_cfg = (struct cam_ife_csid_ver2_path_cfg *)res->res_priv;
-		evt.res_id   = res->res_id;
-		CAM_ERR_RATE_LIMIT(CAM_ISP,
-			"csid[%u] Res:%s Err 0x%x status 0x%x time_stamp: %lld:%lld",
-			csid_hw->hw_intf->hw_idx, res->res_name, err_type,
-			irq_status, path_cfg->error_ts.tv_sec,
-			path_cfg->error_ts.tv_nsec);
-	} else {
-		CAM_ERR_RATE_LIMIT(CAM_ISP,
-			"csid[%u] Rx Err: 0x%x status 0x%x",
-			csid_hw->hw_intf->hw_idx, err_type, irq_status);
+	if (!is_secondary) {
+		if (res) {
+			cam_ife_csid_ver2_print_debug_reg_status(csid_hw, res);
+			path_cfg = (struct cam_ife_csid_ver2_path_cfg *)res->res_priv;
+			evt.res_id   = res->res_id;
+			CAM_ERR_RATE_LIMIT(CAM_ISP,
+				"csid[%u] Res:%s Err 0x%x status 0x%x time_stamp: %lld:%lld",
+				csid_hw->hw_intf->hw_idx, res->res_name, err_type,
+				irq_status, path_cfg->error_ts.tv_sec,
+				path_cfg->error_ts.tv_nsec);
+		} else {
+			CAM_ERR_RATE_LIMIT(CAM_ISP,
+				"csid[%u] Rx Err: 0x%x status 0x%x",
+				csid_hw->hw_intf->hw_idx, err_type, irq_status);
+		}
 	}
 
-	evt.in_core_idx = cam_ife_csid_ver2_input_core_to_hw_idx(csid_hw->top_cfg.input_core_type);
+	evt.in_core_idx =
+		cam_ife_csid_ver2_input_core_to_hw_idx(csid_hw->top_cfg.input_core_type);
 
 	csid_hw->event_cb(csid_hw->token, CAM_ISP_HW_EVENT_ERROR, (void *)&evt);
 
@@ -952,6 +982,7 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
 	uint32_t                                    event_type = 0;
 	uint32_t                                    long_pkt_ftr_val;
 	uint32_t                                    total_crc;
+	uint32_t                                    data_idx;
 
 	if (!handler_priv || !evt_payload_priv) {
 		CAM_ERR(CAM_ISP, "Invalid params");
@@ -961,6 +992,7 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
 	payload = evt_payload_priv;
 	csid_hw = handler_priv;
 	soc_info = &csid_hw->hw_info->soc_info;
+	data_idx = csid_hw->rx_cfg.phy_sel -1;
 
 	log_buf = csid_hw->log_buf;
 	memset(log_buf, 0, sizeof(csid_hw->log_buf));
@@ -1103,16 +1135,20 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
 		csid_hw->hw_intf->hw_idx,
 		payload->irq_reg_val[CAM_IFE_CSID_IRQ_REG_RX]);
 
-	if (csid_hw->flags.fatal_err_detected) {
-		event_type |= CAM_ISP_HW_ERROR_CSID_FATAL;
-		cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE,
-			CAM_SUBDEV_MESSAGE_IRQ_ERR,
-			(csid_hw->rx_cfg.phy_sel -1));
-	}
+	if (!csid_hw->flags.reset_awaited) {
+		if (csid_hw->flags.fatal_err_detected) {
+			event_type |= CAM_ISP_HW_ERROR_CSID_FATAL;
 
-	if (event_type)
-		cam_ife_csid_ver2_handle_event_err(csid_hw,
-			rx_irq_status, event_type, NULL);
+			cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE,
+				CAM_SUBDEV_MESSAGE_IRQ_ERR, (void *)&data_idx);
+		}
+
+		if (event_type) {
+			cam_ife_csid_ver2_handle_event_err(csid_hw,
+				rx_irq_status, event_type, false, NULL);
+			csid_hw->flags.reset_awaited = true;
+		}
+	}
 unlock:
 	spin_unlock(&csid_hw->lock_state);
 end:
@@ -1349,7 +1385,7 @@ static int cam_ife_csid_ver2_top_err_irq_bottom_half(
 
 	if (event_type)
 		cam_ife_csid_ver2_handle_event_err(csid_hw,
-			irq_status, event_type, NULL);
+			irq_status, event_type, false, NULL);
 
 	cam_ife_csid_ver2_put_evt_payload(csid_hw, &payload,
 		&csid_hw->path_free_payload_list,
@@ -1429,10 +1465,11 @@ static int cam_ife_csid_ver2_ipp_bottom_half(
 		goto end;
 	}
 
+	evt_info.hw_type  = CAM_ISP_HW_TYPE_CSID;
 	evt_info.hw_idx   = csid_hw->hw_intf->hw_idx;
 	evt_info.res_id   = CAM_IFE_PIX_PATH_RES_IPP;
 	evt_info.res_type = CAM_ISP_RESOURCE_PIX_PATH;
-	evt_info.reg_val = irq_status_ipp;
+	evt_info.reg_val  = irq_status_ipp;
 
 	if (irq_status_ipp & IFE_CSID_VER2_PATH_CAMIF_EOF) {
 		if (csid_hw->event_cb)
@@ -1501,6 +1538,7 @@ static int cam_ife_csid_ver2_ipp_bottom_half(
 		cam_ife_csid_ver2_handle_event_err(csid_hw,
 			irq_status_ipp,
 			err_type,
+			false,
 			res);
 unlock:
 	spin_unlock(&csid_hw->lock_state);
@@ -1598,6 +1636,7 @@ static int cam_ife_csid_ver2_ppp_bottom_half(
 		cam_ife_csid_ver2_handle_event_err(csid_hw,
 			irq_status_ppp,
 			err_type,
+			false,
 			res);
 unlock:
 	spin_unlock(&csid_hw->lock_state);
@@ -1625,7 +1664,7 @@ static int cam_ife_csid_ver2_rdi_bottom_half(
 	uint32_t                                      irq_status_rdi;
 	uint32_t                                      err_mask;
 	uint32_t                                      err_type = 0;
-	bool                                         skip_sof_notify = false;
+	bool                                          skip_evt_notify = false;
 	struct cam_isp_hw_event_info                  evt_info;
 
 	if (!handler_priv || !evt_payload_priv) {
@@ -1706,7 +1745,7 @@ static int cam_ife_csid_ver2_rdi_bottom_half(
 	if (err_type) {
 
 		cam_ife_csid_ver2_handle_event_err(csid_hw,
-			irq_status_rdi, err_type, res);
+			irq_status_rdi, err_type, false, res);
 		goto end;
 	}
 
@@ -1720,19 +1759,34 @@ static int cam_ife_csid_ver2_rdi_bottom_half(
 	evt_info.reg_val = irq_status_rdi;
 	evt_info.hw_type = CAM_ISP_HW_TYPE_CSID;
 
-	/* Check for secondary evt */
-	if ((path_cfg->en_secondary_evt) &&
-		(irq_status_rdi & IFE_CSID_VER2_PATH_CAMIF_SOF)) {
-		evt_info.is_secondary_evt = true;
-		CAM_DBG(CAM_ISP,
-			"CSID[%u] RDI:%u notify CAMIF SOF as secondary evt",
-			csid_hw->hw_intf->hw_idx, res->res_id);
+	/* Check for specific secondary events */
+	if (path_cfg->sec_evt_config.en_secondary_evt) {
+		if ((irq_status_rdi & IFE_CSID_VER2_PATH_CAMIF_SOF) &&
+			(path_cfg->sec_evt_config.evt_type & CAM_IFE_CSID_EVT_SOF)) {
+			evt_info.is_secondary_evt = true;
+			csid_hw->event_cb(csid_hw->token,
+				CAM_ISP_HW_EVENT_SOF, (void *)&evt_info);
+			skip_evt_notify = true;
+		}
 
-		csid_hw->event_cb(csid_hw->token,
-			CAM_ISP_HW_EVENT_SOF, (void *)&evt_info);
-		skip_sof_notify = true;
+		if ((irq_status_rdi & IFE_CSID_VER2_PATH_CAMIF_EPOCH0) &&
+			(path_cfg->sec_evt_config.evt_type & CAM_IFE_CSID_EVT_EPOCH)) {
+			evt_info.is_secondary_evt = true;
+			csid_hw->event_cb(csid_hw->token,
+				CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info);
+			skip_evt_notify = true;
+		}
+
+		if ((irq_status_rdi &
+			IFE_CSID_VER2_PATH_SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP) &&
+			(path_cfg->sec_evt_config.evt_type &
+			CAM_IFE_CSID_EVT_SENSOR_SYNC_FRAME_DROP)) {
+			cam_ife_csid_ver2_handle_event_err(csid_hw,
+				irq_status_rdi, CAM_ISP_HW_ERROR_CSID_SENSOR_FRAME_DROP, true, res);
+		}
 	}
 
+	evt_info.is_secondary_evt = false;
 	if (!path_cfg->handle_camif_irq)
 		goto end;
 
@@ -1741,7 +1795,7 @@ static int cam_ife_csid_ver2_rdi_bottom_half(
 				CAM_ISP_HW_EVENT_EOF,
 				(void *)&evt_info);
 
-	if (!skip_sof_notify && (irq_status_rdi & IFE_CSID_VER2_PATH_CAMIF_SOF))
+	if (!skip_evt_notify && (irq_status_rdi & IFE_CSID_VER2_PATH_CAMIF_SOF))
 		csid_hw->event_cb(csid_hw->token,
 				CAM_ISP_HW_EVENT_SOF,
 				(void *)&evt_info);
@@ -1751,7 +1805,7 @@ static int cam_ife_csid_ver2_rdi_bottom_half(
 				CAM_ISP_HW_EVENT_REG_UPDATE,
 				(void *)&evt_info);
 
-	if (irq_status_rdi & IFE_CSID_VER2_PATH_CAMIF_EPOCH0)
+	if (!skip_evt_notify && (irq_status_rdi & IFE_CSID_VER2_PATH_CAMIF_EPOCH0))
 		csid_hw->event_cb(csid_hw->token,
 				CAM_ISP_HW_EVENT_EPOCH,
 				(void *)&evt_info);
@@ -2081,6 +2135,45 @@ err:
 	return rc;
 }
 
+static bool cam_ife_csid_hw_ver2_need_unpack_mipi(
+	struct cam_ife_csid_ver2_hw                  *csid_hw,
+	struct cam_csid_hw_reserve_resource_args     *reserve,
+	const struct cam_ife_csid_ver2_path_reg_info *path_reg,
+	uint32_t                                      format)
+{
+	bool  need_unpack = false;
+
+	switch(format) {
+	case CAM_FORMAT_MIPI_RAW_8:
+		need_unpack = (bool)(path_reg->capabilities & CAM_IFE_CSID_CAP_MIPI8_UNPACK);
+		break;
+	case CAM_FORMAT_MIPI_RAW_10:
+		need_unpack = (bool)(path_reg->capabilities & CAM_IFE_CSID_CAP_MIPI10_UNPACK);
+		break;
+	case CAM_FORMAT_MIPI_RAW_12:
+		need_unpack = (bool)(path_reg->capabilities & CAM_IFE_CSID_CAP_MIPI12_UNPACK);
+		break;
+	case CAM_FORMAT_MIPI_RAW_14:
+		need_unpack = (bool)(path_reg->capabilities & CAM_IFE_CSID_CAP_MIPI14_UNPACK);
+		break;
+	case CAM_FORMAT_MIPI_RAW_16:
+		need_unpack = (bool)(path_reg->capabilities & CAM_IFE_CSID_CAP_MIPI16_UNPACK);
+		break;
+	case CAM_FORMAT_MIPI_RAW_20:
+		need_unpack = (bool)(path_reg->capabilities & CAM_IFE_CSID_CAP_MIPI20_UNPACK);
+		break;
+	default:
+		need_unpack = false;
+		break;
+	}
+
+	CAM_DBG(CAM_ISP, "CSID[%u], RDI_%u format %u need_unpack %u sfe_shdr %u",
+		csid_hw->hw_intf->hw_idx, reserve->res_id, format, need_unpack,
+		reserve->sfe_inline_shdr);
+
+	return need_unpack;
+}
+
 static int cam_ife_csid_hw_ver2_config_path_data(
 	struct cam_ife_csid_ver2_hw *csid_hw,
 	struct cam_ife_csid_ver2_path_cfg *path_cfg,
@@ -2093,6 +2186,7 @@ static int cam_ife_csid_hw_ver2_config_path_data(
 		(struct cam_ife_csid_ver2_reg_info *)csid_hw->core_info->csid_reg;
 	struct cam_ife_csid_cid_data *cid_data = &csid_hw->cid_data[cid];
 	struct cam_isp_resource_node *res = &csid_hw->path_res[reserve->res_id];
+	const struct cam_ife_csid_ver2_path_reg_info  *path_reg = NULL;
 
 	for(i = 0; i < reserve->in_port->num_valid_vc_dt; i++)
 		path_cfg->in_format[i] = reserve->in_port->format[i];
@@ -2109,7 +2203,9 @@ static int cam_ife_csid_hw_ver2_config_path_data(
 	path_cfg->vertical_bin = reserve->in_port->vertical_bin;
 	path_cfg->qcfa_bin = reserve->in_port->qcfa_bin;
 	path_cfg->num_bytes_out = reserve->in_port->num_bytes_out;
-	path_cfg->en_secondary_evt = reserve->en_secondary_evt;
+	path_cfg->sec_evt_config.en_secondary_evt = reserve->sec_evt_config.en_secondary_evt;
+	path_cfg->sec_evt_config.evt_type = reserve->sec_evt_config.evt_type;
+	path_reg = csid_reg->path_reg[res->res_id];
 
 	if (reserve->sync_mode == CAM_ISP_HW_SYNC_MASTER) {
 		path_cfg->start_pixel = reserve->in_port->left_start;
@@ -2163,11 +2259,18 @@ static int cam_ife_csid_hw_ver2_config_path_data(
 	case CAM_IFE_PIX_PATH_RES_RDI_3:
 	case CAM_IFE_PIX_PATH_RES_RDI_4:
 		is_rpp = path_cfg->crop_enable || path_cfg->drop_enable;
+		/*
+		 * if csid gives unpacked out, packing needs to be done at
+		 * WM side if needed, based on the format the decision is
+		 * taken at WM side
+		 */
+		reserve->use_wm_pack = cam_ife_csid_hw_ver2_need_unpack_mipi(csid_hw,
+			reserve, path_reg, path_cfg->out_format);
 		rc = cam_ife_csid_get_format_rdi(
 			path_cfg->in_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0],
 			path_cfg->out_format,
 			&path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0],
-			is_rpp);
+			is_rpp, reserve->use_wm_pack);
 		if (rc)
 			goto end;
 
@@ -2178,7 +2281,7 @@ static int cam_ife_csid_hw_ver2_config_path_data(
 				path_cfg->in_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_1],
 				path_cfg->out_format,
 				&path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_1],
-				is_rpp);
+				is_rpp, reserve->use_wm_pack);
 			if (rc)
 				goto end;
 		}
@@ -2290,41 +2393,32 @@ static int cam_ife_csid_ver_config_camif(
 	struct cam_csid_hw_reserve_resource_args  *reserve,
 	struct cam_ife_csid_ver2_path_cfg *path_cfg)
 {
-	int rc = 0;
-	uint32_t epoch0 = 0;
 	struct cam_ife_csid_ver2_reg_info *csid_reg;
-	const struct cam_ife_csid_ver2_path_reg_info  *rdi_reg = NULL;
 
 	csid_reg = (struct cam_ife_csid_ver2_reg_info *)
-		    csid_hw->core_info->csid_reg;
+		csid_hw->core_info->csid_reg;
 
 	switch (reserve->res_id) {
-	case  CAM_IFE_PIX_PATH_RES_IPP:
-		epoch0 = (path_cfg->end_line - path_cfg->start_line)/
-			csid_reg->cmn_reg->epoch_div_factor;
-		break;
+	case CAM_IFE_PIX_PATH_RES_IPP:
 	case CAM_IFE_PIX_PATH_RES_RDI_0:
 	case CAM_IFE_PIX_PATH_RES_RDI_1:
 	case CAM_IFE_PIX_PATH_RES_RDI_2:
 	case CAM_IFE_PIX_PATH_RES_RDI_3:
 	case CAM_IFE_PIX_PATH_RES_RDI_4:
-		rdi_reg = csid_reg->path_reg[reserve->res_id];
-		if (!rdi_reg) {
-			rc = -EINVAL;
-			CAM_ERR(CAM_ISP, "CSID[%d] invalid res %d",
-				csid_hw->hw_intf->hw_idx, reserve->res_id);
-			goto end;
-		}
-		epoch0 = rdi_reg->epoch0_cfg_val;
+		path_cfg->camif_data.epoch0 =
+		(path_cfg->end_line - path_cfg->start_line) /
+		csid_reg->cmn_reg->epoch_div_factor;
+
+		CAM_DBG(CAM_ISP, "CSID[%d] res_id: %u epoch0: 0x%x",
+			csid_hw->hw_intf->hw_idx, reserve->res_id,
+			path_cfg->camif_data.epoch0);
+		break;
+	default:
+		CAM_DBG(CAM_ISP, "No CAMIF epoch update for res: %u", reserve->res_id);
 		break;
 	}
 
-	path_cfg->camif_data.epoch0 = epoch0;
-
-end:
-	CAM_DBG(CAM_ISP, "CSID[%d] epoch0: 0x%x",
-			csid_hw->hw_intf->hw_idx, epoch0);
-	return rc;
+	return 0;
 }
 
 int cam_ife_csid_hw_ver2_hw_cfg(
@@ -2497,9 +2591,9 @@ int cam_ife_csid_ver2_reserve(void *hw_priv,
 	csid_hw->token  = reserve->cb_priv;
 	reserve->buf_done_controller = csid_hw->buf_done_irq_controller;
 	res->cdm_ops = reserve->cdm_ops;
-	csid_hw->flags.sfe_inline_shdr = reserve->sfe_inline_shdr;
+	csid_hw->flags.sfe_en = reserve->sfe_en;
+	path_cfg->sfe_shdr = reserve->sfe_inline_shdr;
 	csid_hw->flags.offline_mode = reserve->is_offline;
-
 	reserve->need_top_cfg = csid_reg->need_top_cfg;
 
 	CAM_DBG(CAM_ISP, "CSID[%u] Resource[id: %d name:%s] state %d cid %d",
@@ -2595,7 +2689,7 @@ end:
 	return rc;
 }
 
-static int cam_ife_csid_ver2_shdr_cfg(
+static int cam_ife_csid_ver2_res_master_slave_cfg(
 	struct cam_ife_csid_ver2_hw *csid_hw,
 	uint32_t res_id)
 {
@@ -2622,6 +2716,9 @@ static int cam_ife_csid_ver2_shdr_cfg(
 	case CAM_IFE_PIX_PATH_RES_RDI_2:
 		val |= BIT(csid_reg->cmn_reg->shdr_slave_rdi2_shift);
 		break;
+	case CAM_IFE_PIX_PATH_RES_PPP:
+		val |= BIT(csid_reg->cmn_reg->shdr_slave_ppp_shift);
+		break;
 	default:
 		break;
 	}
@@ -2708,8 +2805,14 @@ static int cam_ife_csid_ver2_init_config_rdi_path(
 			(cmn_reg->timestamp_strobe_val <<
 				cmn_reg->timestamp_stb_sel_shift_val);
 
+	if (cam_ife_csid_ver2_disable_sof_retime(csid_hw, res))
+		cfg0 |= 1 << path_reg->sof_retiming_dis_shift;
+
 	cam_io_w_mb(cfg0, mem_base + path_reg->cfg0_addr);
 
+	CAM_DBG(CAM_ISP, "CSID[%d] %s cfg0_addr 0x%x",
+		csid_hw->hw_intf->hw_idx, res->res_name, cfg0);
+
 	/*Configure Multi VC DT combo */
 	if (cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].valid) {
 		val = (cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].vc <<
@@ -2757,6 +2860,12 @@ static int cam_ife_csid_ver2_init_config_rdi_path(
 			(cmn_reg->timestamp_strobe_val <<
 				cmn_reg->timestamp_stb_sel_shift_val);
 
+	/* We use line smoothting only on RDI_0 in all usecases */
+	if ((path_reg->capabilities &
+		CAM_IFE_CSID_CAP_LINE_SMOOTHING_IN_RDI) &&
+		(res->res_id == CAM_IFE_PIX_PATH_RES_RDI_0))
+		cfg1 |= 1 << path_reg->pix_store_en_shift_val;
+
 	cam_io_w_mb(cfg1, mem_base + path_reg->cfg1_addr);
 
 	/* set frame drop pattern to 0 and period to 1 */
@@ -2784,8 +2893,10 @@ static int cam_ife_csid_ver2_init_config_rdi_path(
 			path_reg->err_recovery_cfg0_addr);
 	}
 
-	if (csid_hw->flags.sfe_inline_shdr)
-		cam_ife_csid_ver2_shdr_cfg(csid_hw, res->res_id);
+	if (path_cfg->sfe_shdr ||
+		(csid_hw->flags.rdi_lcr_en &&
+		 res->res_id == CAM_IFE_PIX_PATH_RES_RDI_0))
+		cam_ife_csid_ver2_res_master_slave_cfg(csid_hw, res->res_id);
 
 	if (csid_hw->debug_info.debug_val &
 		CAM_IFE_CSID_DEBUG_ENABLE_HBI_VBI_INFO) {
@@ -2860,6 +2971,9 @@ static int cam_ife_csid_ver2_init_config_pxl_path(
 			(cmn_reg->timestamp_strobe_val <<
 				cmn_reg->timestamp_stb_sel_shift_val);
 
+	if (cam_ife_csid_ver2_disable_sof_retime(csid_hw, res))
+		cfg0 |= 1 << path_reg->sof_retiming_dis_shift;
+
 	CAM_DBG(CAM_ISP, "CSID[%d] res:%d cfg0_addr 0x%x",
 		csid_hw->hw_intf->hw_idx, res->res_id, cfg0);
 
@@ -2971,6 +3085,9 @@ static int cam_ife_csid_ver2_init_config_pxl_path(
 			mem_base + path_reg->format_measure_cfg0_addr);
 	}
 
+	if (csid_hw->flags.rdi_lcr_en && res->res_id == CAM_IFE_PIX_PATH_RES_PPP)
+		cam_ife_csid_ver2_res_master_slave_cfg(csid_hw, res->res_id);
+
 	res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW;
 	return rc;
 }
@@ -3069,18 +3186,23 @@ static int cam_ife_csid_ver2_program_rdi_path(
 	}
 
 	if ((csid_hw->flags.offline_mode ||
-		csid_hw->flags.sfe_inline_shdr) &&
+		path_cfg->sfe_shdr) &&
 		(res->res_id == CAM_IFE_PIX_PATH_RES_RDI_0)) {
 		val |= path_reg->camif_irq_mask;
 		path_cfg->handle_camif_irq = true;
 	}
 
-	/* Currently CAMIF SOF is the secondary evt enabled for HW mgr */
-	if (path_cfg->en_secondary_evt) {
-		val |= IFE_CSID_VER2_PATH_CAMIF_SOF;
+	/* Enable secondary events dictated by HW mgr for RDI paths */
+	if (path_cfg->sec_evt_config.en_secondary_evt) {
+		if (path_cfg->sec_evt_config.evt_type & CAM_IFE_CSID_EVT_SOF)
+			val |= IFE_CSID_VER2_PATH_CAMIF_SOF;
+
+		if (path_cfg->sec_evt_config.evt_type & CAM_IFE_CSID_EVT_EPOCH)
+			val |= IFE_CSID_VER2_PATH_CAMIF_EPOCH0;
+
 		CAM_DBG(CAM_ISP,
-			"Enable camif SOF irq for res: %s",
-			res->res_name);
+			"Enable camif: %d evt irq for res: %s",
+			path_cfg->sec_evt_config.evt_type, res->res_name);
 	}
 
 	res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING;
@@ -3669,7 +3791,6 @@ err:
 	return rc;
 }
 
-
 static int cam_ife_csid_ver2_program_top(
 	struct cam_ife_csid_ver2_hw *csid_hw)
 {
@@ -3711,6 +3832,8 @@ static int cam_ife_csid_ver2_program_top(
 	val |= csid_hw->top_cfg.out_ife_en <<
 			top_reg->out_ife_en_shift_val;
 
+	val |= csid_hw->top_cfg.rdi_lcr;
+
 	cam_io_w_mb(val,
 		soc_info->reg_map[CAM_IFE_CSID_TOP_MEM_BASE_ID].mem_base +
 		top_reg->io_path_cfg0_addr[csid_hw->hw_intf->hw_idx]);
@@ -4034,6 +4157,7 @@ static int cam_ife_csid_ver2_disable_core(
 	spin_lock_bh(&csid_hw->lock_state);
 	csid_hw->flags.device_enabled = false;
 	csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN;
+	csid_hw->flags.rdi_lcr_en = false;
 	spin_unlock_bh(&csid_hw->lock_state);
 	rc = cam_ife_csid_disable_soc_resources(soc_info);
 	if (rc)
@@ -4041,7 +4165,6 @@ static int cam_ife_csid_ver2_disable_core(
 			csid_hw->hw_intf->hw_idx);
 
 	csid_hw->counters.error_irq_count = 0;
-
 	return rc;
 }
 
@@ -4196,13 +4319,20 @@ int cam_ife_csid_ver2_start(void *hw_priv, void *args,
 		}
 	}
 
-	/* Configure RUP/AUP/MUP @ streamon for all paths together */
+	/*
+	 * Configure RUP/AUP/MUP @ streamon for all enabled paths
+	 * For internal recovery - skip this, CDM packet corresponding
+	 * to the request being recovered will apply the appropriate RUP/AUP/MUP
+	 */
 	rup_aup_mask |= (csid_hw->rx_cfg.mup << csid_reg->cmn_reg->mup_shift_val);
-	cam_io_w_mb(rup_aup_mask,
-		soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base +
-		csid_reg->cmn_reg->rup_aup_cmd_addr);
-	CAM_DBG(CAM_ISP, "CSID:%u RUP_AUP_MUP: 0x%x at start",
-		csid_hw->hw_intf->hw_idx, rup_aup_mask);
+	if (!start_args->is_internal_start)
+		cam_io_w_mb(rup_aup_mask,
+			soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base +
+			csid_reg->cmn_reg->rup_aup_cmd_addr);
+
+	CAM_DBG(CAM_ISP, "CSID:%u RUP_AUP_MUP: 0x%x at start updated: %s",
+		csid_hw->hw_intf->hw_idx, rup_aup_mask,
+		CAM_BOOL_TO_YESNO(!start_args->is_internal_start));
 
 	cam_ife_csid_ver2_enable_csi2(csid_hw);
 
@@ -4214,6 +4344,7 @@ int cam_ife_csid_ver2_start(void *hw_priv, void *args,
 		cam_ife_csid_ver2_enable_path(csid_hw, res);
 	}
 
+	csid_hw->flags.reset_awaited = false;
 end:
 	mutex_unlock(&csid_hw->hw_info->hw_mutex);
 	return rc;
@@ -4256,6 +4387,7 @@ int cam_ife_csid_ver2_stop(void *hw_priv,
 		csid_stop->num_res);
 
 	csid_hw->flags.device_enabled = false;
+	csid_hw->flags.rdi_lcr_en = false;
 
 	reset.reset_type = (csid_hw->flags.fatal_err_detected) ? CAM_IFE_CSID_RESET_GLOBAL :
 		CAM_IFE_CSID_RESET_PATH;
@@ -4487,12 +4619,18 @@ static int cam_ife_csid_ver2_reg_update(
 	reg_val_pair[0] = csid_reg->cmn_reg->rup_aup_cmd_addr;
 	reg_val_pair[1] = rup_aup_mask;
 
-	reg_val_pair[1] |= csid_hw->rx_cfg.mup <<
-			csid_reg->cmn_reg->mup_shift_val;
+	/* If not an actual request, configure last applied MUP */
+	if (rup_args->reg_write)
+		reg_val_pair[1] |= (rup_args->last_applied_mup <<
+			csid_reg->cmn_reg->mup_shift_val);
+	else
+		reg_val_pair[1] |= (csid_hw->rx_cfg.mup <<
+			csid_reg->cmn_reg->mup_shift_val);
 
-	CAM_DBG(CAM_ISP, "CSID:%d reg_update_cmd 0x%X offset 0x%X",
+	CAM_DBG(CAM_ISP, "CSID:%d configure rup_aup_mup: 0x%x offset: 0x%x via %s",
 		csid_hw->hw_intf->hw_idx,
-		reg_val_pair[1], reg_val_pair[0]);
+		reg_val_pair[1], reg_val_pair[0],
+		(rup_args->reg_write ? "AHB" : "CDM"));
 
 	if (rup_args->reg_write) {
 		soc_info = &csid_hw->hw_info->soc_info;
@@ -4876,6 +5014,59 @@ end:
 	return 0;
 }
 
+static int cam_ife_csid_ver2_rdi_lcr_cfg(
+	struct cam_ife_csid_ver2_hw  *csid_hw, void *cmd_args)
+{
+	const struct cam_ife_csid_ver2_path_reg_info *path_reg;
+	struct cam_ife_csid_ver2_reg_info            *csid_reg;
+	struct cam_ife_csid_ver2_path_cfg            *path_cfg = NULL;
+	struct cam_isp_resource_node                 *res = cmd_args;
+
+	if (!csid_hw || !cmd_args) {
+		CAM_ERR(CAM_ISP, "Invalid params");
+		return -EINVAL;
+	}
+
+	csid_reg = (struct cam_ife_csid_ver2_reg_info *)
+			csid_hw->core_info->csid_reg;
+
+	path_reg = csid_reg->path_reg[res->res_id];
+	path_cfg = (struct cam_ife_csid_ver2_path_cfg *)res->res_priv;
+	if (!path_cfg || !path_reg || !path_reg->capabilities ||
+		!(path_reg->capabilities & CAM_IFE_CSID_CAP_INPUT_LCR)) {
+		CAM_ERR(CAM_ISP, "Invalid res %s", res->res_name);
+		return -EINVAL;
+	}
+
+	if (!path_cfg->sfe_shdr && (res->res_id != CAM_IFE_PIX_PATH_RES_RDI_0)) {
+		CAM_ERR(CAM_ISP, "Invalid res: %s, capabilities 0x%x sfe_shdr: %u",
+			res->res_name, path_reg->capabilities, path_cfg->sfe_shdr);
+		return -EINVAL;
+	}
+
+	/*
+	 * LCR should not be on for a resource if CSID is giving packed data
+	 * this case would come for formats which are not supported
+	 * */
+	if (path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].packing_fmt) {
+		CAM_ERR(CAM_ISP, "LCR enabled for %s, csid out packed not supported",
+			res->res_name);
+		return -EINVAL;
+	}
+
+	if (csid_hw->flags.sfe_en)
+		csid_hw->top_cfg.rdi_lcr |= BIT(res->res_id) <<
+			csid_reg->top_reg->rdi_lcr_shift_val;
+
+	csid_hw->flags.rdi_lcr_en = true;
+	path_cfg->lcr_en = true;
+
+	CAM_DBG(CAM_ISP, "CSID[%u] %s top_cfg %u",
+		csid_hw->hw_intf->hw_idx, res->res_name, csid_hw->top_cfg.rdi_lcr);
+
+	return 0;
+}
+
 static int cam_ife_csid_ver2_process_cmd(void *hw_priv,
 	uint32_t cmd_type, void *cmd_args, uint32_t arg_size)
 {
@@ -4953,6 +5144,9 @@ static int cam_ife_csid_ver2_process_cmd(void *hw_priv,
 	case CAM_ISP_HW_CMD_CSID_DISCARD_INIT_FRAMES:
 		rc = cam_ife_csid_ver2_set_discard_frame_cfg(csid_hw, cmd_args);
 		break;
+	case CAM_ISP_HW_CMD_RDI_LCR_CFG:
+		rc = cam_ife_csid_ver2_rdi_lcr_cfg(csid_hw, cmd_args);
+		break;
 	default:
 		CAM_ERR(CAM_ISP, "CSID:%d unsupported cmd:%d",
 			csid_hw->hw_intf->hw_idx, cmd_type);

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h

@@ -108,6 +108,7 @@ struct cam_ife_csid_ver2_top_cfg {
 	bool          dual_en;
 	bool          offline_sfe_en;
 	bool          out_ife_en;
+	bool          rdi_lcr;
 };
 
 struct cam_ife_csid_ver2_evt_payload {
@@ -134,6 +135,7 @@ struct cam_ife_csid_ver2_camif_data {
  * @cid:                    cid value for path
  * @path_format:            Array of Path format which contains format
  *                          info i.e Decode format, Packing format etc
+ * @sec_evt_config:         Secondary event config from HW mgr for a given path
  * @in_format:              Array of input format which contains format type
  * @out_format:             output format
  * @start_pixel:            start pixel for horizontal crop
@@ -165,45 +167,47 @@ struct cam_ife_csid_ver2_camif_data {
  *                          If we know the number of paths to avoid configuring discard
  *                          for before processing discard config we can skip it for
  *                          the corresponding paths
- * @en_secondary_evt:       Enable secondary evt for this path, to notify
- *                          hw manager
+ * @sfe_shdr:               flag to indicate if sfe is inline shdr
+ * @lcr_en:                 Flag to indicate if path is part can be input to LCR
  *
  */
 struct cam_ife_csid_ver2_path_cfg {
-	struct cam_ife_csid_ver2_camif_data camif_data;
-	struct timespec64                   error_ts;
-	struct cam_ife_csid_path_format     path_format[CAM_ISP_VC_DT_CFG];
-	uint32_t                            cid;
-	uint32_t                            in_format[CAM_ISP_VC_DT_CFG];
-	uint32_t                            out_format;
-	uint32_t                            start_pixel;
-	uint32_t                            end_pixel;
-	uint32_t                            width;
-	uint32_t                            start_line;
-	uint32_t                            end_line;
-	uint32_t                            height;
-	uint32_t                            master_idx;
-	uint64_t                            clk_rate;
-	uint32_t                            horizontal_bin;
-	uint32_t                            vertical_bin;
-	uint32_t                            qcfa_bin;
-	uint32_t                            hor_ver_bin;
-	uint32_t                            num_bytes_out;
-	uint32_t                            irq_handle;
-	uint32_t                            err_irq_handle;
-	uint32_t                            discard_irq_handle;
-	uint32_t                            irq_reg_idx;
-	uint32_t                            sof_cnt;
-	uint32_t                            num_frames_discard;
-	enum cam_isp_hw_sync_mode           sync_mode;
-	bool                                vfr_en;
-	bool                                frame_id_dec_en;
-	bool                                crop_enable;
-	bool                                drop_enable;
-	bool                                handle_camif_irq;
-	bool                                discard_init_frames;
-	bool                                skip_discard_frame_cfg;
-	bool                                en_secondary_evt;
+	struct cam_ife_csid_ver2_camif_data  camif_data;
+	struct timespec64                    error_ts;
+	struct cam_ife_csid_path_format      path_format[CAM_ISP_VC_DT_CFG];
+	struct cam_csid_secondary_evt_config sec_evt_config;
+	uint32_t                             cid;
+	uint32_t                             in_format[CAM_ISP_VC_DT_CFG];
+	uint32_t                             out_format;
+	uint32_t                             start_pixel;
+	uint32_t                             end_pixel;
+	uint32_t                             width;
+	uint32_t                             start_line;
+	uint32_t                             end_line;
+	uint32_t                             height;
+	uint32_t                             master_idx;
+	uint64_t                             clk_rate;
+	uint32_t                             horizontal_bin;
+	uint32_t                             vertical_bin;
+	uint32_t                             qcfa_bin;
+	uint32_t                             hor_ver_bin;
+	uint32_t                             num_bytes_out;
+	uint32_t                             irq_handle;
+	uint32_t                             err_irq_handle;
+	uint32_t                             discard_irq_handle;
+	uint32_t                             irq_reg_idx;
+	uint32_t                             sof_cnt;
+	uint32_t                             num_frames_discard;
+	enum cam_isp_hw_sync_mode            sync_mode;
+	bool                                 vfr_en;
+	bool                                 frame_id_dec_en;
+	bool                                 crop_enable;
+	bool                                 drop_enable;
+	bool                                 handle_camif_irq;
+	bool                                 discard_init_frames;
+	bool                                 skip_discard_frame_cfg;
+	bool                                 sfe_shdr;
+	bool                                 lcr_en;
 };
 
 struct cam_ife_csid_ver2_top_reg_info {
@@ -215,6 +219,7 @@ struct cam_ife_csid_ver2_top_reg_info {
 	uint32_t dual_sync_sel_shift_val;
 	uint32_t dual_en_shift_val;
 	uint32_t master_slave_sel_shift_val;
+	uint32_t rdi_lcr_shift_val;
 	uint32_t master_sel_val;
 	uint32_t slave_sel_val;
 	uint32_t io_path_cfg_rst_val;
@@ -348,6 +353,8 @@ struct cam_ife_csid_ver2_path_reg_info {
 	uint32_t epoch1_cfg_val;
 	uint32_t epoch0_shift_val;
 	uint32_t epoch1_shift_val;
+	uint32_t sof_retiming_dis_shift;
+	uint32_t capabilities;
 };
 
 struct cam_ife_csid_ver2_common_reg_info {
@@ -421,6 +428,7 @@ struct cam_ife_csid_ver2_common_reg_info {
 	uint32_t multi_vcdt_ts_combo_en_shift_val;
 	uint32_t multi_vcdt_en_shift_val;
 	uint32_t mup_shift_val;
+	uint32_t shdr_slave_ppp_shift;
 	uint32_t shdr_slave_rdi2_shift;
 	uint32_t shdr_slave_rdi1_shift;
 	uint32_t shdr_master_rdi0_shift;

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite680.h

@@ -692,6 +692,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.resume_frame_boundary          = 1,
 		.overflow_ctrl_en               = 1,
 		.overflow_ctrl_mode_val         = 0x8,
+		.mipi_pack_supported            = 1,
 		.packing_fmt_shift_val          = 15,
 		.plain_alignment_shift_val      = 11,
 		.plain_fmt_shift_val            = 12,
@@ -781,6 +782,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.resume_frame_boundary          = 1,
 		.overflow_ctrl_en               = 1,
 		.overflow_ctrl_mode_val         = 0x8,
+		.mipi_pack_supported            = 1,
 		.packing_fmt_shift_val          = 15,
 		.plain_alignment_shift_val      = 11,
 		.plain_fmt_shift_val            = 12,
@@ -870,6 +872,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.resume_frame_boundary          = 1,
 		.overflow_ctrl_en               = 1,
 		.overflow_ctrl_mode_val         = 0x8,
+		.mipi_pack_supported            = 1,
 		.packing_fmt_shift_val          = 15,
 		.plain_alignment_shift_val      = 11,
 		.plain_fmt_shift_val            = 12,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite_mod.c

@@ -52,6 +52,10 @@ static const struct of_device_id cam_ife_csid_lite_dt_match[] = {
 		.compatible = "qcom,csid-lite480",
 		.data = &cam_ife_csid_lite_480_hw_info,
 	},
+	{
+		.compatible = "qcom,csid-lite570",
+		.data = &cam_ife_csid_lite_480_hw_info,
+	},
 	{
 		.compatible = "qcom,csid-lite580",
 		.data = &cam_ife_csid_lite_480_hw_info,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_mod.c

@@ -14,6 +14,7 @@
 #include "cam_ife_csid175.h"
 #include "cam_ife_csid175_200.h"
 #include "cam_ife_csid480.h"
+#include "cam_ife_csid570.h"
 #include "cam_ife_csid580.h"
 #include "cam_ife_csid680.h"
 #include "cam_ife_csid780.h"
@@ -50,6 +51,11 @@ static struct cam_ife_csid_core_info cam_ife_csid480_hw_info = {
 	.sw_version  = CAM_IFE_CSID_VER_1_0,
 };
 
+static struct cam_ife_csid_core_info cam_ife_csid570_hw_info = {
+	.csid_reg = &cam_ife_csid_570_reg_info,
+	.sw_version  = CAM_IFE_CSID_VER_1_0,
+};
+
 static struct cam_ife_csid_core_info cam_ife_csid580_hw_info = {
 	.csid_reg = &cam_ife_csid_580_reg_info,
 	.sw_version  = CAM_IFE_CSID_VER_1_0,
@@ -91,6 +97,10 @@ static const struct of_device_id cam_ife_csid_dt_match[] = {
 		.compatible = "qcom,csid480",
 		.data = &cam_ife_csid480_hw_info,
 	},
+	{
+		.compatible = "qcom,csid570",
+		.data = &cam_ife_csid570_hw_info,
+	},
 	{
 		.compatible = "qcom,csid580",
 		.data = &cam_ife_csid580_hw_info,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.c

@@ -37,6 +37,14 @@ static int cam_ife_csid_get_dt_properties(struct cam_hw_soc_info *soc_info)
 		soc_private->is_ife_csid_lite = true;
 	}
 
+	rc = of_property_read_u32(of_node, "rt-wrapper-base", &soc_private->rt_wrapper_base);
+	if (rc) {
+		soc_private->rt_wrapper_base = 0;
+		CAM_DBG(CAM_ISP, "rc: %d Error reading rt_wrapper_base for core_idx: %u",
+			rc, soc_info->index);
+		rc = 0;
+	}
+
 	return rc;
 }
 

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.h

@@ -16,12 +16,14 @@
  * @cpas_handle:             Handle returned on registering with CPAS driver.
  *                           This handle is used for all further interface
  *                           with CPAS.
+ * @rt_wrapper_base:        Base address of the RT-Wrapper if the hw is in rt-wrapper
  * @is_ife_csid_lite:        Flag to indicate Whether a full csid or a Lite csid
  * @max_width_enabled:       Flag to enable max width restriction
  * @max_width:               Maxinum allowed width
  */
 struct cam_csid_soc_private {
 	uint32_t cpas_handle;
+	uint32_t rt_wrapper_base;
 	bool     is_ife_csid_lite;
 	bool     max_width_enabled;
 	uint32_t max_width;

drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h

@@ -53,6 +53,17 @@ enum cam_ife_cid_res_id {
 	CAM_IFE_CSID_CID_MAX,
 };
 
+/**
+ * enum cam_ife_csid_secondary_evt_type - Specify the event type
+ */
+enum cam_ife_csid_secondary_evt_type {
+	CAM_IFE_CSID_EVT_SOF = 1,
+	CAM_IFE_CSID_EVT_EPOCH,
+	CAM_IFE_CSID_EVT_EOF,
+	CAM_IFE_CSID_EVT_SENSOR_SYNC_FRAME_DROP,
+	CAM_IFE_CSID_EVT_MAX,
+};
+
 /**
  * struct cam_ife_csid_hw_caps- get the CSID hw capability
  * @num_rdis:             number of rdis supported by CSID HW device
@@ -142,6 +153,17 @@ struct cam_isp_in_port_generic_info {
 	struct cam_isp_out_port_generic_info    *data;
 };
 
+/**
+ * struct cam_csid_secondary_evt_config - secondary event enablement
+ * @evt_type:           Type of secondary event enabled [SOF/EPOCH/EOF...]
+ * @en_secondary_evt:   Enable secondary event
+ *
+ */
+struct cam_csid_secondary_evt_config {
+	enum cam_ife_csid_secondary_evt_type evt_type;
+	bool                                 en_secondary_evt;
+};
+
 /**
  * struct cam_csid_hw_reserve_resource- hw reserve
  * @res_type :           Reource type CID or PATH
@@ -159,21 +181,23 @@ struct cam_isp_in_port_generic_info {
  * @dual_core_id:        In case of dual csid, core id of another hw
  *                       reserve
  * @node_res :           Reserved resource structure pointer
+ * @sec_evt_config:      Config to enable secondary events for the given resource
+ *                       depending on the use-case
  * @crop_enable :        Flag to indicate CSID crop enable
  * @drop_enable :        Flag to indicate CSID drop enable
  * @sfe_inline_shdr:     Flag to indicate if sfe is inline shdr
  * @is_offline :         Flag to indicate offline
  * @need_top_cfg:        Flag to indicate if top cfg is needed
- * @en_secondary_evt:    Flag to enable secondary event for the given resource
- *                       depending on the use-case
  * @tasklet:             Tasklet to schedule bottom halves
  * @buf_done_controller: IRQ controller for buf done for version 680 hw
  * @cdm_ops:             CDM Ops
  * @event_cb:            Callback function to hw mgr in case of hw events
- * @cb_priv:             Private pointer to return to callback
  * @phy_sel:             Phy selection number if tpg is enabled from userspace
+ * @cb_priv:             Private pointer to return to callback
  * @can_use_lite:        Flag to indicate if current call qualifies for
  *                       acquire lite
+ * @sfe_en:              Flag to indicate if SFE is enabled
+ * @use_wm_pack:         [OUT]Flag to indicate if WM packing is to be used for packing
  *
  */
 struct cam_csid_hw_reserve_resource_args {
@@ -185,19 +209,21 @@ struct cam_csid_hw_reserve_resource_args {
 	uint32_t                                  master_idx;
 	uint32_t                                  dual_core_id;
 	struct cam_isp_resource_node             *node_res;
+	struct cam_csid_secondary_evt_config      sec_evt_config;
 	bool                                      crop_enable;
 	bool                                      drop_enable;
 	bool                                      sfe_inline_shdr;
 	bool                                      is_offline;
 	bool                                      need_top_cfg;
-	bool                                      en_secondary_evt;
 	void                                     *tasklet;
 	void                                     *buf_done_controller;
 	void                                     *cdm_ops;
 	cam_hw_mgr_event_cb_func                  event_cb;
 	uint32_t                                  phy_sel;
-	bool                                      can_use_lite;
 	void                                     *cb_priv;
+	bool                                      can_use_lite;
+	bool                                      sfe_en;
+	bool                                      use_wm_pack;
 };
 
 /**
@@ -257,6 +283,7 @@ struct cam_csid_hw_stop_args {
 struct cam_csid_hw_start_args {
 	struct cam_isp_resource_node            **node_res;
 	uint32_t                                  num_res;
+	bool                                      is_internal_start;
 };
 
 
@@ -361,15 +388,17 @@ struct cam_ife_csid_dual_sync_args {
 /*
  * struct cam_isp_csid_reg_update_args:
  *
- * @cmd:           cmd buf update args
- * @node_res:      Node res pointer
- * @num_res:       Num of resources
- * @reg_write:     if set use AHB to config rup/aup
+ * @cmd:              cmd buf update args
+ * @node_res:         Node res pointer
+ * @num_res:          Num of resources
+ * @last_applied_mup: last applied MUP
+ * @reg_write:        if set use AHB to config rup/aup
  */
 struct cam_isp_csid_reg_update_args {
 	struct cam_isp_hw_cmd_buf_update  cmd;
 	struct cam_isp_resource_node     *res[CAM_IFE_PIX_PATH_RES_MAX];
 	uint32_t                          num_res;
+	uint32_t                          last_applied_mup;
 	bool                              reg_write;
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h

@@ -48,10 +48,12 @@ struct cam_isp_bw_control_args {
  *
  * @hw_intf:             Isp hw intf pointer
  * @request_id:          Request Id
+ * @skip_clk_data_rst:   Skip resetting any clk info
  */
 struct cam_isp_apply_clk_bw_args {
 	struct cam_hw_intf                *hw_intf;
 	uint64_t                           request_id;
+	bool                               skip_clk_data_rst;
 };
 
 /*
@@ -201,6 +203,7 @@ enum cam_isp_hw_cmd_type {
 	CAM_ISP_HW_CMD_INIT_CONFIG_UPDATE,
 	CAM_ISP_HW_CSID_MINI_DUMP,
 	CAM_ISP_HW_BUS_MINI_DUMP,
+	CAM_ISP_HW_CMD_RDI_LCR_CFG,
 	CAM_ISP_HW_CMD_MAX,
 };
 
@@ -271,6 +274,34 @@ struct cam_isp_blanking_config {
 	struct cam_isp_resource_node       *node_res;
 };
 
+/**
+ * struct cam_isp_hw_error_event_info:
+ *
+ * @brief:              Structure to pass error event details to hw mgr
+ *
+ * @err_type:           Type of error being reported
+ *
+ */
+struct cam_isp_hw_error_event_info {
+	uint32_t    err_type;
+};
+
+/**
+ * struct cam_isp_hw_compdone_event_info:
+ *
+ * @brief:              Structure to pass bufdone event details to hw mgr
+ *
+ * @num_res:            Number of valid resource IDs in this event
+ * @res_id:             Resource IDs to report buf dones
+ * @last_consumed_addr: Last consumed addr for resource ID at that index
+ *
+ */
+struct cam_isp_hw_compdone_event_info {
+	uint32_t num_res;
+	uint32_t res_id[CAM_NUM_OUT_PER_COMP_IRQ_MAX];
+	uint32_t last_consumed_addr[CAM_NUM_OUT_PER_COMP_IRQ_MAX];
+};
+
 /*
  * struct cam_isp_hw_event_info:
  *
@@ -280,10 +311,10 @@ struct cam_isp_blanking_config {
  * @is_secondary_evt:  Indicates if event was requested by hw mgr
  * @res_id:            Unique resource ID
  * @hw_idx:            IFE hw index
- * @err_type:          Error type if any
  * @reg_val:           Any critical register value captured during irq handling
  * @hw_type:           Hw Type sending the event
  * @in_core_idx:       Input core type if CSID error evt
+ * @event_data:        Any additional data specific to this event
  *
  */
 struct cam_isp_hw_event_info {
@@ -291,32 +322,10 @@ struct cam_isp_hw_event_info {
 	bool                           is_secondary_evt;
 	uint32_t                       res_id;
 	uint32_t                       hw_idx;
-	uint32_t                       err_type;
 	uint32_t                       reg_val;
 	uint32_t                       hw_type;
 	uint32_t                       in_core_idx;
-};
-
-/**
- * struct cam_isp_hw_compdone_event_info:
- *
- * @brief:              Structure to pass bufdone event details to hw mgr
- *
- * @res_type:           Type of IFE/SFE resource
- * @hw_idx:             IFE/SFE hw index
- * @num_res:            Number of valid resource IDs in this event
- * @hw_type:            Hw Type sending the event (IFE or SFE)
- * @res_id:             Resource IDs to report buf dones
- * @last_consumed_addr: Last consumed addr for resource ID at that index
- *
- */
-struct cam_isp_hw_compdone_event_info {
-	enum cam_isp_resource_type     res_type;
-	uint32_t                       hw_idx;
-	uint32_t                       hw_type;
-	uint32_t num_res;
-	uint32_t res_id[CAM_NUM_OUT_PER_COMP_IRQ_MAX];
-	uint32_t last_consumed_addr[CAM_NUM_OUT_PER_COMP_IRQ_MAX];
+	void                          *event_data;
 };
 
 /*

drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_sfe_hw_intf.h

@@ -11,7 +11,6 @@
 #include "cam_cpas_api.h"
 
 #define SFE_CORE_BASE_IDX           0
-#define SFE_RT_CDM_BASE_IDX         1
 #define CAM_SFE_HW_NUM_MAX          2
 
 enum cam_sfe_core_id {
@@ -307,6 +306,7 @@ struct cam_sfe_hw_sfe_in_acquire_args {
  * @split_id:                In case of Dual SFE, this is Left or Right.
  * @is_master:               In case of Dual SFE, this is Master or Slave.
  * @cdm_ops:                 CDM operations
+ * @use_wm_pack:             Flag to indicalte packing at WM side
  */
 struct cam_sfe_hw_sfe_out_acquire_args {
 	struct cam_isp_resource_node         *rsrc_node;
@@ -316,6 +316,7 @@ struct cam_sfe_hw_sfe_out_acquire_args {
 	enum cam_isp_hw_split_id              split_id;
 	uint32_t                              is_master;
 	struct cam_cdm_utils_ops             *cdm_ops;
+	bool                                  use_wm_pack;
 };
 
 /*

drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h

@@ -142,6 +142,7 @@ struct cam_vfe_hw_vfe_bus_rd_acquire_args {
  * @dual_slave_core:         If Master and Slave exists, HW Index of Slave
  * @cdm_ops:                 CDM operations
  * @disable_ubwc_comp:       Disable UBWC compression
+ * @use_wm_pack:             Use WM Packing
  */
 struct cam_vfe_hw_vfe_out_acquire_args {
 	struct cam_isp_resource_node         *rsrc_node;
@@ -153,6 +154,7 @@ struct cam_vfe_hw_vfe_out_acquire_args {
 	uint32_t                              dual_slave_core;
 	struct cam_cdm_utils_ops             *cdm_ops;
 	bool                                  disable_ubwc_comp;
+	bool                                  use_wm_pack;
 };
 
 /*

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_soc.c

@@ -21,6 +21,15 @@ static int cam_sfe_get_dt_properties(struct cam_hw_soc_info *soc_info)
 		goto end;
 	}
 
+	rc = of_property_read_u32(pdev->dev.of_node, "rt-wrapper-base",
+		&soc_private->rt_wrapper_base);
+	if (rc) {
+		soc_private->rt_wrapper_base = 0;
+		CAM_DBG(CAM_ISP, "rc: %d Error reading rt_wrapper_base for core_idx: %u",
+			rc, soc_info->index);
+		rc = 0;
+	}
+
 	soc_private->num_pid = 0;
 	num_pid = of_property_count_u32_elems(pdev->dev.of_node, "cam_hw_pid");
 	CAM_DBG(CAM_SFE, "sfe:%d pid count %d", soc_info->index, num_pid);

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_soc.h

@@ -18,12 +18,14 @@
  *                           This handle is used for all further interface
  *                           with CPAS.
  * @cpas_version:            CPAS version
+ * @* @rt_wrapper_base:      Base address of the RT-Wrapper if the hw is in rt-wrapper
  * @num_pid:                 Number of pids of sfe
  * @pid:                     SFE pid values list
  */
 struct cam_sfe_soc_private {
 	uint32_t    cpas_handle;
 	uint32_t    cpas_version;
+	uint32_t    rt_wrapper_base;
 	uint32_t    num_pid;
 	uint32_t    pid[CAM_ISP_HW_MAX_PID_VAL];
 };

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_rd.c

@@ -673,6 +673,7 @@ static int cam_sfe_bus_rd_handle_irq_bottom_half(
 	struct cam_sfe_bus_rd_priv            *bus_priv;
 	struct cam_sfe_bus_rd_common_data     *common_data = NULL;
 	struct cam_isp_hw_event_info           evt_info;
+	struct cam_isp_hw_error_event_info     err_evt_info;
 	uint32_t status = 0, constraint_violation = 0;
 
 	if (!handler_priv || !evt_payload_priv)
@@ -690,10 +691,12 @@ static int cam_sfe_bus_rd_handle_irq_bottom_half(
 			bus_priv->common_data.core_index,
 			constraint_violation);
 
+		evt_info.hw_type  = CAM_ISP_HW_TYPE_SFE;
 		evt_info.hw_idx = bus_priv->common_data.core_index;
 		evt_info.res_type = CAM_ISP_RESOURCE_SFE_RD;
 		evt_info.res_id = CAM_SFE_BUS_RD_MAX;
-		evt_info.err_type = CAM_SFE_IRQ_STATUS_VIOLATION;
+		err_evt_info.err_type = CAM_SFE_IRQ_STATUS_VIOLATION;
+		evt_info.event_data = (void *)&err_evt_info;
 
 		if (common_data->event_cb)
 			common_data->event_cb(NULL,

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.c

@@ -113,8 +113,6 @@ struct cam_sfe_bus_wr_wm_resource_data {
 	struct cam_sfe_bus_reg_offset_bus_client  *hw_regs;
 	struct cam_sfe_wr_scratch_buf_info scratch_buf_info;
 
-	bool                 init_cfg_done;
-	bool                 hfr_cfg_done;
 
 	uint32_t             offset;
 	uint32_t             width;
@@ -137,9 +135,12 @@ struct cam_sfe_bus_wr_wm_resource_data {
 	uint32_t             acquired_width;
 	uint32_t             acquired_height;
 
-	bool                 enable_caching;
 	uint32_t             cache_cfg;
 	int32_t              current_scid;
+	bool                 enable_caching;
+	bool                 init_cfg_done;
+	bool                 hfr_cfg_done;
+	bool                 use_wm_pack;
 };
 
 struct cam_sfe_bus_wr_comp_grp_data {
@@ -501,7 +502,8 @@ static inline void cam_sfe_bus_config_rdi_wm_frame_based_mode(
 static int cam_sfe_bus_config_rdi_wm(
 	struct cam_sfe_bus_wr_wm_resource_data  *rsrc_data)
 {
-	rsrc_data->pack_fmt = 0x0;
+
+	rsrc_data->pack_fmt = PACKER_FMT_PLAIN_128;
 	switch (rsrc_data->format) {
 	case CAM_FORMAT_MIPI_RAW_10:
 		if (rsrc_data->wm_mode == CAM_SFE_WM_LINE_BASED_MODE) {
@@ -514,6 +516,12 @@ static int cam_sfe_bus_config_rdi_wm(
 			CAM_WARN(CAM_SFE, "No index mode support for SFE WM: %u",
 				rsrc_data->index);
 		}
+
+		if (rsrc_data->use_wm_pack) {
+			rsrc_data->pack_fmt = PACKER_FMT_MIPI10;
+			if (rsrc_data->wm_mode == CAM_SFE_WM_LINE_BASED_MODE)
+				rsrc_data->width = ALIGNUP((rsrc_data->acquired_width), 16);
+		}
 		break;
 	case CAM_FORMAT_MIPI_RAW_6:
 		if (rsrc_data->wm_mode == CAM_SFE_WM_LINE_BASED_MODE) {
@@ -550,6 +558,12 @@ static int cam_sfe_bus_config_rdi_wm(
 			CAM_WARN(CAM_SFE, "No index mode support for SFE WM: %u",
 				rsrc_data->index);
 		}
+
+		if (rsrc_data->use_wm_pack) {
+			rsrc_data->pack_fmt = PACKER_FMT_MIPI12;
+			if (rsrc_data->wm_mode == CAM_SFE_WM_LINE_BASED_MODE)
+				rsrc_data->width = ALIGNUP((rsrc_data->acquired_width), 16);
+		}
 		break;
 	case CAM_FORMAT_MIPI_RAW_14:
 		if (rsrc_data->wm_mode == CAM_SFE_WM_LINE_BASED_MODE) {
@@ -562,6 +576,11 @@ static int cam_sfe_bus_config_rdi_wm(
 			CAM_WARN(CAM_SFE, "No index mode support for SFE WM: %u",
 				rsrc_data->index);
 		}
+		if (rsrc_data->use_wm_pack) {
+			rsrc_data->pack_fmt = PACKER_FMT_MIPI14;
+			if (rsrc_data->wm_mode == CAM_SFE_WM_LINE_BASED_MODE)
+				rsrc_data->width = ALIGNUP((rsrc_data->acquired_width), 16);
+		}
 		break;
 	case CAM_FORMAT_MIPI_RAW_16:
 		if (rsrc_data->wm_mode == CAM_SFE_WM_LINE_BASED_MODE) {
@@ -659,15 +678,14 @@ static int cam_sfe_bus_config_rdi_wm(
 }
 
 static int cam_sfe_bus_acquire_wm(
-	struct cam_sfe_bus_wr_priv            *bus_priv,
-	struct cam_isp_out_port_generic_info  *out_port_info,
-	void                                  *tasklet,
-	enum cam_sfe_bus_sfe_out_type          sfe_out_res_id,
-	enum cam_sfe_bus_plane_type            plane,
-	struct cam_isp_resource_node          *wm_res,
-	uint32_t                              *comp_done_mask,
-	uint32_t                               is_dual,
-	enum cam_sfe_bus_wr_comp_grp_type     *comp_grp_id)
+	struct cam_sfe_bus_wr_priv             *bus_priv,
+	struct cam_sfe_hw_sfe_out_acquire_args *out_acq_args,
+	void                                   *tasklet,
+	enum cam_sfe_bus_sfe_out_type           sfe_out_res_id,
+	enum cam_sfe_bus_plane_type             plane,
+	struct cam_isp_resource_node           *wm_res,
+	uint32_t                               *comp_done_mask,
+	enum cam_sfe_bus_wr_comp_grp_type      *comp_grp_id)
 {
 	int32_t wm_idx = 0, rc;
 	struct cam_sfe_bus_wr_wm_resource_data  *rsrc_data = NULL;
@@ -681,15 +699,16 @@ static int cam_sfe_bus_acquire_wm(
 
 	rsrc_data = wm_res->res_priv;
 	wm_idx = rsrc_data->index;
-	rsrc_data->format = out_port_info->format;
+	rsrc_data->format = out_acq_args->out_port_info->format;
+	rsrc_data->use_wm_pack = out_acq_args->use_wm_pack;
 	rsrc_data->pack_fmt = cam_sfe_bus_get_packer_fmt(bus_priv,
 		rsrc_data->format, wm_idx);
 
-	rsrc_data->width = out_port_info->width;
-	rsrc_data->height = out_port_info->height;
-	rsrc_data->acquired_width = out_port_info->width;
-	rsrc_data->acquired_height = out_port_info->height;
-	rsrc_data->is_dual = is_dual;
+	rsrc_data->width = out_acq_args->out_port_info->width;
+	rsrc_data->height = out_acq_args->out_port_info->height;
+	rsrc_data->acquired_width = out_acq_args->out_port_info->width;
+	rsrc_data->acquired_height = out_acq_args->out_port_info->height;
+	rsrc_data->is_dual = out_acq_args->is_dual;
 	rsrc_data->enable_caching =  false;
 	rsrc_data->offset = 0;
 
@@ -1350,13 +1369,12 @@ static int cam_sfe_bus_acquire_sfe_out(void *priv, void *acquire_args,
 	/* Acquire WM and retrieve COMP GRP ID */
 	for (i = 0; i < rsrc_data->num_wm; i++) {
 		rc = cam_sfe_bus_acquire_wm(bus_priv,
-			out_acquire_args->out_port_info,
+			out_acquire_args,
 			acq_args->tasklet,
 			sfe_out_res_id,
 			i,
 			&rsrc_data->wm_res[i],
 			&client_done_mask,
-			out_acquire_args->is_dual,
 			&comp_grp_id);
 		if (rc) {
 			CAM_ERR(CAM_SFE,
@@ -1803,7 +1821,8 @@ static int cam_sfe_bus_handle_sfe_out_done_bottom_half(
 	struct cam_isp_resource_node           *sfe_out = handler_priv;
 	struct cam_sfe_bus_wr_out_data         *rsrc_data = sfe_out->res_priv;
 	struct cam_sfe_bus_wr_irq_evt_payload  *evt_payload = evt_payload_priv;
-	struct cam_isp_hw_compdone_event_info    evt_info = {0};
+	struct cam_isp_hw_event_info            evt_info;
+	struct cam_isp_hw_compdone_event_info   compdone_evt_info = {0};
 	void                                   *ctx = NULL;
 	uint32_t                       out_list[CAM_SFE_BUS_SFE_OUT_MAX];
 
@@ -1838,14 +1857,15 @@ static int cam_sfe_bus_handle_sfe_out_done_bottom_half(
 			goto end;
 		}
 
-		evt_info.num_res = num_out;
+		compdone_evt_info.num_res = num_out;
 		for (i = 0; i < num_out; i++) {
-			evt_info.res_id[i] = out_list[i];
+			compdone_evt_info.res_id[i] = out_list[i];
 			cam_sfe_bus_get_last_consumed_addr(
 				rsrc_data->bus_priv,
-				evt_info.res_id[i], &val);
-			evt_info.last_consumed_addr[i] = val;
+				compdone_evt_info.res_id[i], &val);
+			compdone_evt_info.last_consumed_addr[i] = val;
 		}
+		evt_info.event_data = (void *)&compdone_evt_info;
 		if (rsrc_data->common_data->event_cb)
 			rsrc_data->common_data->event_cb(ctx, evt_id,
 				(void *)&evt_info);
@@ -2147,11 +2167,14 @@ static int cam_sfe_bus_wr_irq_bottom_half(
 	cam_sfe_bus_wr_put_evt_payload(common_data, &evt_payload);
 
 	if (!skip_err_notify) {
+		struct cam_isp_hw_error_event_info err_evt_info;
+
 		evt_info.hw_idx = common_data->core_index;
 		evt_info.hw_type = CAM_ISP_HW_TYPE_SFE;
 		evt_info.res_type = CAM_ISP_RESOURCE_SFE_OUT;
 		evt_info.res_id = CAM_SFE_BUS_SFE_OUT_MAX;
-		evt_info.err_type = CAM_SFE_IRQ_STATUS_VIOLATION;
+		err_evt_info.err_type = CAM_SFE_IRQ_STATUS_VIOLATION;
+		evt_info.event_data = (void *)&err_evt_info;
 
 		if (common_data->event_cb) {
 			struct cam_isp_resource_node      *out_rsrc_node = NULL;

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_top/cam_sfe_top.c

@@ -38,6 +38,7 @@ struct cam_sfe_top_priv {
 	uint32_t                        last_bw_counter;
 	uint32_t                        last_clk_counter;
 	uint64_t                        total_bw_applied;
+	struct cam_axi_vote             agg_incoming_vote;
 	struct cam_axi_vote             req_axi_vote[CAM_SFE_TOP_IN_PORT_MAX];
 	struct cam_axi_vote             last_bw_vote[CAM_DELAY_CLK_BW_REDUCTION_NUM_REQ];
 	uint64_t                        last_total_bw_vote[CAM_DELAY_CLK_BW_REDUCTION_NUM_REQ];
@@ -61,6 +62,7 @@ struct cam_sfe_top_priv {
 	struct cam_sfe_top_hw_info     *hw_info;
 	uint32_t                        num_clc_module;
 	struct cam_sfe_top_debug_info  (*clc_dbg_mod_info)[CAM_SFE_TOP_DBG_REG_MAX][8];
+	bool                            skip_clk_data_rst;
 };
 
 struct cam_sfe_path_data {
@@ -109,7 +111,7 @@ static int cam_sfe_top_set_axi_bw_vote(
 	soc_info = top_priv->common_data.soc_info;
 	soc_private = (struct cam_sfe_soc_private *)soc_info->soc_private;
 
-	CAM_DBG(CAM_PERF, "SFE:%d Sending final BW to cpas bw_state:%s bw_vote:%llu req_id:%d",
+	CAM_DBG(CAM_PERF, "SFE:%d Sending final BW to cpas bw_state:%s bw_vote:%llu req_id:%ld",
 		top_priv->common_data.hw_intf->hw_idx,
 		cam_sfe_top_clk_bw_state_to_string(top_priv->bw_state),
 		total_bw_new_vote, (start_stop ? -1 : request_id));
@@ -140,7 +142,7 @@ static int cam_sfe_top_set_hw_clk_rate(
 	soc_info = top_priv->common_data.soc_info;
 	soc_private = (struct cam_sfe_soc_private *)soc_info->soc_private;
 
-	CAM_DBG(CAM_PERF, "Applying SFE:%d Clock name=%s idx=%d clk=%llu req_id=%d",
+	CAM_DBG(CAM_PERF, "Applying SFE:%d Clock name=%s idx=%d clk=%llu req_id=%ld",
 		top_priv->common_data.hw_intf->hw_idx, soc_info->clk_name[soc_info->src_clk_idx],
 		soc_info->src_clk_idx, final_clk_rate, (start_stop ? -1 : request_id));
 
@@ -318,14 +320,13 @@ int cam_sfe_top_calc_axi_bw_vote(struct cam_sfe_top_priv *top_priv,
 	bool start_stop, struct cam_axi_vote **to_be_applied_axi_vote,
 	uint64_t *total_bw_new_vote, uint64_t request_id)
 {
-	static struct cam_axi_vote agg_vote = {0};
 	int rc = 0;
 	uint32_t i;
 	uint32_t num_paths = 0;
 	bool bw_unchanged = true;
 	struct cam_axi_vote *final_bw_vote = NULL;
 
-	memset(&agg_vote, 0, sizeof(struct cam_axi_vote));
+	memset(&top_priv->agg_incoming_vote, 0, sizeof(struct cam_axi_vote));
 	for (i = 0; i < top_priv->num_in_ports; i++) {
 		if (top_priv->axi_vote_control[i] ==
 			CAM_ISP_BW_CONTROL_INCLUDE) {
@@ -341,7 +342,7 @@ int cam_sfe_top_calc_axi_bw_vote(struct cam_sfe_top_priv *top_priv,
 				goto end;
 			}
 
-			memcpy(&agg_vote.axi_path[num_paths],
+			memcpy(&top_priv->agg_incoming_vote.axi_path[num_paths],
 				&top_priv->req_axi_vote[i].axi_path[0],
 				top_priv->req_axi_vote[i].num_paths *
 				sizeof(
@@ -350,25 +351,25 @@ int cam_sfe_top_calc_axi_bw_vote(struct cam_sfe_top_priv *top_priv,
 		}
 	}
 
-	agg_vote.num_paths = num_paths;
+	top_priv->agg_incoming_vote.num_paths = num_paths;
 
-	for (i = 0; i < agg_vote.num_paths; i++) {
+	for (i = 0; i < top_priv->agg_incoming_vote.num_paths; i++) {
 		CAM_DBG(CAM_PERF,
 			"sfe[%d] : New BW Vote : counter[%d] [%s][%s] [%llu %llu %llu]",
 			top_priv->common_data.hw_intf->hw_idx,
 			top_priv->last_bw_counter,
 			cam_cpas_axi_util_path_type_to_string(
-			agg_vote.axi_path[i].path_data_type),
+			top_priv->agg_incoming_vote.axi_path[i].path_data_type),
 			cam_cpas_axi_util_trans_type_to_string(
-			agg_vote.axi_path[i].transac_type),
-			agg_vote.axi_path[i].camnoc_bw,
-			agg_vote.axi_path[i].mnoc_ab_bw,
-			agg_vote.axi_path[i].mnoc_ib_bw);
+			top_priv->agg_incoming_vote.axi_path[i].transac_type),
+			top_priv->agg_incoming_vote.axi_path[i].camnoc_bw,
+			top_priv->agg_incoming_vote.axi_path[i].mnoc_ab_bw,
+			top_priv->agg_incoming_vote.axi_path[i].mnoc_ib_bw);
 
-		*total_bw_new_vote += agg_vote.axi_path[i].camnoc_bw;
+		*total_bw_new_vote += top_priv->agg_incoming_vote.axi_path[i].camnoc_bw;
 	}
 
-	memcpy(&top_priv->last_bw_vote[top_priv->last_bw_counter], &agg_vote,
+	memcpy(&top_priv->last_bw_vote[top_priv->last_bw_counter], &top_priv->agg_incoming_vote,
 		sizeof(struct cam_axi_vote));
 	top_priv->last_total_bw_vote[top_priv->last_bw_counter] = *total_bw_new_vote;
 	top_priv->last_bw_counter = (top_priv->last_bw_counter + 1) %
@@ -378,7 +379,7 @@ int cam_sfe_top_calc_axi_bw_vote(struct cam_sfe_top_priv *top_priv,
 		bw_unchanged = false;
 
 	CAM_DBG(CAM_PERF,
-		"applied_total=%lld, new_total=%lld unchanged=%d, start_stop=%d req_id=%d",
+		"applied_total=%lld, new_total=%lld unchanged=%d, start_stop=%d req_id=%ld",
 		top_priv->total_bw_applied,
 		*total_bw_new_vote, bw_unchanged, start_stop, (start_stop ? -1 : request_id));
 
@@ -391,14 +392,14 @@ int cam_sfe_top_calc_axi_bw_vote(struct cam_sfe_top_priv *top_priv,
 
 	if (start_stop) {
 		/* need to vote current request immediately */
-		final_bw_vote = &agg_vote;
+		final_bw_vote = &top_priv->agg_incoming_vote;
 		/* Reset everything, we can start afresh */
 		memset(top_priv->last_bw_vote, 0, sizeof(struct cam_axi_vote) *
 			CAM_DELAY_CLK_BW_REDUCTION_NUM_REQ);
 		memset(top_priv->last_total_bw_vote, 0, sizeof(uint64_t) *
 			CAM_DELAY_CLK_BW_REDUCTION_NUM_REQ);
 		top_priv->last_bw_counter = 0;
-		top_priv->last_bw_vote[top_priv->last_bw_counter] = agg_vote;
+		top_priv->last_bw_vote[top_priv->last_bw_counter] = top_priv->agg_incoming_vote;
 		top_priv->last_total_bw_vote[top_priv->last_bw_counter] = *total_bw_new_vote;
 		top_priv->last_bw_counter = (top_priv->last_bw_counter + 1) %
 			CAM_DELAY_CLK_BW_REDUCTION_NUM_REQ;
@@ -443,7 +444,7 @@ int cam_sfe_top_calc_axi_bw_vote(struct cam_sfe_top_priv *top_priv,
 
 
 	CAM_DBG(CAM_PERF,
-		"sfe[%d] : Delayed update: applied_total=%lld new_total=%lld, start_stop=%d bw_state=%s req_id=%d",
+		"sfe[%d] : Delayed update: applied_total=%lld new_total=%lld, start_stop=%d bw_state=%s req_id=%ld",
 		top_priv->common_data.hw_intf->hw_idx, top_priv->total_bw_applied,
 		total_bw_new_vote, start_stop,
 		cam_sfe_top_clk_bw_state_to_string(top_priv->bw_state),
@@ -587,7 +588,7 @@ int cam_sfe_top_calc_hw_clk_rate(
 			max_req_clk_rate = top_priv->req_clk_rate[i];
 	}
 
-	if (start_stop) {
+	if (start_stop && !top_priv->skip_clk_data_rst) {
 		/* need to vote current clk immediately */
 		*final_clk_rate = max_req_clk_rate;
 		/* Reset everything, we can start afresh */
@@ -619,7 +620,7 @@ int cam_sfe_top_calc_hw_clk_rate(
 	else
 		top_priv->clk_state = CAM_CLK_BW_STATE_DECREASE;
 
-	CAM_DBG(CAM_PERF, "SFE:%d Clock state:%s hw_clk_rate:%llu req_id:%d",
+	CAM_DBG(CAM_PERF, "SFE:%d Clock state:%s hw_clk_rate:%llu req_id:%ld",
 		top_priv->common_data.hw_intf->hw_idx,
 		cam_sfe_top_clk_bw_state_to_string(top_priv->clk_state),
 		top_priv->applied_clk_rate, (start_stop ? -1 : request_id));
@@ -636,6 +637,7 @@ static int cam_sfe_top_get_base(
 	uint32_t                          mem_base = 0;
 	struct cam_isp_hw_get_cmd_update *cdm_args  = cmd_args;
 	struct cam_cdm_utils_ops         *cdm_util_ops = NULL;
+	struct cam_sfe_soc_private       *soc_private;
 
 	if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) {
 		CAM_ERR(CAM_SFE, "Invalid cmd size");
@@ -648,6 +650,12 @@ static int cam_sfe_top_get_base(
 		return -EINVAL;
 	}
 
+	soc_private = top_priv->common_data.soc_info->soc_private;
+	if (!soc_private) {
+		CAM_ERR(CAM_ISP, "soc_private is null");
+		return -EINVAL;
+	}
+
 	cdm_util_ops =
 		(struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops;
 
@@ -667,17 +675,19 @@ static int cam_sfe_top_get_base(
 		top_priv->common_data.soc_info,
 		SFE_CORE_BASE_IDX);
 
-	if (cdm_args->cdm_id == CAM_CDM_RT)
-		mem_base -= CAM_SOC_GET_REG_MAP_CAM_BASE(
-			top_priv->common_data.soc_info,
-			SFE_RT_CDM_BASE_IDX);
+	if (cdm_args->cdm_id == CAM_CDM_RT) {
+		if (!soc_private->rt_wrapper_base) {
+			CAM_ERR(CAM_ISP, "rt_wrapper_base_addr is null");
+			return -EINVAL;
+		}
+		mem_base -= soc_private->rt_wrapper_base;
+	}
 
 	CAM_DBG(CAM_SFE, "core %d mem_base 0x%x, CDM Id: %d",
 		top_priv->common_data.soc_info->index, mem_base,
 		cdm_args->cdm_id);
 
-	cdm_util_ops->cdm_write_changebase(
-	cdm_args->cmd.cmd_buf_addr, mem_base);
+	cdm_util_ops->cdm_write_changebase(cdm_args->cmd.cmd_buf_addr, mem_base);
 	cdm_args->cmd.used_bytes = (size * 4);
 
 	return 0;
@@ -816,6 +826,13 @@ static int cam_sfe_top_apply_clk_bw_update(struct cam_sfe_top_priv *top_priv,
 		goto end;
 	}
 
+	if (clk_bw_args->skip_clk_data_rst) {
+		top_priv->skip_clk_data_rst = true;
+		CAM_DBG(CAM_SFE, "SFE:%u requested to avoid clk data rst",
+			hw_intf->hw_idx);
+		return 0;
+	}
+
 	rc = cam_sfe_top_calc_hw_clk_rate(top_priv, false, &final_clk_rate, request_id);
 	if (rc) {
 		CAM_ERR(CAM_SFE,
@@ -837,7 +854,7 @@ static int cam_sfe_top_apply_clk_bw_update(struct cam_sfe_top_priv *top_priv,
 			cam_sfe_top_clk_bw_state_to_string(top_priv->bw_state));
 	}
 
-	CAM_DBG(CAM_PERF, "SFE:%d APPLY CLK/BW req_id:%d clk_state:%s bw_state:%s ",
+	CAM_DBG(CAM_PERF, "SFE:%d APPLY CLK/BW req_id:%ld clk_state:%s bw_state:%s ",
 		hw_intf->hw_idx, request_id,
 		cam_sfe_top_clk_bw_state_to_string(top_priv->clk_state),
 		cam_sfe_top_clk_bw_state_to_string(top_priv->bw_state));
@@ -951,6 +968,7 @@ static int cam_sfe_top_apply_clock_start_stop(struct cam_sfe_top_priv *top_priv)
 
 end:
 	top_priv->clk_state = CAM_CLK_BW_STATE_INIT;
+	top_priv->skip_clk_data_rst = false;
 	return rc;
 }
 
@@ -1384,12 +1402,15 @@ static int cam_sfe_top_handle_err_irq_bottom_half(
 
 	if (irq_status[0] &
 		top_priv->common_data.common_reg_data->error_irq_mask) {
+		struct cam_isp_hw_error_event_info err_evt_info;
+
 		viol_sts = payload->violation_status;
 		CAM_INFO(CAM_SFE, "Violation status 0x%x",
 			viol_sts);
 		cam_sfe_top_print_top_irq_error(top_priv,
 			irq_status[0], viol_sts);
-		evt_info.err_type = CAM_SFE_IRQ_STATUS_VIOLATION;
+		err_evt_info.err_type = CAM_SFE_IRQ_STATUS_VIOLATION;
+		evt_info.event_data = (void *)&err_evt_info;
 		cam_sfe_top_print_debug_reg_info(top_priv);
 		if (top_priv->event_cb)
 			top_priv->event_cb(top_priv->priv_per_stream,
@@ -1664,7 +1685,8 @@ int cam_sfe_top_stop(
 	sfe_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED;
 	for (i = 0; i < CAM_SFE_TOP_IN_PORT_MAX; i++) {
 		if (top_priv->in_rsrc[i].res_id == sfe_res->res_id) {
-			top_priv->req_clk_rate[i] = 0;
+			if (!top_priv->skip_clk_data_rst)
+				top_priv->req_clk_rate[i] = 0;
 			memset(&top_priv->req_axi_vote[i], 0,
 				sizeof(struct cam_axi_vote));
 			top_priv->axi_vote_control[i] =
@@ -1712,7 +1734,8 @@ int cam_sfe_top_stop(
 	 * when all resources are streamed off
 	 */
 	if (!top_priv->start_stop_cnt) {
-		top_priv->applied_clk_rate = 0;
+		if (!top_priv->skip_clk_data_rst)
+			top_priv->applied_clk_rate = 0;
 
 		if (top_priv->error_irq_handle > 0) {
 			cam_irq_controller_unsubscribe_irq(

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c

@@ -3109,6 +3109,7 @@ static int cam_tfe_csid_evt_bottom_half_handler(
 	struct cam_tfe_csid_hw *csid_hw;
 	struct cam_csid_evt_payload *evt_payload;
 	const struct cam_tfe_csid_reg_offset    *csid_reg;
+	struct cam_isp_hw_error_event_info err_evt_info;
 	struct cam_isp_hw_event_info event_info;
 	int i;
 	int rc = 0;
@@ -3175,13 +3176,14 @@ static int cam_tfe_csid_evt_bottom_half_handler(
 	 * which we want to offload to bottom half from
 	 * irq handlers
 	 */
-	event_info.err_type = evt_payload->evt_type;
+	err_evt_info.err_type = evt_payload->evt_type;
 	event_info.hw_idx = evt_payload->hw_idx;
 
 	switch (evt_payload->evt_type) {
 	case CAM_ISP_HW_ERROR_CSID_FATAL:
 		if (csid_hw->fatal_err_detected)
 			break;
+		event_info.event_data = (void *)&err_evt_info;
 		csid_hw->fatal_err_detected = true;
 		rc = csid_hw->event_cb(NULL,
 			CAM_ISP_HW_EVENT_ERROR, (void *)&event_info);
@@ -3258,6 +3260,7 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data)
 	uint32_t sof_irq_debug_en = 0, log_en = 0;
 	unsigned long flags;
 	uint32_t i, val, val1;
+	uint32_t data_idx;
 
 	if (!data) {
 		CAM_ERR(CAM_ISP, "CSID: Invalid arguments");
@@ -3265,6 +3268,7 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data)
 	}
 
 	csid_hw = (struct cam_tfe_csid_hw *)data;
+	data_idx = csid_hw->csi2_rx_cfg.phy_sel - 1;
 	CAM_DBG(CAM_ISP, "CSID %d IRQ Handling", csid_hw->hw_intf->hw_idx);
 
 	csid_reg = csid_hw->csid_info->csid_reg;
@@ -3397,8 +3401,7 @@ handle_fatal_error:
 		/* phy_sel starts from 1 and should never be zero*/
 		if (csid_hw->csi2_rx_cfg.phy_sel > 0) {
 			cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE,
-				CAM_SUBDEV_MESSAGE_IRQ_ERR,
-				(csid_hw->csi2_rx_cfg.phy_sel - 1));
+				CAM_SUBDEV_MESSAGE_IRQ_ERR, (void *)&data_idx);
 		}
 		cam_tfe_csid_handle_hw_err_irq(csid_hw,
 			CAM_ISP_HW_ERROR_CSID_FATAL, irq_status);

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c

@@ -456,6 +456,7 @@ static int cam_tfe_error_irq_bottom_half(
 	cam_hw_mgr_event_cb_func              event_cb,
 	void                                 *event_cb_priv)
 {
+	struct cam_isp_hw_error_event_info   err_evt_info;
 	struct cam_isp_hw_event_info         evt_info;
 	struct cam_tfe_hw_info              *hw_info;
 	uint32_t   error_detected = 0;
@@ -465,18 +466,18 @@ static int cam_tfe_error_irq_bottom_half(
 	evt_info.res_type = CAM_ISP_RESOURCE_TFE_IN;
 
 	if (evt_payload->irq_reg_val[0] & hw_info->error_irq_mask[0]) {
-		evt_info.err_type = CAM_TFE_IRQ_STATUS_OVERFLOW;
+		err_evt_info.err_type = CAM_TFE_IRQ_STATUS_OVERFLOW;
 		error_detected = 1;
 	}
 
 	if ((evt_payload->bus_irq_val[0] & hw_info->bus_error_irq_mask[0]) ||
 		(evt_payload->irq_reg_val[2] & hw_info->error_irq_mask[2])) {
-		evt_info.err_type = CAM_TFE_IRQ_STATUS_VIOLATION;
+		err_evt_info.err_type = CAM_TFE_IRQ_STATUS_VIOLATION;
 		error_detected = 1;
 	}
 
 	if (error_detected) {
-		evt_info.err_type = CAM_TFE_IRQ_STATUS_OVERFLOW;
+		evt_info.event_data = (void *)&err_evt_info;
 		top_priv->error_ts.tv_sec =
 			evt_payload->ts.mono_time.tv_sec;
 		top_priv->error_ts.tv_nsec =

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c

@@ -517,6 +517,7 @@ int cam_vfe_process_cmd(void *hw_priv, uint32_t cmd_type,
 	case CAM_ISP_HW_CMD_GET_PATH_PORT_MAP:
 	case CAM_ISP_HW_CMD_APPLY_CLK_BW_UPDATE:
 	case CAM_ISP_HW_CMD_INIT_CONFIG_UPDATE:
+	case CAM_ISP_HW_CMD_RDI_LCR_CFG:
 		rc = core_info->vfe_top->hw_ops.process_cmd(
 			core_info->vfe_top->top_priv, cmd_type, cmd_args,
 			arg_size);

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c

@@ -51,6 +51,14 @@ static int cam_vfe_get_dt_properties(struct cam_hw_soc_info *soc_info)
 		return rc;
 	}
 
+	rc = of_property_read_u32(of_node, "rt-wrapper-base", &vfe_soc_private->rt_wrapper_base);
+	if (rc) {
+		vfe_soc_private->rt_wrapper_base = 0;
+		CAM_DBG(CAM_ISP, "rc: %d Error reading rt_wrapper_base for core_idx: %u",
+			rc, soc_info->index);
+		rc = 0;
+	}
+
 	vfe_soc_private->is_ife_lite = false;
 	if (strnstr(soc_info->compatible, "lite",
 		strlen(soc_info->compatible)) != NULL) {

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.h

@@ -22,6 +22,7 @@
  *                           This handle is used for all further interface
  *                           with CPAS.
  * @cpas_version:            Has cpas version read from Hardware
+ * @rt_wrapper_base:         Base address of the RT-Wrapper if the hw is in rt-wrapper
  * @dsp_clk_index:           DSP clk index in optional clocks
  * @ubwc_static_ctrl:        UBWC static control configuration
  * @is_ife_lite:             Flag to indicate full vs lite IFE
@@ -32,6 +33,7 @@
 struct cam_vfe_soc_private {
 	uint32_t    cpas_handle;
 	uint32_t    cpas_version;
+	uint32_t    rt_wrapper_base;
 	int32_t     dsp_clk_index;
 	uint32_t    ubwc_static_ctrl[UBWC_STATIC_CONFIG_MAX];
 	bool        is_ife_lite;

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe.c

@@ -9,6 +9,7 @@
 #include "cam_vfe175.h"
 #include "cam_vfe175_130.h"
 #include "cam_vfe480.h"
+#include "cam_vfe570.h"
 #include "cam_vfe580.h"
 #include "cam_vfe680.h"
 #include "cam_vfe780.h"
@@ -42,6 +43,10 @@ static const struct of_device_id cam_vfe_dt_match[] = {
 		.compatible = "qcom,vfe480",
 		.data = &cam_vfe480_hw_info,
 	},
+	{
+		.compatible = "qcom,vfe570",
+		.data = &cam_vfe570_hw_info,
+	},
 	{
 		.compatible = "qcom,vfe580",
 		.data = &cam_vfe580_hw_info,
@@ -66,6 +71,10 @@ static const struct of_device_id cam_vfe_dt_match[] = {
 		.compatible = "qcom,vfe-lite480",
 		.data = &cam_vfe_lite48x_hw_info,
 	},
+	{
+		.compatible = "qcom,vfe-lite570",
+		.data = &cam_vfe_lite48x_hw_info,
+	},
 	{
 		.compatible = "qcom,vfe-lite580",
 		.data = &cam_vfe_lite48x_hw_info,

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe570.h

@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+
+#ifndef _CAM_VFE570_H_
+#define _CAM_VFE570_H_
+#include "cam_vfe480.h"
+#include "cam_vfe_top_ver3.h"
+#include "cam_vfe_core.h"
+
+static struct cam_vfe_camif_ver3_reg_data vfe_570_camif_reg_data = {
+	.pp_extern_reg_update_shift      = 4,
+	.dual_pd_extern_reg_update_shift = 17,
+	.extern_reg_update_mask          = 1,
+	.dual_ife_pix_en_shift           = 3,
+	.dual_ife_sync_sel_shift         = 18,
+	.operating_mode_shift            = 11,
+	.input_mux_sel_shift             = 5,
+	.pixel_pattern_shift             = 24,
+	.pixel_pattern_mask              = 0x7,
+	.dsp_mode_shift                  = 24,
+	.dsp_mode_mask                   = 0x1,
+	.dsp_en_shift                    = 23,
+	.dsp_en_mask                     = 0x1,
+	.reg_update_cmd_data             = 0x41,
+	.epoch_line_cfg                  = 0x00000014,
+	.sof_irq_mask                    = 0x00000001,
+	.epoch0_irq_mask                 = 0x00000004,
+	.epoch1_irq_mask                 = 0x00000008,
+	.eof_irq_mask                    = 0x00000002,
+	.error_irq_mask0                 = 0x82000200,
+	.error_irq_mask2                 = 0x30301F80,
+	.subscribe_irq_mask1             = 0x00000007,
+	.enable_diagnostic_hw            = 0x1,
+	.pp_camif_cfg_en_shift           = 0,
+	.pp_camif_cfg_ife_out_en_shift   = 8,
+	.top_debug_cfg_en                = 1,
+	.dual_vfe_sync_mask              = 0x3,
+	.input_bayer_fmt                 = 0,
+	.input_yuv_fmt                   = 1,
+
+};
+
+static struct cam_vfe_camif_lite_ver3_reg_data vfe570_camif_rdi1_reg_data = {
+	.extern_reg_update_shift         = 0,
+	.input_mux_sel_shift             = 7,
+	.reg_update_cmd_data             = 0x4,
+	.epoch_line_cfg                  = 0x0,
+	.sof_irq_mask                    = 0x100,
+	.epoch0_irq_mask                 = 0x400,
+	.epoch1_irq_mask                 = 0x800,
+	.eof_irq_mask                    = 0x200,
+	.error_irq_mask0                 = 0x10000000,
+	.error_irq_mask2                 = 0x40000,
+	.subscribe_irq_mask1             = 0x300,
+	.enable_diagnostic_hw            = 0x1,
+};
+
+struct cam_vfe_camif_lite_ver3_hw_info
+	vfe570_rdi_hw_info_arr[CAM_VFE_RDI_VER2_MAX] = {
+	{
+		.common_reg     = &vfe480_top_common_reg,
+		.camif_lite_reg = &vfe480_camif_rdi[0],
+		.reg_data       = &vfe480_camif_rdi_reg_data[0],
+	},
+	{
+		.common_reg     = &vfe480_top_common_reg,
+		.camif_lite_reg = &vfe480_camif_rdi[1],
+		.reg_data       = &vfe570_camif_rdi1_reg_data,
+	},
+	{
+		.common_reg     = &vfe480_top_common_reg,
+		.camif_lite_reg = &vfe480_camif_rdi[2],
+		.reg_data       = &vfe480_camif_rdi_reg_data[2],
+	},
+};
+
+static struct cam_vfe_top_ver3_hw_info vfe570_top_hw_info = {
+	.common_reg = &vfe480_top_common_reg,
+	.camif_hw_info = {
+		.common_reg     = &vfe480_top_common_reg,
+		.camif_reg      = &vfe480_camif_reg,
+		.reg_data       = &vfe_570_camif_reg_data,
+		},
+	.pdlib_hw_info = {
+		.common_reg     = &vfe480_top_common_reg,
+		.camif_lite_reg = &vfe480_camif_pd,
+		.reg_data       = &vfe480_camif_pd_reg_data,
+		},
+	.rdi_hw_info[0] = &vfe570_rdi_hw_info_arr[0],
+	.rdi_hw_info[1] = &vfe570_rdi_hw_info_arr[1],
+	.rdi_hw_info[2] = &vfe570_rdi_hw_info_arr[2],
+	.lcr_hw_info = {
+		.common_reg     = &vfe480_top_common_reg,
+		.camif_lite_reg = &vfe480_camif_lcr,
+		.reg_data       = &vfe480_camif_lcr_reg_data,
+		},
+	.num_mux = 6,
+	.mux_type = {
+		CAM_VFE_CAMIF_VER_3_0,
+		CAM_VFE_RDI_VER_1_0,
+		CAM_VFE_RDI_VER_1_0,
+		CAM_VFE_RDI_VER_1_0,
+		CAM_VFE_PDLIB_VER_1_0,
+		CAM_VFE_LCR_VER_1_0,
+	},
+	.num_path_port_map = 2,
+	.path_port_map = {
+		{CAM_ISP_HW_VFE_IN_LCR, CAM_ISP_IFE_OUT_RES_LCR},
+		{CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_2PD},
+	},
+};
+
+static struct cam_vfe_hw_info cam_vfe570_hw_info = {
+	.irq_hw_info                   = &vfe480_irq_hw_info,
+
+	.bus_version                   = CAM_VFE_BUS_VER_3_0,
+	.bus_hw_info                   = &vfe480_bus_hw_info,
+
+	.bus_rd_version                = CAM_VFE_BUS_RD_VER_1_0,
+	.bus_rd_hw_info                = &vfe480_bus_rd_hw_info,
+
+	.top_version                   = CAM_VFE_TOP_VER_3_0,
+	.top_hw_info                   = &vfe570_top_hw_info,
+};
+
+#endif /* _CAM_VFE570_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe780.h

@@ -472,6 +472,21 @@ static struct cam_vfe_top_ver4_pdaf_violation_desc vfe780_pdaf_violation_desc[]
 	},
 };
 
+static struct cam_vfe_top_ver4_pdaf_lcr_res_info vfe780_pdaf_lcr_res_mask[] = {
+	{
+		.res_id = CAM_ISP_HW_VFE_IN_RDI0,
+		.val = 0,
+	},
+	{
+		.res_id = CAM_ISP_HW_VFE_IN_RDI1,
+		.val = 1,
+	},
+	{
+		.res_id = CAM_ISP_HW_VFE_IN_RDI2,
+		.val= 2,
+	},
+};
+
 static struct cam_irq_register_set vfe780_top_irq_reg_set[2] = {
 	{
 		.mask_reg_offset   = 0x00000034,
@@ -530,6 +545,8 @@ static struct cam_vfe_top_ver4_reg_offset_common vfe780_top_common_reg = {
 	.bus_overflow_status      = 0x00000C68,
 	.top_debug_cfg            = 0x000000FC,
 	.num_top_debug_reg        = CAM_VFE_780_NUM_DBG_REG,
+	.pdaf_input_cfg_0         = 0x00000130,
+	.pdaf_input_cfg_1         = 0x00000134,
 	.top_debug = {
 		0x000000A0,
 		0x000000A4,
@@ -818,6 +835,8 @@ static struct cam_vfe_top_ver4_hw_info vfe780_top_hw_info = {
 	.num_pdaf_violation_errors       = ARRAY_SIZE(vfe780_pdaf_violation_desc),
 	.pdaf_violation_desc             = vfe780_pdaf_violation_desc,
 	.debug_reg_info                  = &vfe780_dbg_reg_info,
+	.pdaf_lcr_res_mask               = vfe780_pdaf_lcr_res_mask,
+	.num_pdaf_lcr_res                = ARRAY_SIZE(vfe780_pdaf_lcr_res_mask),
 };
 
 static struct cam_irq_register_set vfe780_bus_irq_reg[2] = {

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite68x.h

@@ -463,6 +463,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe680x_bus_hw_info = {
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
 			.num_wm        = 1,
 			.mid[0]        = 8,
+			.line_based    = 1,
 			.wm_idx        = {
 				0,
 			},
@@ -477,6 +478,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe680x_bus_hw_info = {
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_2,
 			.num_wm        = 1,
 			.mid[0]        = 9,
+			.line_based    = 1,
 			.wm_idx        = {
 				1,
 			},
@@ -491,6 +493,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe680x_bus_hw_info = {
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_3,
 			.num_wm        = 1,
 			.mid[0]        = 10,
+			.line_based    = 1,
 			.wm_idx        = {
 				2,
 			},
@@ -505,6 +508,7 @@ static struct cam_vfe_bus_ver3_hw_info vfe680x_bus_hw_info = {
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_4,
 			.num_wm        = 1,
 			.mid[0]        = 11,
+			.line_based    = 1,
 			.wm_idx        = {
 				3,
 			},

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c

@@ -1447,6 +1447,7 @@ static int cam_vfe_bus_err_bottom_half(void *handler_priv,
 	struct cam_vfe_bus_ver2_priv *bus_priv = handler_priv;
 	struct cam_vfe_bus_ver2_common_data *common_data;
 	struct cam_isp_hw_event_info evt_info;
+	struct cam_isp_hw_error_event_info err_evt_info;
 	uint32_t val = 0;
 
 	if (!handler_priv || !evt_payload_priv)
@@ -1532,10 +1533,14 @@ static int cam_vfe_bus_err_bottom_half(void *handler_priv,
 
 	cam_vfe_bus_put_evt_payload(common_data, &evt_payload);
 
+	evt_info.hw_type = CAM_ISP_HW_TYPE_VFE;
 	evt_info.hw_idx = common_data->core_index;
 	evt_info.res_type = CAM_ISP_RESOURCE_VFE_OUT;
 	evt_info.res_id = CAM_VFE_BUS_VER2_VFE_OUT_MAX;
 
+	err_evt_info.err_type = CAM_VFE_IRQ_STATUS_VIOLATION;
+	evt_info.event_data = (void *)&err_evt_info;
+
 	if (common_data->event_cb)
 		common_data->event_cb(NULL, CAM_ISP_HW_EVENT_ERROR,
 			(void *)&evt_info);
@@ -2476,7 +2481,8 @@ static int cam_vfe_bus_handle_vfe_out_done_bottom_half(
 	int rc = -EINVAL;
 	struct cam_isp_resource_node             *vfe_out = handler_priv;
 	struct cam_vfe_bus_ver2_vfe_out_data     *rsrc_data = vfe_out->res_priv;
-	struct cam_isp_hw_compdone_event_info      evt_info = {0};
+	struct cam_isp_hw_event_info              evt_info;
+	struct cam_isp_hw_compdone_event_info     compdone_evt_info = {0};
 	void                                     *ctx = NULL;
 	uint32_t                                  evt_id = 0;
 	uint32_t                                  comp_mask = 0;
@@ -2506,6 +2512,7 @@ static int cam_vfe_bus_handle_vfe_out_done_bottom_half(
 	case CAM_VFE_IRQ_STATUS_SUCCESS:
 		evt_id = evt_payload->evt_id;
 
+		evt_info.hw_type = CAM_ISP_HW_TYPE_VFE;
 		evt_info.res_type = vfe_out->res_type;
 		evt_info.hw_idx   = vfe_out->hw_intf->hw_idx;
 		if (rsrc_data->comp_grp) {
@@ -2523,14 +2530,15 @@ static int cam_vfe_bus_handle_vfe_out_done_bottom_half(
 				goto end;
 			}
 
-			evt_info.num_res = num_out;
+			compdone_evt_info.num_res = num_out;
 			for (i = 0; i < num_out; i++) {
-				evt_info.res_id[i] = out_list[i];
+				compdone_evt_info.res_id[i] = out_list[i];
 			}
 		} else {
-			evt_info.num_res = 1;
-			evt_info.res_id[0] = vfe_out->res_id;
+			compdone_evt_info.num_res = 1;
+			compdone_evt_info.res_id[0] = vfe_out->res_id;
 		}
+		evt_info.event_data = (void *)&compdone_evt_info;
 		if (rsrc_data->common_data->event_cb)
 			rsrc_data->common_data->event_cb(ctx,
 				evt_id, (void *)&evt_info);

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c

@@ -151,6 +151,7 @@ struct cam_vfe_bus_ver3_wm_resource_data {
 	uint32_t             acquired_width;
 	uint32_t             acquired_height;
 	uint32_t             default_line_based;
+	bool                 use_wm_pack;
 };
 
 struct cam_vfe_bus_ver3_comp_grp_data {
@@ -554,7 +555,7 @@ static int cam_vfe_bus_ver3_get_comp_vfe_out_res_id_list(
 		out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_BAYER_RS;
 
 	if (comp_mask & (BIT_ULL(CAM_VFE_BUS_VER3_VFE_OUT_PDAF_PARSED)))
-		out_list[count++] = CAM_VFE_BUS_VER3_VFE_OUT_PDAF_PARSED;
+		out_list[count++] = CAM_ISP_IFE_OUT_RES_PDAF_PARSED_DATA;
 
 	*num_out = count;
 	return 0;
@@ -742,6 +743,7 @@ static int cam_vfe_bus_ver3_handle_rup_bottom_half(void *handler_priv,
 
 	irq_status = payload->irq_reg_val[CAM_IFE_IRQ_BUS_VER3_REG_STATUS0];
 
+	evt_info.hw_type  = CAM_ISP_HW_TYPE_VFE;
 	evt_info.hw_idx = rsrc_data->common_data->core_index;
 	evt_info.res_type = CAM_ISP_RESOURCE_VFE_IN;
 
@@ -846,7 +848,7 @@ static int cam_vfe_bus_ver3_handle_rup_bottom_half(void *handler_priv,
 static int cam_vfe_bus_ver3_config_rdi_wm(
 	struct cam_vfe_bus_ver3_wm_resource_data  *rsrc_data)
 {
-	/* Force RDI to use PLAIN128 */
+
 	rsrc_data->pack_fmt = PACKER_FMT_VER3_PLAIN_128;
 	switch (rsrc_data->format) {
 	case CAM_FORMAT_MIPI_RAW_10:
@@ -860,6 +862,12 @@ static int cam_vfe_bus_ver3_config_rdi_wm(
 			rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE;
 			rsrc_data->en_cfg = (0x1 << 16) | 0x1;
 		}
+
+		if (rsrc_data->use_wm_pack) {
+			rsrc_data->pack_fmt = PACKER_FMT_VER3_MIPI10;
+			if (rsrc_data->default_line_based)
+				rsrc_data->width = ALIGNUP((rsrc_data->acquired_width), 16);
+		}
 		break;
 	case CAM_FORMAT_MIPI_RAW_6:
 		if (rsrc_data->default_line_based) {
@@ -897,6 +905,12 @@ static int cam_vfe_bus_ver3_config_rdi_wm(
 			rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE;
 			rsrc_data->en_cfg = (0x1 << 16) | 0x1;
 		}
+
+		if (rsrc_data->use_wm_pack) {
+			rsrc_data->pack_fmt = PACKER_FMT_VER3_MIPI12;
+			if (rsrc_data->default_line_based)
+				rsrc_data->width = ALIGNUP((rsrc_data->acquired_width), 16);
+		}
 		break;
 	case CAM_FORMAT_MIPI_RAW_14:
 		if (rsrc_data->default_line_based) {
@@ -909,6 +923,12 @@ static int cam_vfe_bus_ver3_config_rdi_wm(
 			rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE;
 			rsrc_data->en_cfg = (0x1 << 16) | 0x1;
 		}
+
+		if (rsrc_data->use_wm_pack) {
+			rsrc_data->pack_fmt = PACKER_FMT_VER3_MIPI14;
+			if (rsrc_data->default_line_based)
+				rsrc_data->width = ALIGNUP((rsrc_data->acquired_width), 16);
+		}
 		break;
 	case CAM_FORMAT_MIPI_RAW_16:
 		if (rsrc_data->default_line_based) {
@@ -933,6 +953,9 @@ static int cam_vfe_bus_ver3_config_rdi_wm(
 			rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE;
 			rsrc_data->en_cfg = (0x1 << 16) | 0x1;
 		}
+
+		if (rsrc_data->use_wm_pack)
+			rsrc_data->pack_fmt = PACKER_FMT_VER3_MIPI20;
 		break;
 	case CAM_FORMAT_PLAIN128:
 		if (rsrc_data->default_line_based) {
@@ -997,13 +1020,12 @@ static int cam_vfe_bus_ver3_config_rdi_wm(
 }
 
 static int cam_vfe_bus_ver3_acquire_wm(
-	struct cam_vfe_bus_ver3_priv          *ver3_bus_priv,
-	struct cam_isp_out_port_generic_info  *out_port_info,
-	void                                  *tasklet,
-	enum cam_vfe_bus_ver3_vfe_out_type     vfe_out_res_id,
-	enum cam_vfe_bus_plane_type            plane,
-	struct cam_isp_resource_node          *wm_res,
-	uint32_t                               is_dual,
+	struct cam_vfe_bus_ver3_priv           *ver3_bus_priv,
+	struct cam_vfe_hw_vfe_out_acquire_args *out_acq_args,
+	void                                   *tasklet,
+	enum cam_vfe_bus_ver3_vfe_out_type      vfe_out_res_id,
+	enum cam_vfe_bus_plane_type             plane,
+	struct cam_isp_resource_node           *wm_res,
 	enum cam_vfe_bus_ver3_comp_grp_type   *comp_grp_id)
 {
 	int32_t wm_idx = 0, rc;
@@ -1020,15 +1042,16 @@ static int cam_vfe_bus_ver3_acquire_wm(
 
 	rsrc_data = wm_res->res_priv;
 	wm_idx = rsrc_data->index;
-	rsrc_data->format = out_port_info->format;
+	rsrc_data->format = out_acq_args->out_port_info->format;
+	rsrc_data->use_wm_pack = out_acq_args->use_wm_pack;
 	rsrc_data->pack_fmt = cam_vfe_bus_ver3_get_packer_fmt(rsrc_data->format,
 		wm_idx);
 
-	rsrc_data->width = out_port_info->width;
-	rsrc_data->height = out_port_info->height;
-	rsrc_data->acquired_width = out_port_info->width;
-	rsrc_data->acquired_height = out_port_info->height;
-	rsrc_data->is_dual = is_dual;
+	rsrc_data->width = out_acq_args->out_port_info->width;
+	rsrc_data->height = out_acq_args->out_port_info->height;
+	rsrc_data->acquired_width = out_acq_args->out_port_info->width;
+	rsrc_data->acquired_height = out_acq_args->out_port_info->height;
+	rsrc_data->is_dual = out_acq_args->is_dual;
 	/* Set WM offset value to default */
 	rsrc_data->offset  = 0;
 	CAM_DBG(CAM_ISP, "WM:%d width %d height %d", rsrc_data->index,
@@ -2028,12 +2051,11 @@ static int cam_vfe_bus_ver3_acquire_vfe_out(void *bus_priv, void *acquire_args,
 	/* Acquire WM and retrieve COMP GRP ID */
 	for (i = 0; i < rsrc_data->num_wm; i++) {
 		rc = cam_vfe_bus_ver3_acquire_wm(ver3_bus_priv,
-			out_acquire_args->out_port_info,
+			out_acquire_args,
 			acq_args->tasklet,
 			vfe_out_res_id,
 			i,
 			&rsrc_data->wm_res[i],
-			out_acquire_args->is_dual,
 			&comp_acq_args.comp_grp_id);
 		if (rc) {
 			CAM_ERR(CAM_ISP,
@@ -2403,7 +2425,8 @@ static int cam_vfe_bus_ver3_handle_vfe_out_done_bottom_half(
 	struct cam_isp_resource_node          *vfe_out = handler_priv;
 	struct cam_vfe_bus_ver3_vfe_out_data  *rsrc_data = vfe_out->res_priv;
 	struct cam_vfe_bus_irq_evt_payload    *evt_payload = evt_payload_priv;
-	struct cam_isp_hw_compdone_event_info  evt_info = {0};
+	struct cam_isp_hw_event_info           evt_info;
+	struct cam_isp_hw_compdone_event_info  compdone_evt_info = {0};
 	void                                  *ctx = NULL;
 	uint32_t                               evt_id = 0;
 	uint64_t                               comp_mask = 0;
@@ -2439,14 +2462,15 @@ static int cam_vfe_bus_ver3_handle_vfe_out_done_bottom_half(
 			goto end;
 		}
 
-		evt_info.num_res = num_out;
+		compdone_evt_info.num_res = num_out;
 		for (i = 0; i < num_out; i++) {
-			evt_info.res_id[i] = out_list[i];
-			evt_info.last_consumed_addr[i] =
+			compdone_evt_info.res_id[i] = out_list[i];
+			compdone_evt_info.last_consumed_addr[i] =
 				cam_vfe_bus_ver3_get_last_consumed_addr(
 				rsrc_data->bus_priv,
-				evt_info.res_id[i]);
+				compdone_evt_info.res_id[i]);
 		}
+		evt_info.event_data = (void *)&compdone_evt_info;
 		if (rsrc_data->common_data->event_cb)
 			rsrc_data->common_data->event_cb(ctx, evt_id,
 				(void *)&evt_info);
@@ -2860,6 +2884,7 @@ static int cam_vfe_bus_ver3_err_irq_bottom_half(
 	struct cam_vfe_bus_ver3_priv *bus_priv = handler_priv;
 	struct cam_vfe_bus_ver3_common_data *common_data;
 	struct cam_isp_hw_event_info evt_info;
+	struct cam_isp_hw_error_event_info err_evt_info;
 	uint32_t status = 0, image_size_violation = 0, ccif_violation = 0, constraint_violation = 0;
 
 	if (!handler_priv || !evt_payload_priv)
@@ -2901,8 +2926,9 @@ static int cam_vfe_bus_ver3_err_irq_bottom_half(
 	evt_info.hw_idx = common_data->core_index;
 	evt_info.res_type = CAM_ISP_RESOURCE_VFE_OUT;
 	evt_info.res_id = CAM_VFE_BUS_VER3_VFE_OUT_MAX;
-	evt_info.err_type = CAM_VFE_IRQ_STATUS_VIOLATION;
 	evt_info.hw_type = CAM_ISP_HW_TYPE_VFE;
+	err_evt_info.err_type = CAM_VFE_IRQ_STATUS_VIOLATION;
+	evt_info.event_data = (void *)&err_evt_info;
 
 	if (common_data->event_cb)
 		common_data->event_cb(common_data->priv, CAM_ISP_HW_EVENT_ERROR,
@@ -3138,9 +3164,8 @@ static int cam_vfe_bus_ver3_update_wm(void *priv, void *cmd_args,
 	struct cam_cdm_utils_ops                       *cdm_util_ops;
 	uint32_t *reg_val_pair;
 	uint32_t num_regval_pairs = 0;
-	uint32_t i, j, k, size = 0;
+	uint32_t i, j, size = 0;
 	uint32_t frame_inc = 0, val;
-	uint32_t loop_size = 0;
 	uint32_t iova_addr, iova_offset, image_buf_offset = 0;
 	dma_addr_t iova;
 
@@ -3284,12 +3309,6 @@ static int cam_vfe_bus_ver3_update_wm(void *priv, void *cmd_args,
 				wm_data->index, reg_val_pair[j-1]);
 		}
 
-		if ((!bus_priv->common_data.is_lite && wm_data->index > 22) ||
-			bus_priv->common_data.is_lite)
-			loop_size = wm_data->irq_subsample_period + 1;
-		else
-			loop_size = 1;
-
 		if (wm_data->en_ubwc)
 			image_buf_offset = io_cfg->planes[i].meta_size;
 		else if (wm_data->en_cfg & (0x3 << 16))
@@ -3298,31 +3317,29 @@ static int cam_vfe_bus_ver3_update_wm(void *priv, void *cmd_args,
 			image_buf_offset = 0;
 
 		/* WM Image address */
-		for (k = 0; k < loop_size; k++) {
-			iova = update_buf->wm_update->image_buf[i] +
-				image_buf_offset + (k * frame_inc);
+		iova = update_buf->wm_update->image_buf[i] +
+			image_buf_offset;
 
-			if (cam_smmu_is_expanded_memory()) {
-				iova_addr = CAM_36BIT_INTF_GET_IOVA_BASE(iova);
-				iova_offset = CAM_36BIT_INTF_GET_IOVA_OFFSET(iova);
+		if (cam_smmu_is_expanded_memory()) {
+			iova_addr = CAM_36BIT_INTF_GET_IOVA_BASE(iova);
+			iova_offset = CAM_36BIT_INTF_GET_IOVA_OFFSET(iova);
 
-				CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j,
-					wm_data->hw_regs->image_addr, iova_addr);
+			CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j,
+				wm_data->hw_regs->image_addr, iova_addr);
 
-				CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j,
-					wm_data->hw_regs->addr_cfg, iova_offset);
+			CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j,
+				wm_data->hw_regs->addr_cfg, iova_offset);
 
-				CAM_DBG(CAM_ISP, "WM:%d image address 0x%X 0x%X",
-					wm_data->index, reg_val_pair[j-2], reg_val_pair[j-1]);
-			} else {
-				iova_addr = iova;
+			CAM_DBG(CAM_ISP, "WM:%d image address 0x%X 0x%X",
+				wm_data->index, reg_val_pair[j-2], reg_val_pair[j-1]);
+		} else {
+			iova_addr = iova;
 
-				CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j,
-					wm_data->hw_regs->image_addr, iova_addr);
+			CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j,
+				wm_data->hw_regs->image_addr, iova_addr);
 
-				CAM_DBG(CAM_ISP, "WM:%d image address 0x%X",
-					wm_data->index, reg_val_pair[j-1]);
-			}
+			CAM_DBG(CAM_ISP, "WM:%d image address 0x%X",
+				wm_data->index, reg_val_pair[j-1]);
 		}
 
 		update_buf->wm_update->image_buf_offset[i] = image_buf_offset;

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c

@@ -496,6 +496,7 @@ static int cam_vfe_camif_lite_handle_irq_bottom_half(
 	uint32_t                              irq_status1;
 	struct cam_hw_soc_info               *soc_info = NULL;
 	struct cam_vfe_soc_private           *soc_private = NULL;
+	struct cam_isp_hw_error_event_info    err_evt_info;
 	struct timespec64                     ts;
 
 	if (!handler_priv || !evt_payload_priv) {
@@ -512,6 +513,7 @@ static int cam_vfe_camif_lite_handle_irq_bottom_half(
 	soc_private =
 		(struct cam_vfe_soc_private *)soc_info->soc_private;
 
+	evt_info.hw_type  = CAM_ISP_HW_TYPE_VFE;
 	evt_info.hw_idx   = camif_lite_node->hw_intf->hw_idx;
 	evt_info.res_id   = camif_lite_node->res_id;
 	evt_info.res_type = camif_lite_node->res_type;
@@ -548,6 +550,8 @@ static int cam_vfe_camif_lite_handle_irq_bottom_half(
 		CAM_DBG(CAM_ISP, "VFE:%d CAMIF LITE Received ERROR",
 			evt_info.hw_idx);
 
+		err_evt_info.err_type = CAM_VFE_IRQ_STATUS_OVERFLOW;
+		evt_info.event_data = (void *)&err_evt_info;
 		cam_vfe_camif_lite_cpas_fifo_levels_reg_dump(camif_lite_priv);
 
 		ktime_get_boottime_ts64(&ts);

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver3.c

@@ -1076,6 +1076,7 @@ static int cam_vfe_camif_lite_handle_irq_bottom_half(
 	struct cam_vfe_mux_camif_lite_data *camif_lite_priv;
 	struct cam_vfe_top_irq_evt_payload *payload;
 	struct cam_isp_hw_event_info evt_info;
+	struct cam_isp_hw_error_event_info err_evt_info;
 	struct cam_vfe_soc_private *soc_private = NULL;
 	uint32_t irq_status[CAM_IFE_IRQ_REGISTERS_MAX] = {0};
 	int i = 0;
@@ -1100,9 +1101,11 @@ static int cam_vfe_camif_lite_handle_irq_bottom_half(
 	for (i = 0; i < CAM_IFE_IRQ_REGISTERS_MAX; i++)
 		irq_status[i] = payload->irq_reg_val[i];
 
+	evt_info.hw_type  = CAM_ISP_HW_TYPE_VFE;
 	evt_info.hw_idx   = camif_lite_node->hw_intf->hw_idx;
 	evt_info.res_id   = camif_lite_node->res_id;
 	evt_info.res_type = camif_lite_node->res_type;
+	evt_info.hw_type  = CAM_ISP_HW_TYPE_VFE;
 
 	CAM_DBG(CAM_ISP,
 		"VFE:%d CAMIF LITE:%d %s IRQ status_0: 0x%X status_1: 0x%X status_2: 0x%X",
@@ -1165,7 +1168,8 @@ static int cam_vfe_camif_lite_handle_irq_bottom_half(
 		CAM_ERR(CAM_ISP, "VFE:%d Overflow",
 			camif_lite_node->hw_intf->hw_idx);
 
-		evt_info.err_type = CAM_VFE_IRQ_STATUS_OVERFLOW;
+		err_evt_info.err_type = CAM_VFE_IRQ_STATUS_OVERFLOW;
+		evt_info.event_data = (void *)&err_evt_info;
 		ktime_get_boottime_ts64(&ts);
 		CAM_INFO(CAM_ISP,
 			"current monotonic time stamp seconds %lld:%lld",
@@ -1214,7 +1218,8 @@ static int cam_vfe_camif_lite_handle_irq_bottom_half(
 		CAM_ERR(CAM_ISP, "VFE:%d Violation",
 			camif_lite_node->hw_intf->hw_idx);
 
-		evt_info.err_type = CAM_VFE_IRQ_STATUS_VIOLATION;
+		err_evt_info.err_type = CAM_VFE_IRQ_STATUS_VIOLATION;
+		evt_info.event_data = (void *)&err_evt_info;
 
 		if (camif_lite_priv->event_cb)
 			camif_lite_priv->event_cb(camif_lite_priv->priv,

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c

@@ -790,6 +790,7 @@ static int cam_vfe_camif_handle_irq_bottom_half(void *handler_priv,
 	uint32_t                              irq_status0;
 	uint32_t                              irq_status1;
 	uint32_t                              val;
+	struct cam_isp_hw_error_event_info    err_evt_info;
 	struct timespec64                     ts;
 
 	if (!handler_priv || !evt_payload_priv) {
@@ -806,6 +807,7 @@ static int cam_vfe_camif_handle_irq_bottom_half(void *handler_priv,
 	soc_info = camif_priv->soc_info;
 	soc_private = (struct cam_vfe_soc_private *)soc_info->soc_private;
 
+	evt_info.hw_type  = CAM_ISP_HW_TYPE_VFE;
 	evt_info.hw_idx   = camif_node->hw_intf->hw_idx;
 	evt_info.res_id   = camif_node->res_id;
 	evt_info.res_type = camif_node->res_type;
@@ -882,6 +884,8 @@ static int cam_vfe_camif_handle_irq_bottom_half(void *handler_priv,
 	if (irq_status0 & camif_priv->reg_data->error_irq_mask0) {
 		CAM_DBG(CAM_ISP, "Received ERROR");
 
+		err_evt_info.err_type = CAM_VFE_IRQ_STATUS_OVERFLOW;
+		evt_info.event_data = (void *)&err_evt_info;
 		ktime_get_boottime_ts64(&ts);
 		CAM_INFO(CAM_ISP,
 			"current monotonic time stamp seconds %lld:%lld",
@@ -908,6 +912,8 @@ static int cam_vfe_camif_handle_irq_bottom_half(void *handler_priv,
 	if (irq_status1 & camif_priv->reg_data->error_irq_mask1) {
 		CAM_DBG(CAM_ISP, "Received ERROR");
 
+		err_evt_info.err_type = CAM_VFE_IRQ_STATUS_OVERFLOW;
+		evt_info.event_data = (void *)&err_evt_info;
 		ktime_get_boottime_ts64(&ts);
 		CAM_INFO(CAM_ISP,
 			"current monotonic time stamp seconds %lld:%lld",

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c

@@ -474,6 +474,7 @@ static int cam_vfe_camif_ver3_resource_start(
 	switch (soc_private->cpas_version) {
 	case CAM_CPAS_TITAN_480_V100:
 	case CAM_CPAS_TITAN_580_V100:
+	case CAM_CPAS_TITAN_570_V100:
 	case CAM_CPAS_TITAN_570_V200:
 		epoch0_line_cfg = ((rsrc_data->last_line +
 			rsrc_data->vbi_value) -
@@ -1360,6 +1361,7 @@ static int cam_vfe_camif_ver3_handle_irq_bottom_half(void *handler_priv,
 	struct cam_vfe_mux_camif_ver3_data *camif_priv;
 	struct cam_vfe_top_irq_evt_payload *payload;
 	struct cam_isp_hw_event_info evt_info;
+	struct cam_isp_hw_error_event_info err_evt_info;
 	struct cam_hw_soc_info *soc_info = NULL;
 	struct cam_vfe_soc_private *soc_private = NULL;
 	uint32_t irq_status[CAM_IFE_IRQ_REGISTERS_MAX] = {0};
@@ -1385,10 +1387,12 @@ static int cam_vfe_camif_ver3_handle_irq_bottom_half(void *handler_priv,
 	for (i = 0; i < CAM_IFE_IRQ_REGISTERS_MAX; i++)
 		irq_status[i] = payload->irq_reg_val[i];
 
+	evt_info.hw_type  = CAM_ISP_HW_TYPE_VFE;
 	evt_info.hw_idx   = camif_node->hw_intf->hw_idx;
 	evt_info.res_id   = camif_node->res_id;
 	evt_info.res_type = camif_node->res_type;
 	evt_info.reg_val = 0;
+	evt_info.hw_type = CAM_ISP_HW_TYPE_VFE;
 
 	if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1]
 		& camif_priv->reg_data->sof_irq_mask) {
@@ -1468,7 +1472,8 @@ static int cam_vfe_camif_ver3_handle_irq_bottom_half(void *handler_priv,
 			ts.tv_sec, ts.tv_nsec);
 
 		ret = CAM_VFE_IRQ_STATUS_OVERFLOW;
-		evt_info.err_type = CAM_VFE_IRQ_STATUS_OVERFLOW;
+		err_evt_info.err_type = CAM_VFE_IRQ_STATUS_OVERFLOW;
+		evt_info.event_data = (void *)&err_evt_info;
 
 		CAM_INFO(CAM_ISP, "ife_clk_src:%lld",
 			soc_private->ife_clk_src);
@@ -1501,7 +1506,8 @@ static int cam_vfe_camif_ver3_handle_irq_bottom_half(void *handler_priv,
 			ts.tv_sec, ts.tv_nsec);
 
 		ret = CAM_VFE_IRQ_STATUS_VIOLATION;
-		evt_info.err_type = CAM_VFE_IRQ_STATUS_VIOLATION;
+		err_evt_info.err_type = CAM_VFE_IRQ_STATUS_VIOLATION;
+		evt_info.event_data = (void *)&err_evt_info;
 
 		CAM_INFO(CAM_ISP, "ife_clk_src:%lld",
 			soc_private->ife_clk_src);

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_fe_ver1.c

@@ -516,7 +516,6 @@ static int cam_vfe_fe_handle_irq_bottom_half(void *handler_priv,
 	struct cam_isp_resource_node         *fe_node;
 	struct cam_vfe_mux_fe_data           *fe_priv;
 	struct cam_vfe_top_irq_evt_payload   *payload;
-	struct cam_isp_hw_event_info          evt_info;
 	uint32_t                              irq_status0;
 	uint32_t                              irq_status1;
 
@@ -531,10 +530,6 @@ static int cam_vfe_fe_handle_irq_bottom_half(void *handler_priv,
 	irq_status0 = payload->irq_reg_val[CAM_IFE_IRQ_CAMIF_REG_STATUS0];
 	irq_status1 = payload->irq_reg_val[CAM_IFE_IRQ_CAMIF_REG_STATUS1];
 
-	evt_info.hw_idx = fe_node->hw_intf->hw_idx;
-	evt_info.res_id = fe_node->res_id;
-	evt_info.res_type = fe_node->res_type;
-
 	CAM_DBG(CAM_ISP, "event ID, irq_status_0 = 0x%x", irq_status0);
 
 	if (irq_status0 & fe_priv->reg_data->sof_irq_mask) {
@@ -574,8 +569,8 @@ static int cam_vfe_fe_handle_irq_bottom_half(void *handler_priv,
 	if (irq_status1 & fe_priv->reg_data->error_irq_mask1) {
 		CAM_DBG(CAM_ISP, "Received ERROR");
 		ret = CAM_ISP_HW_ERROR_OVERFLOW;
-		evt_info.err_type = CAM_VFE_IRQ_STATUS_OVERFLOW;
 		cam_vfe_fe_reg_dump(fe_node);
+		/* No HW mgr notification on error */
 	} else {
 		ret = CAM_ISP_HW_ERROR_NONE;
 	}

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c

@@ -473,6 +473,7 @@ static int cam_vfe_rdi_handle_irq_bottom_half(void *handler_priv,
 	struct cam_vfe_mux_rdi_data         *rdi_priv;
 	struct cam_vfe_top_irq_evt_payload  *payload;
 	struct cam_isp_hw_event_info         evt_info;
+	struct cam_isp_hw_error_event_info	 err_evt_info;
 	uint32_t                             irq_status0;
 	uint32_t                             irq_status1;
 	uint32_t                             irq_rdi_status;
@@ -495,6 +496,7 @@ static int cam_vfe_rdi_handle_irq_bottom_half(void *handler_priv,
 	irq_status0 = payload->irq_reg_val[CAM_IFE_IRQ_CAMIF_REG_STATUS0];
 	irq_status1 = payload->irq_reg_val[CAM_IFE_IRQ_CAMIF_REG_STATUS1];
 
+	evt_info.hw_type  = CAM_ISP_HW_TYPE_VFE;
 	evt_info.hw_idx   = rdi_node->hw_intf->hw_idx;
 	evt_info.res_id   = rdi_node->res_id;
 	evt_info.res_type = rdi_node->res_type;
@@ -564,6 +566,8 @@ static int cam_vfe_rdi_handle_irq_bottom_half(void *handler_priv,
 			evt_info.res_id = CAM_ISP_IFE_OUT_RES_RDI_3;
 			}
 
+		err_evt_info.err_type = CAM_VFE_IRQ_STATUS_OVERFLOW;
+		evt_info.event_data = (void *)&err_evt_info;
 		if (rdi_priv->event_cb)
 			rdi_priv->event_cb(rdi_priv->priv,
 			CAM_ISP_HW_EVENT_ERROR,

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.c

@@ -26,11 +26,12 @@ static int cam_vfe_top_set_axi_bw_vote(struct cam_vfe_top_priv_common *top_commo
 	int rc = 0;
 	struct cam_hw_soc_info        *soc_info = NULL;
 	struct cam_vfe_soc_private    *soc_private = NULL;
+	int i, j;
 
 	soc_info = top_common->soc_info;
 	soc_private = (struct cam_vfe_soc_private *)soc_info->soc_private;
 
-	CAM_DBG(CAM_PERF, "VFE:%d Sending final BW to cpas bw_state:%s bw_vote:%llu req_id:%d",
+	CAM_DBG(CAM_PERF, "VFE:%d Sending final BW to cpas bw_state:%s bw_vote:%llu req_id:%ld",
 		top_common->hw_idx, cam_vfe_top_clk_bw_state_to_string(top_common->bw_state),
 		total_bw_new_vote, (start_stop ? -1 : request_id));
 	rc = cam_cpas_update_axi_vote(soc_private->cpas_handle,
@@ -41,7 +42,37 @@ static int cam_vfe_top_set_axi_bw_vote(struct cam_vfe_top_priv_common *top_commo
 			sizeof(struct cam_axi_vote));
 		top_common->total_bw_applied = total_bw_new_vote;
 	} else {
-		CAM_ERR(CAM_PERF, "BW request failed, rc=%d", rc);
+		CAM_ERR(CAM_PERF,
+			"VFE:%d BW request failed, req_id: %ld, final num_paths: %d, rc=%d",
+			top_common->hw_idx, (start_stop ? -1 : request_id),
+			final_bw_vote->num_paths, rc);
+		for (i = 0; i < final_bw_vote->num_paths; i++) {
+			CAM_INFO(CAM_PERF,
+				"ife[%d] : Applied BW Vote : [%s][%s] [%llu %llu %llu]",
+				top_common->hw_idx,
+				cam_cpas_axi_util_path_type_to_string(
+				final_bw_vote->axi_path[i].path_data_type),
+				cam_cpas_axi_util_trans_type_to_string(
+				final_bw_vote->axi_path[i].transac_type),
+				final_bw_vote->axi_path[i].camnoc_bw,
+				final_bw_vote->axi_path[i].mnoc_ab_bw,
+				final_bw_vote->axi_path[i].mnoc_ib_bw);
+		}
+
+		for (i = 0; i < CAM_DELAY_CLK_BW_REDUCTION_NUM_REQ; i++) {
+			for (j = 0; j < top_common->last_bw_vote[i].num_paths; j++) {
+				CAM_INFO(CAM_PERF,
+					"ife[%d] : History[%d] BW Vote : [%s][%s] [%llu %llu %llu]",
+					top_common->hw_idx, i,
+					cam_cpas_axi_util_path_type_to_string(
+					top_common->last_bw_vote[i].axi_path[j].path_data_type),
+					cam_cpas_axi_util_trans_type_to_string(
+					top_common->last_bw_vote[i].axi_path[j].transac_type),
+					top_common->last_bw_vote[i].axi_path[j].camnoc_bw,
+					top_common->last_bw_vote[i].axi_path[j].mnoc_ab_bw,
+					top_common->last_bw_vote[i].axi_path[j].mnoc_ib_bw);
+			}
+		}
 	}
 
 	return rc;
@@ -59,7 +90,7 @@ static int cam_vfe_top_set_hw_clk_rate(struct cam_vfe_top_priv_common *top_commo
 	soc_info = top_common->soc_info;
 	soc_private = (struct cam_vfe_soc_private *)soc_info->soc_private;
 
-	CAM_DBG(CAM_PERF, "Applying VFE:%d Clock name=%s idx=%d clk=%llu req_id=%d",
+	CAM_DBG(CAM_PERF, "Applying VFE:%d Clock name=%s idx=%d clk=%llu req_id=%ld",
 		top_common->hw_idx, soc_info->clk_name[soc_info->src_clk_idx],
 		soc_info->src_clk_idx, final_clk_rate, (start_stop ? -1 : request_id));
 
@@ -115,7 +146,7 @@ static int cam_vfe_top_calc_hw_clk_rate(
 			max_req_clk_rate = top_common->req_clk_rate[i];
 	}
 
-	if (start_stop) {
+	if (start_stop && !top_common->skip_data_rst_on_stop) {
 		/* need to vote current clk immediately */
 		*final_clk_rate = max_req_clk_rate;
 		/* Reset everything, we can start afresh */
@@ -148,7 +179,7 @@ static int cam_vfe_top_calc_hw_clk_rate(
 	else
 		top_common->clk_state = CAM_CLK_BW_STATE_DECREASE;
 
-	CAM_DBG(CAM_PERF, "VFE:%d Clock state:%s applied_clk_rate:%llu req_id:%d",
+	CAM_DBG(CAM_PERF, "VFE:%d Clock state:%s applied_clk_rate:%llu req_id:%ld",
 		top_common->hw_idx, cam_vfe_top_clk_bw_state_to_string(top_common->clk_state),
 		top_common->applied_clk_rate, (start_stop ? -1 : request_id));
 
@@ -220,7 +251,6 @@ static int cam_vfe_top_calc_axi_bw_vote(
 	struct cam_axi_vote **to_be_applied_axi_vote, uint64_t *total_bw_new_vote,
 	uint64_t request_id)
 {
-	static struct cam_axi_vote agg_vote;
 	int rc = 0;
 	uint32_t i;
 	uint32_t num_paths = 0;
@@ -234,7 +264,7 @@ static int cam_vfe_top_calc_axi_bw_vote(
 		return -EINVAL;
 	}
 
-	memset(&agg_vote, 0, sizeof(struct cam_axi_vote));
+	memset(&top_common->agg_incoming_vote, 0, sizeof(struct cam_axi_vote));
 	for (i = 0; i < top_common->num_mux; i++) {
 		if (top_common->axi_vote_control[i] ==
 			CAM_ISP_BW_CONTROL_INCLUDE) {
@@ -250,7 +280,7 @@ static int cam_vfe_top_calc_axi_bw_vote(
 				goto end;
 			}
 
-			memcpy(&agg_vote.axi_path[num_paths],
+			memcpy(&top_common->agg_incoming_vote.axi_path[num_paths],
 				&top_common->req_axi_vote[i].axi_path[0],
 				top_common->req_axi_vote[i].num_paths *
 				sizeof(
@@ -259,26 +289,26 @@ static int cam_vfe_top_calc_axi_bw_vote(
 		}
 	}
 
-	agg_vote.num_paths = num_paths;
+	top_common->agg_incoming_vote.num_paths = num_paths;
 
-	for (i = 0; i < agg_vote.num_paths; i++) {
+	for (i = 0; i < top_common->agg_incoming_vote.num_paths; i++) {
 		CAM_DBG(CAM_PERF,
 			"ife[%d] : New BW Vote : counter[%d] [%s][%s] [%llu %llu %llu]",
 			top_common->hw_idx,
 			top_common->last_bw_counter,
 			cam_cpas_axi_util_path_type_to_string(
-			agg_vote.axi_path[i].path_data_type),
+			top_common->agg_incoming_vote.axi_path[i].path_data_type),
 			cam_cpas_axi_util_trans_type_to_string(
-			agg_vote.axi_path[i].transac_type),
-			agg_vote.axi_path[i].camnoc_bw,
-			agg_vote.axi_path[i].mnoc_ab_bw,
-			agg_vote.axi_path[i].mnoc_ib_bw);
+			top_common->agg_incoming_vote.axi_path[i].transac_type),
+			top_common->agg_incoming_vote.axi_path[i].camnoc_bw,
+			top_common->agg_incoming_vote.axi_path[i].mnoc_ab_bw,
+			top_common->agg_incoming_vote.axi_path[i].mnoc_ib_bw);
 
-		*total_bw_new_vote += agg_vote.axi_path[i].camnoc_bw;
+		*total_bw_new_vote += top_common->agg_incoming_vote.axi_path[i].camnoc_bw;
 	}
 
-	memcpy(&top_common->last_bw_vote[top_common->last_bw_counter], &agg_vote,
-		sizeof(struct cam_axi_vote));
+	memcpy(&top_common->last_bw_vote[top_common->last_bw_counter],
+		&top_common->agg_incoming_vote, sizeof(struct cam_axi_vote));
 	top_common->last_total_bw_vote[top_common->last_bw_counter] = *total_bw_new_vote;
 	top_common->last_bw_counter = (top_common->last_bw_counter + 1) %
 		CAM_DELAY_CLK_BW_REDUCTION_NUM_REQ;
@@ -287,7 +317,7 @@ static int cam_vfe_top_calc_axi_bw_vote(
 		bw_unchanged = false;
 
 	CAM_DBG(CAM_PERF,
-		"ife[%d] : applied_total=%lld, new_total=%lld unchanged=%d, start_stop=%d req_id=%d",
+		"ife[%d] : applied_total=%lld, new_total=%lld unchanged=%d, start_stop=%d req_id=%ld",
 		top_common->hw_idx, top_common->total_bw_applied,
 		*total_bw_new_vote, bw_unchanged, start_stop, (start_stop ? -1 : request_id));
 
@@ -300,14 +330,15 @@ static int cam_vfe_top_calc_axi_bw_vote(
 
 	if (start_stop) {
 		/* need to vote current request immediately */
-		final_bw_vote = &agg_vote;
+		final_bw_vote = &top_common->agg_incoming_vote;
 		/* Reset everything, we can start afresh */
 		memset(top_common->last_bw_vote, 0, sizeof(struct cam_axi_vote) *
 			CAM_DELAY_CLK_BW_REDUCTION_NUM_REQ);
 		memset(top_common->last_total_bw_vote, 0, sizeof(uint64_t) *
 			CAM_DELAY_CLK_BW_REDUCTION_NUM_REQ);
 		top_common->last_bw_counter = 0;
-		top_common->last_bw_vote[top_common->last_bw_counter] = agg_vote;
+		top_common->last_bw_vote[top_common->last_bw_counter] =
+			top_common->agg_incoming_vote;
 		top_common->last_total_bw_vote[top_common->last_bw_counter] = *total_bw_new_vote;
 		top_common->last_bw_counter = (top_common->last_bw_counter + 1) %
 			CAM_DELAY_CLK_BW_REDUCTION_NUM_REQ;
@@ -351,7 +382,7 @@ static int cam_vfe_top_calc_axi_bw_vote(
 	}
 
 	CAM_DBG(CAM_PERF,
-		"ife[%d] : Delayed update: applied_total=%lld new_total=%lld start_stop=%d bw_state=%s req_id=%d",
+		"ife[%d] : Delayed update: applied_total=%lld new_total=%lld start_stop=%d bw_state=%s req_id=%ld",
 		top_common->hw_idx, top_common->total_bw_applied,
 		*total_bw_new_vote, start_stop,
 		cam_vfe_top_clk_bw_state_to_string(top_common->bw_state),
@@ -566,6 +597,12 @@ int cam_vfe_top_apply_clk_bw_update(struct cam_vfe_top_priv_common *top_common,
 		goto end;
 	}
 
+	if (clk_bw_args->skip_clk_data_rst) {
+		top_common->skip_data_rst_on_stop = true;
+		CAM_DBG(CAM_ISP, "VFE:%u requested to avoid clk data rst", hw_intf->hw_idx);
+		return 0;
+	}
+
 	rc = cam_vfe_top_calc_hw_clk_rate(top_common, false, &final_clk_rate, request_id);
 	if (rc) {
 		CAM_ERR(CAM_ISP,
@@ -589,7 +626,7 @@ int cam_vfe_top_apply_clk_bw_update(struct cam_vfe_top_priv_common *top_common,
 		goto end;
 	}
 
-	CAM_DBG(CAM_PERF, "VFE:%d APPLY CLK/BW req_id:%d clk_state:%s bw_state:%s ",
+	CAM_DBG(CAM_PERF, "VFE:%d APPLY CLK/BW req_id:%ld clk_state:%s bw_state:%s ",
 		hw_intf->hw_idx, request_id,
 		cam_vfe_top_clk_bw_state_to_string(top_common->clk_state),
 		cam_vfe_top_clk_bw_state_to_string(top_common->bw_state));
@@ -703,6 +740,7 @@ int cam_vfe_top_apply_clock_start_stop(struct cam_vfe_top_priv_common *top_commo
 
 end:
 	top_common->clk_state = CAM_CLK_BW_STATE_INIT;
+	top_common->skip_data_rst_on_stop = false;
 	return rc;
 }
 

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.h

@@ -21,6 +21,7 @@ struct cam_vfe_top_priv_common {
 	uint32_t                        num_mux;
 	uint32_t                        hw_idx;
 	struct cam_axi_vote             applied_axi_vote;
+	struct cam_axi_vote             agg_incoming_vote;
 	struct cam_axi_vote             req_axi_vote[CAM_VFE_TOP_MUX_MAX];
 	struct cam_axi_vote             last_bw_vote[CAM_DELAY_CLK_BW_REDUCTION_NUM_REQ];
 	uint64_t                        last_total_bw_vote[CAM_DELAY_CLK_BW_REDUCTION_NUM_REQ];
@@ -35,6 +36,7 @@ struct cam_vfe_top_priv_common {
 	struct cam_hw_soc_info         *soc_info;
 	unsigned long                   applied_clk_rate;
 	unsigned long                   req_clk_rate[CAM_VFE_TOP_MUX_MAX];
+	bool                            skip_data_rst_on_stop;
 
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c

@@ -99,6 +99,82 @@ static int cam_vfe_top_ver4_get_path_port_map(struct cam_vfe_top_ver4_priv *top_
 	return 0;
 }
 
+static int cam_vfe_top_ver4_pdaf_lcr_config(struct cam_vfe_top_ver4_priv *top_priv,
+	void *cmd_args, uint32_t arg_size)
+{
+	struct cam_vfe_top_ver4_hw_info  *hw_info;
+	struct cam_isp_hw_get_cmd_update *cdm_args = NULL;
+	struct cam_cdm_utils_ops         *cdm_util_ops = NULL;
+	uint32_t                          i;
+	uint32_t                          reg_val_idx = 0;
+	uint32_t                          num_reg_vals;
+	uint32_t                          reg_val_pair[4];
+	struct cam_isp_lcr_rdi_cfg_args  *cfg_args;
+	size_t                            size;
+
+	if (!cmd_args || !top_priv) {
+		CAM_ERR(CAM_ISP, "Error, Invalid args");
+		return -EINVAL;
+	}
+
+	cdm_args = (struct cam_isp_hw_get_cmd_update *)cmd_args;
+	if (!cdm_args->res) {
+		CAM_ERR(CAM_ISP, "Error, Invalid res");
+		return -EINVAL;
+	}
+
+	hw_info = top_priv->common_data.hw_info;
+	if (!hw_info->num_pdaf_lcr_res || !hw_info->pdaf_lcr_res_mask) {
+		CAM_DBG(CAM_ISP, "PDAF LCR is not supported");
+		return 0;
+	}
+
+	cfg_args = (struct cam_isp_lcr_rdi_cfg_args *)cdm_args->data;
+	cdm_util_ops =
+		(struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops;
+	if (!cdm_util_ops) {
+		CAM_ERR(CAM_ISP, "Invalid CDM ops");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < hw_info->num_pdaf_lcr_res; i++)
+		if (cdm_args->res->res_id ==
+			hw_info->pdaf_lcr_res_mask[i].res_id)
+			break;
+
+	if (i == hw_info->num_pdaf_lcr_res) {
+		CAM_ERR(CAM_ISP, "Res :%d is not supported for mux",
+			cfg_args->rdi_lcr_cfg->res_id);
+		return -EINVAL;
+	}
+
+	if (cfg_args->is_init)
+		num_reg_vals = 2;
+	else
+		num_reg_vals = 1;
+
+	size = cdm_util_ops->cdm_required_size_reg_random(num_reg_vals);
+	/* since cdm returns dwords, we need to convert it into bytes */
+	if ((size * 4) > cdm_args->cmd.size) {
+		CAM_ERR(CAM_ISP, "buf size:%d is not sufficient, expected: %d",
+			cdm_args->cmd.size, (size*4));
+		return -EINVAL;
+	}
+
+	if (cfg_args->is_init) {
+		reg_val_pair[reg_val_idx++] = hw_info->common_reg->pdaf_input_cfg_1;
+		reg_val_pair[reg_val_idx++] = 0;
+	}
+
+	reg_val_pair[reg_val_idx++] = hw_info->common_reg->pdaf_input_cfg_0;
+	reg_val_pair[reg_val_idx++] = hw_info->pdaf_lcr_res_mask[i].val;
+	cdm_util_ops->cdm_write_regrandom(cdm_args->cmd.cmd_buf_addr,
+		num_reg_vals, reg_val_pair);
+	cdm_args->cmd.used_bytes = size * 4;
+
+	return 0;
+}
+
 static int cam_vfe_top_ver4_mux_get_base(struct cam_vfe_top_ver4_priv *top_priv,
 	void *cmd_args, uint32_t arg_size)
 {
@@ -106,6 +182,7 @@ static int cam_vfe_top_ver4_mux_get_base(struct cam_vfe_top_ver4_priv *top_priv,
 	uint32_t                          mem_base = 0;
 	struct cam_isp_hw_get_cmd_update *cdm_args  = cmd_args;
 	struct cam_cdm_utils_ops         *cdm_util_ops = NULL;
+	struct cam_vfe_soc_private       *soc_private;
 
 	if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) {
 		CAM_ERR(CAM_ISP, "Error, Invalid cmd size");
@@ -118,6 +195,12 @@ static int cam_vfe_top_ver4_mux_get_base(struct cam_vfe_top_ver4_priv *top_priv,
 		return -EINVAL;
 	}
 
+	soc_private = top_priv->top_common.soc_info->soc_private;
+	if (!soc_private) {
+		CAM_ERR(CAM_ISP, "soc_private is null");
+		return -EINVAL;
+	}
+
 	cdm_util_ops =
 		(struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops;
 
@@ -136,16 +219,20 @@ static int cam_vfe_top_ver4_mux_get_base(struct cam_vfe_top_ver4_priv *top_priv,
 
 	mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE(
 		top_priv->top_common.soc_info, VFE_CORE_BASE_IDX);
-	if (cdm_args->cdm_id == CAM_CDM_RT)
-		mem_base -= CAM_SOC_GET_REG_MAP_CAM_BASE(
-			top_priv->top_common.soc_info, RT_BASE_IDX);
+	if (cdm_args->cdm_id == CAM_CDM_RT) {
+		if (!soc_private->rt_wrapper_base) {
+			CAM_ERR(CAM_ISP, "rt_wrapper_base_addr is null");
+			return -EINVAL;
+		}
+
+		mem_base -= soc_private->rt_wrapper_base;
+	}
 
 	CAM_DBG(CAM_ISP, "core %d mem_base 0x%x, cdm_id: %u",
 		top_priv->top_common.soc_info->index, mem_base,
 		cdm_args->cdm_id);
 
-	cdm_util_ops->cdm_write_changebase(
-		cdm_args->cmd.cmd_buf_addr, mem_base);
+	cdm_util_ops->cdm_write_changebase(cdm_args->cmd.cmd_buf_addr, mem_base);
 	cdm_args->cmd.used_bytes = (size * 4);
 
 	return 0;
@@ -788,7 +875,8 @@ int cam_vfe_top_ver4_stop(void *device_priv,
 		for (i = 0; i < top_priv->top_common.num_mux; i++) {
 			if (top_priv->top_common.mux_rsrc[i].res_id ==
 				mux_res->res_id) {
-				top_priv->top_common.req_clk_rate[i] = 0;
+				if (!top_priv->top_common.skip_data_rst_on_stop)
+					top_priv->top_common.req_clk_rate[i] = 0;
 				memset(&top_priv->top_common.req_axi_vote[i],
 					0, sizeof(struct cam_axi_vote));
 				top_priv->top_common.axi_vote_control[i] =
@@ -886,6 +974,10 @@ int cam_vfe_top_ver4_process_cmd(void *device_priv, uint32_t cmd_type,
 	case CAM_ISP_HW_CMD_INIT_CONFIG_UPDATE:
 		rc = cam_vfe_init_config_update(cmd_args, arg_size);
 		break;
+	case CAM_ISP_HW_CMD_RDI_LCR_CFG:
+		rc = cam_vfe_top_ver4_pdaf_lcr_config(top_priv, cmd_args,
+			arg_size);
+		break;
 	default:
 		rc = -EINVAL;
 		CAM_ERR(CAM_ISP, "Error, Invalid cmd:%d", cmd_type);
@@ -1008,6 +1100,7 @@ static int cam_vfe_handle_irq_bottom_half(void *handler_priv,
 	struct cam_vfe_mux_ver4_data *vfe_priv;
 	struct cam_vfe_top_irq_evt_payload *payload;
 	struct cam_isp_hw_event_info evt_info;
+	struct cam_isp_hw_error_event_info err_evt_info;
 	uint32_t irq_status[CAM_IFE_IRQ_REGISTERS_MAX] = {0};
 	struct timespec64 ts;
 	int i = 0;
@@ -1111,6 +1204,8 @@ static int cam_vfe_handle_irq_bottom_half(void *handler_priv,
 		& vfe_priv->reg_data->error_irq_mask) {
 		CAM_ERR(CAM_ISP, "VFE:%d Error", evt_info.hw_idx);
 
+		err_evt_info.err_type = CAM_VFE_IRQ_STATUS_VIOLATION;
+		evt_info.event_data = (void *)&err_evt_info;
 		ktime_get_boottime_ts64(&ts);
 		CAM_INFO(CAM_ISP,
 			"current monotonic time stamp seconds %lld:%lld",
@@ -1356,8 +1451,9 @@ static int cam_vfe_resource_stop(
 	struct cam_isp_resource_node *vfe_res)
 {
 	struct cam_vfe_mux_ver4_data        *vfe_priv;
-	int                                        rc = 0;
-	uint32_t                                   val = 0;
+	struct cam_vfe_top_ver4_priv        *top_priv;
+	int                                  rc = 0;
+	uint32_t                             val = 0;
 
 	if (!vfe_res) {
 		CAM_ERR(CAM_ISP, "Error, Invalid input arguments");
@@ -1369,6 +1465,7 @@ static int cam_vfe_resource_stop(
 		return 0;
 
 	vfe_priv = (struct cam_vfe_mux_ver4_data *)vfe_res->res_priv;
+	top_priv = vfe_priv->top_priv;
 
 	if (vfe_priv->is_lite || !vfe_priv->is_pixel_path)
 		goto skip_core_decfg;
@@ -1414,7 +1511,10 @@ skip_core_decfg:
 		vfe_priv->irq_err_handle = 0;
 	}
 
-	vfe_priv->epoch_factor = 0;
+	/* Skip epoch factor reset for internal recovery */
+	if (!top_priv->top_common.skip_data_rst_on_stop)
+		vfe_priv->epoch_factor = 0;
+
 	CAM_DBG(CAM_ISP, "VFE:%d Res: %s Stopped",
 		vfe_res->hw_intf->hw_idx,
 		vfe_res->res_name);

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.h

@@ -57,6 +57,8 @@ struct cam_vfe_top_ver4_reg_offset_common {
 	uint32_t epoch1_pattern_cfg;
 	uint32_t epoch_height_cfg;
 	uint32_t top_debug_cfg;
+	uint32_t pdaf_input_cfg_0;
+	uint32_t pdaf_input_cfg_1;
 	uint32_t num_top_debug_reg;
 	uint32_t top_debug[CAM_VFE_TOP_DBG_REG_MAX];
 };
@@ -93,6 +95,11 @@ struct cam_vfe_top_ver4_pdaf_violation_desc {
 	char     *desc;
 };
 
+struct cam_vfe_top_ver4_pdaf_lcr_res_info {
+	uint32_t  res_id;
+	uint32_t  val;
+};
+
 struct cam_vfe_ver4_path_hw_info {
 	struct cam_vfe_top_ver4_reg_offset_common  *common_reg;
 	struct cam_vfe_ver4_path_reg_data          *reg_data;
@@ -121,6 +128,8 @@ struct cam_vfe_top_ver4_hw_info {
 	struct cam_vfe_top_ver4_top_err_irq_desc    *top_err_desc;
 	uint32_t                                     num_pdaf_violation_errors;
 	struct cam_vfe_top_ver4_pdaf_violation_desc *pdaf_violation_desc;
+	struct cam_vfe_top_ver4_pdaf_lcr_res_info   *pdaf_lcr_res_mask;
+	uint32_t                                     num_pdaf_lcr_res;
 };
 
 struct cam_vfe_ver4_path_reg_data {

drivers/cam_req_mgr/cam_mem_mgr.c

@@ -1946,12 +1946,11 @@ int cam_mem_mgr_send_buffer_to_presil(int32_t iommu_hdl, int32_t buf_handle)
 	/* Sending Presil IO Buf to PC side ( as iova start address indicates) */
 	uint64_t io_buf_addr;
 	size_t io_buf_size;
-	int i, fd = -1, idx = 0;
+	int i, j, fd = -1, idx = 0;
 	uint8_t *iova_ptr = NULL;
 	uint64_t dmabuf = 0;
 	bool is_mapped_in_cb = false;
 
-
 	CAM_DBG(CAM_PRESIL, "buf handle 0x%0x", buf_handle);
 
 	idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
@@ -1960,8 +1959,28 @@ int cam_mem_mgr_send_buffer_to_presil(int32_t iommu_hdl, int32_t buf_handle)
 			is_mapped_in_cb = true;
 	}
 
-	if (!is_mapped_in_cb)
-		return 0;
+	if (!is_mapped_in_cb) {
+		for (j = 0; j < CAM_MEM_BUFQ_MAX; j++) {
+			if (tbl.bufq[j].i_ino == tbl.bufq[idx].i_ino) {
+				for (i = 0; i < tbl.bufq[j].num_hdl; i++) {
+					if (tbl.bufq[j].hdls[i] == iommu_hdl)
+						is_mapped_in_cb = true;
+				}
+			}
+		}
+
+		if (!is_mapped_in_cb) {
+			CAM_DBG(CAM_PRESIL,
+				"Still Could not find idx=%d, FD %d buf_handle 0x%0x",
+				idx, GET_FD_FROM_HANDLE(buf_handle), buf_handle);
+
+			/*
+			 * Okay to return 0, since this function also gets called for buffers that
+			 * are shared only between umd/kmd, these may not be mapped with smmu
+			 */
+			return 0;
+		}
+	}
 
 	if ((tbl.bufq[idx].buf_handle != 0) && (tbl.bufq[idx].active) &&
 		(tbl.bufq[idx].buf_handle == buf_handle)) {

drivers/cam_req_mgr/cam_req_mgr_core.c

@@ -922,7 +922,7 @@ static int __cam_req_mgr_send_req(struct cam_req_mgr_core_link *link,
 			apply_req.dev_hdl = dev->dev_hdl;
 			apply_req.request_id =
 				link->req.prev_apply_data[pd].req_id;
-			apply_req.trigger_point = 0;
+			apply_req.trigger_point = trigger;
 			apply_req.report_if_bubble = 0;
 			if ((dev->ops) && (dev->ops->notify_frame_skip))
 				dev->ops->notify_frame_skip(&apply_req);
@@ -1002,7 +1002,7 @@ static int __cam_req_mgr_send_req(struct cam_req_mgr_core_link *link,
 				apply_req.dev_hdl = dev->dev_hdl;
 				apply_req.request_id =
 					link->req.prev_apply_data[pd].req_id;
-				apply_req.trigger_point = 0;
+				apply_req.trigger_point = trigger;
 				apply_req.report_if_bubble = 0;
 				if ((dev->ops) && (dev->ops->notify_frame_skip))
 					dev->ops->notify_frame_skip(&apply_req);
@@ -1599,7 +1599,10 @@ static int __cam_req_mgr_check_sync_req_is_ready(
 	if ((trigger == CAM_TRIGGER_POINT_SOF) &&
 		(sync_link->sof_timestamp > 0) &&
 		(sof_timestamp_delta < master_slave_diff) &&
-		(sync_rd_slot->sync_mode == CAM_REQ_MGR_SYNC_MODE_SYNC)) {
+		(sync_rd_slot->sync_mode == CAM_REQ_MGR_SYNC_MODE_SYNC) &&
+		(req_id >= link->initial_sync_req) &&
+		(req_id - link->initial_sync_req >=
+		(INITIAL_IN_SYNC_REQ + link->max_delay))) {
 
 		/*
 		 * This means current frame should sync with next
@@ -2635,8 +2638,11 @@ static int __cam_req_mgr_try_cancel_req(struct cam_req_mgr_core_link *link,
 	case CRM_SLOT_STATUS_REQ_PENDING:
 	case CRM_SLOT_STATUS_REQ_APPLIED:
 		pd = __cam_req_mgr_get_dev_pd(link, CAM_REQ_MGR_DEVICE_IFE);
-		if (pd < 0)
+		if ((pd < 0) || (pd >= CAM_PIPELINE_DELAY_MAX)) {
+			CAM_ERR(CAM_CRM, "pd: %d link_hdl: 0x%x red_id: %d", pd,
+				link->link_hdl, flush_info->req_id);
 			return pd;
+		}
 
 		if (flush_info->req_id <= link->req.prev_apply_data[pd].req_id) {
 			CAM_WARN(CAM_CRM, "req %lld already applied to IFE on link 0x%x",

drivers/cam_req_mgr/cam_req_mgr_core.h

@@ -31,6 +31,8 @@
 /* Default frame rate is 30 */
 #define DEFAULT_FRAME_DURATION 33333333
 
+#define INITIAL_IN_SYNC_REQ 5
+
 #define SYNC_LINK_SOF_CNT_MAX_LMT 1
 
 #define MAXIMUM_LINKS_PER_SESSION  4

drivers/cam_req_mgr/cam_req_mgr_dev.c

@@ -670,7 +670,7 @@ void cam_video_device_cleanup(void)
 
 void cam_subdev_notify_message(u32 subdev_type,
 		enum cam_subdev_message_type_t message_type,
-		uint32_t data)
+		void *data)
 {
 	struct v4l2_subdev *sd = NULL;
 	struct cam_subdev *csd = NULL;
@@ -836,7 +836,6 @@ static int cam_req_mgr_component_master_bind(struct device *dev)
 		goto req_mgr_core_fail;
 	}
 
-	g_dev.state = true;
 	INIT_LIST_HEAD(&cam_req_mgr_ordered_sd_list);
 
 	if (g_cam_req_mgr_timer_cachep == NULL) {
@@ -851,6 +850,7 @@ static int cam_req_mgr_component_master_bind(struct device *dev)
 	}
 
 	CAM_DBG(CAM_CRM, "All probes done, binding slave components");
+	g_dev.state = true;
 	rc = component_bind_all(dev, NULL);
 	if (rc) {
 		CAM_ERR(CAM_CRM,

drivers/cam_req_mgr/cam_subdev.h

@@ -65,7 +65,7 @@ struct cam_subdev {
 	void                                  (*msg_cb)(
 					struct v4l2_subdev *sd,
 					enum cam_subdev_message_type_t msg_type,
-					uint32_t data);
+					void *data);
 	struct list_head                       list;
 	enum cam_subdev_close_seq_priority     close_seq_prior;
 };
@@ -82,7 +82,7 @@ struct cam_subdev {
  */
 void cam_subdev_notify_message(u32 subdev_type,
 		enum cam_subdev_message_type_t message_type,
-		uint32_t data);
+		void *data);
 
 /**
  * cam_subdev_probe()

drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c

@@ -884,15 +884,6 @@ int32_t cam_actuator_driver_cmd(struct cam_actuator_ctrl_t *a_ctrl,
 			goto release_mutex;
 		}
 
-		if (a_ctrl->cam_act_state == CAM_ACTUATOR_CONFIG) {
-			rc = cam_actuator_power_down(a_ctrl);
-			if (rc < 0) {
-				CAM_ERR(CAM_ACTUATOR,
-					"Actuator Power down failed");
-				goto release_mutex;
-			}
-		}
-
 		if (a_ctrl->bridge_intf.device_hdl == -1) {
 			CAM_ERR(CAM_ACTUATOR, "link hdl: %d device hdl: %d",
 				a_ctrl->bridge_intf.device_hdl,
@@ -901,6 +892,15 @@ int32_t cam_actuator_driver_cmd(struct cam_actuator_ctrl_t *a_ctrl,
 			goto release_mutex;
 		}
 
+		if (a_ctrl->cam_act_state == CAM_ACTUATOR_CONFIG) {
+			rc = cam_actuator_power_down(a_ctrl);
+			if (rc < 0) {
+				CAM_ERR(CAM_ACTUATOR,
+					"Actuator Power Down Failed");
+				goto release_mutex;
+			}
+		}
+
 		if (a_ctrl->bridge_intf.link_hdl != -1) {
 			CAM_ERR(CAM_ACTUATOR,
 				"Device [%d] still active on link 0x%x",

drivers/cam_sensor_module/cam_cci/cam_cci_dev.c

@@ -11,19 +11,18 @@
 
 #define CCI_MAX_DELAY 1000000
 
-static struct v4l2_subdev *g_cci_subdev[MAX_CCI];
+static struct v4l2_subdev *g_cci_subdev[MAX_CCI] = { 0 };
 static struct dentry *debugfs_root;
 
 struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index)
 {
 	struct v4l2_subdev *sub_device = NULL;
 
-	if (cci_dev_index < MAX_CCI)
+	if ((cci_dev_index < MAX_CCI) && (g_cci_subdev[cci_dev_index] != NULL))
 		sub_device = g_cci_subdev[cci_dev_index];
 	else
-		CAM_WARN(CAM_CCI, "Index: %u is beyond max num CCI allowed: %u",
-			cci_dev_index,
-			MAX_CCI);
+		CAM_WARN(CAM_CCI, "CCI subdev not available at Index: %u, MAX_CCI : %u",
+			cci_dev_index, MAX_CCI);
 
 	return sub_device;
 }

drivers/cam_sensor_module/cam_cci/cam_cci_dev.h

@@ -59,7 +59,7 @@
 
 #define CAM_CCI_WORKQUEUE_NAME "cam_cci_wq"
 
-#define MAX_CCI 2
+#define MAX_CCI 3
 
 #define PRIORITY_QUEUE (QUEUE_0)
 #define SYNC_QUEUE (QUEUE_1)

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

@@ -85,7 +85,9 @@ static void cam_csiphy_reset_phyconfig_param(struct csiphy_device *csiphy_dev,
 	csiphy_dev->csiphy_info[index].settle_time = 0;
 	csiphy_dev->csiphy_info[index].data_rate = 0;
 	csiphy_dev->csiphy_info[index].secure_mode = 0;
+	csiphy_dev->csiphy_info[index].mipi_flags = 0;
 	csiphy_dev->csiphy_info[index].hdl_data.device_hdl = -1;
+	csiphy_dev->csiphy_info[index].csiphy_3phase = -1;
 }
 
 static inline void cam_csiphy_apply_onthego_reg_values(void __iomem *csiphybase, uint8_t csiphy_idx)
@@ -229,9 +231,14 @@ int cam_csiphy_dump_status_reg(struct csiphy_device *csiphy_dev)
 		return -EINVAL;
 	}
 
+	if (!g_phy_data[soc_info->index].base_address) {
+		CAM_ERR(CAM_CSIPHY, "Invalid cphy_idx: %d", soc_info->index);
+		return -EINVAL;
+	}
+
 	csiphy_reg = &csiphy_dev->ctrl_reg->csiphy_reg;
 	status_regs = csiphy_reg->status_reg_params;
-	phybase = soc_info->reg_map[0].mem_base;
+	phybase = g_phy_data[soc_info->index].base_address;
 
 	if (!status_regs) {
 		CAM_ERR(CAM_CSIPHY, "2ph/3ph status offset not set");
@@ -630,14 +637,12 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 	 * preamble enable.
 	 */
 	if (csiphy_dev->preamble_enable && !preamble_en &&
-		csiphy_dev->csiphy_info[index].csiphy_3phase) {
+		csiphy_dev->combo_mode &&
+		!csiphy_dev->cphy_dphy_combo_mode) {
 		CAM_ERR(CAM_CSIPHY,
-			"Cannot support CPHY combo mode with differnt preamble settings");
-		return -EINVAL;
-	} else if (preamble_en &&
-		!csiphy_dev->csiphy_info[index].csiphy_3phase) {
-		CAM_ERR(CAM_CSIPHY,
-			"Preamble pattern enablement is not supported for DPHY sensors");
+			"Cannot support %s combo mode with differnt preamble settings",
+			(csiphy_dev->csiphy_info[index].csiphy_3phase ?
+			"CPHY" : "DPHY"));
 		return -EINVAL;
 	}
 
@@ -1416,6 +1421,11 @@ int cam_csiphy_util_update_aon_registration
 		return -EINVAL;
 	}
 
+	if (!g_phy_data[phy_idx].base_address) {
+		CAM_ERR(CAM_CSIPHY, "Invalid PHY idx: %d from Sensor user", phy_idx);
+		return -EINVAL;
+	}
+
 	g_phy_data[phy_idx].enable_aon_support = is_aon_user;
 
 	return 0;
@@ -1433,6 +1443,11 @@ int cam_csiphy_util_update_aon_ops(
 		return -ENODEV;
 	}
 
+	if (!g_phy_data[phy_idx].base_address) {
+		CAM_ERR(CAM_CSIPHY, "phy_idx: %d is not supported", phy_idx);
+		return -EINVAL;
+	}
+
 	if (!g_phy_data[phy_idx].aon_sel_param) {
 		CAM_ERR(CAM_CSIPHY, "AON select parameters are null");
 		return -EINVAL;
@@ -1469,33 +1484,40 @@ int cam_csiphy_util_update_aon_ops(
 	return rc;
 }
 
-static void __cam_csiphy_read_2phase_bist_debug_status(
-	struct csiphy_device *csiphy_dev)
+static void __cam_csiphy_read_2phase_bist_counter_status(
+	struct csiphy_device *csiphy_dev, uint32_t *counter)
 {
-	int i = 0;
+	int i = 0, lane_count;
 	int bist_status_arr_size =
-		csiphy_dev->ctrl_reg->csiphy_bist_reg->num_status_err_check_reg;
-	struct csiphy_reg_t *csiphy_common_reg = NULL;
-	void __iomem *csiphybase = NULL;
-
-	csiphybase = csiphy_dev->soc_info.reg_map[0].mem_base;
+		csiphy_dev->ctrl_reg->csiphy_bist_reg->number_of_counters;
+	uint32_t base_offset = 0;
+	void __iomem *phy_base = NULL;
+	uint32_t val = 0;
+	uint32_t offset_betwn_lane = 0;
+	struct bist_reg_settings_t *bist_reg = NULL;
+
+	phy_base = csiphy_dev->soc_info.reg_map[0].mem_base;
+	bist_reg = csiphy_dev->ctrl_reg->csiphy_bist_reg;
+	offset_betwn_lane =
+		csiphy_dev->ctrl_reg->csiphy_reg.size_offset_betn_lanes;
 
 	for (i = 0; i < bist_status_arr_size; i++) {
-		csiphy_common_reg = &csiphy_dev->ctrl_reg->csiphy_bist_reg
-			->bist_status_err_check_arr[i];
-		switch (csiphy_common_reg->csiphy_param_type) {
-		case CSIPHY_2PH_REGS:
-			CAM_INFO(CAM_CSIPHY, "OFFSET: 0x%x value: 0x%x",
-				csiphybase + csiphy_common_reg->reg_addr,
-				cam_io_r(csiphybase + csiphy_common_reg->reg_addr));
-		break;
+		base_offset = bist_reg->bist_counter_2ph_base_offset + (0x4 * i);
+		val = 0;
+		for (lane_count = 0; lane_count < CAM_CSIPHY_MAX_DPHY_LANES; lane_count++) {
+			CAM_DBG(CAM_CSIPHY, "value to be read from addr: 0x%x is 0x%x",
+				base_offset + (lane_count * offset_betwn_lane),
+				(cam_io_r(phy_base + base_offset + (lane_count * offset_betwn_lane))));
+			val |= ((cam_io_r(phy_base + base_offset + (lane_count * offset_betwn_lane))));
 		}
+		*counter |= (val << (i * 8));
+		CAM_DBG(CAM_CSIPHY, "COUNTER VALUE is 0x%x", *counter);
 	}
 
 	return;
 }
 
-static void __cam_csiphy_poll_2phase_pattern_status(
+static void __cam_csiphy_get_2phase_pattern_status(
 	struct csiphy_device *csiphy_dev)
 {
 	int i = 0;
@@ -1503,32 +1525,19 @@ static void __cam_csiphy_poll_2phase_pattern_status(
 		csiphy_dev->ctrl_reg->csiphy_bist_reg->num_status_reg;
 	struct csiphy_reg_t *csiphy_common_reg = NULL;
 	void __iomem *csiphybase = NULL;
-	uint32_t status = 0x00;
+	uint32_t status = 0;
+	uint32_t counter = 0;
+	struct bist_reg_settings_t *bist_reg = NULL;
 
+	CAM_DBG(CAM_CSIPHY, "ENTER");
 	csiphybase = csiphy_dev->soc_info.reg_map[0].mem_base;
-
-	do {
-		usleep_range(2000, 2010);
-		for (i = 0; i < bist_status_arr_size; i++) {
-			csiphy_common_reg = &csiphy_dev->ctrl_reg->csiphy_bist_reg->bist_arry[i];
-			switch (csiphy_common_reg->csiphy_param_type) {
-			case CSIPHY_2PH_REGS:
-				status |= cam_io_r(csiphybase + csiphy_common_reg->reg_addr);
-			break;
-			}
-
-			if (status != 0) {
-				CAM_INFO(CAM_CSIPHY, "PN9 Pattern Test is completed");
-				break;
-			}
-		}
-	} while (!status);
+	bist_reg = csiphy_dev->ctrl_reg->csiphy_bist_reg;
 
 	/* This loop is to read every lane status value
 	 * in case if loop breaks with only last lane.
 	 */
 	for (i = 0; i < bist_status_arr_size; i++) {
-		csiphy_common_reg = &csiphy_dev->ctrl_reg->csiphy_bist_reg->bist_arry[i];
+		csiphy_common_reg = &bist_reg->bist_status_arr[i];
 		switch (csiphy_common_reg->csiphy_param_type) {
 		case CSIPHY_2PH_REGS:
 			status |= cam_io_r(csiphybase + csiphy_common_reg->reg_addr);
@@ -1536,41 +1545,110 @@ static void __cam_csiphy_poll_2phase_pattern_status(
 		}
 	}
 
-	if (status == csiphy_dev->ctrl_reg->csiphy_bist_reg->expected_status_val)
-		CAM_INFO(CAM_CSIPHY, "PN9 Pattern received successfully");
-	else
-		__cam_csiphy_read_2phase_bist_debug_status(csiphy_dev);
+	/* Read the Counter value for possible corrupted headers */
+	__cam_csiphy_read_2phase_bist_counter_status(csiphy_dev, &counter);
+
+	if ((status & PREAMBLE_PATTERN_BIST_DONE) &&
+		(status & bist_reg->error_status_val_2ph)) {
+		/**
+		 * This condition happen when CSIPHY try to read status after sensor
+		 * streamoff. In this case error bit is set due to postamble detection
+		 * which is bit(4). In this scenraio this is not consider as an error.
+		 * We need to check for status2/3 counter value to determine if there are
+		 * more header that is corrupted than 2. Counter always shows value of 2
+		 * with postamble packet.
+		 *
+		 */
+		if (counter <= PREAMBLE_MAX_ERR_COUNT_ALLOWED) {
+			CAM_INFO(CAM_CSIPHY,
+				"PN9 Pattern rxced succesfully:: counter value: 0x%x, Status0: 0x%x",
+				counter, status);
+		} else {
+			CAM_INFO(CAM_CSIPHY,
+				"PN9 Pattern is corrupted:: counter value: 0x%x, Status0: 0x%x",
+				counter, status);
+		}
+	} else if ((status & PREAMBLE_PATTERN_BIST_DONE) &&
+		!(status & bist_reg->error_status_val_2ph)) {
+		/**
+		 * This condition happen when CSIPHY try to read status with some counter
+		 * value is set to check against. In this case error bit is not expected
+		 * to be set.
+		 */
+		CAM_INFO(CAM_CSIPHY,
+			"PN9 Pattern rxced succesfully:: counter value: 0x%x, Status0: 0x%x",
+			counter, status);
+	} else {
+		CAM_INFO(CAM_CSIPHY,
+			"PN9 Pattern is corrupted:: counter value: 0x%x Status0: 0x%x",
+			counter, status);
+	}
 
 	return;
 }
 
-static void __cam_csiphy_read_3phase_bist_debug_status(
-	struct csiphy_device *csiphy_dev)
+static void __cam_csiphy_2ph_status_checker_ops(
+	struct csiphy_device *csiphy_dev, bool set)
 {
 	int i = 0;
-	int bist_status_arr_size =
-		csiphy_dev->ctrl_reg->csiphy_bist_reg->num_status_err_check_reg;
-	struct csiphy_reg_t *csiphy_common_reg = NULL;
 	void __iomem *csiphybase = NULL;
+	uint32_t base_offset = 0;
+	uint32_t read_back_value;
+	uint32_t lane_offset = 0;
+	uint32_t offset_betwn_lane = 0;
+	struct bist_reg_settings_t *bist_reg = NULL;
 
 	csiphybase = csiphy_dev->soc_info.reg_map[0].mem_base;
+	bist_reg = csiphy_dev->ctrl_reg->csiphy_bist_reg;
+	base_offset = bist_reg->set_status_update_2ph_base_offset;
+	offset_betwn_lane =
+		csiphy_dev->ctrl_reg->csiphy_reg.size_offset_betn_lanes;
+
+	/* Set checker bit to read the correct status1 value */
+	for (i = 0; i < CAM_CSIPHY_MAX_DPHY_LANES; i++) {
+		lane_offset = base_offset + (i * offset_betwn_lane);
+		read_back_value = cam_io_r(csiphybase + lane_offset);
+		set ? (read_back_value |= PREAMBLE_PATTERN_SET_CHECKER) :
+			(read_back_value &= ~PREAMBLE_PATTERN_SET_CHECKER);
+		cam_io_w_mb(read_back_value, csiphybase + lane_offset);
+	}
+}
+
+static void __cam_csiphy_read_3phase_bist_counter_status(
+	struct csiphy_device *csiphy_dev, uint32_t *counter)
+{
+	int i = 0, lane_count;
+	int bist_status_arr_size =
+		csiphy_dev->ctrl_reg->csiphy_bist_reg->number_of_counters;
+	uint32_t base_offset = 0;
+	void __iomem *phy_base = NULL;
+	uint32_t val = 0;
+	uint32_t offset_betwn_lane = 0;
+	struct bist_reg_settings_t *bist_reg = NULL;
+
+	phy_base = csiphy_dev->soc_info.reg_map[0].mem_base;
+	bist_reg = csiphy_dev->ctrl_reg->csiphy_bist_reg;
+	offset_betwn_lane =
+		csiphy_dev->ctrl_reg->csiphy_reg.size_offset_betn_lanes;
 
 	for (i = 0; i < bist_status_arr_size; i++) {
-		csiphy_common_reg = &csiphy_dev->ctrl_reg->csiphy_bist_reg
-			->bist_status_err_check_arr[i];
-		switch (csiphy_common_reg->csiphy_param_type) {
-		case CSIPHY_3PH_REGS:
-				CAM_INFO(CAM_CSIPHY, "OFFSET: 0x%x value: 0x%x",
-					csiphybase + csiphy_common_reg->reg_addr,
-					cam_io_r(csiphybase + csiphy_common_reg->reg_addr));
-		break;
+		base_offset = bist_reg->bist_counter_3ph_base_offset + (0x4 * i);
+		val = 0;
+		for (lane_count = 0; lane_count < CAM_CSIPHY_MAX_CPHY_LANES; lane_count++) {
+			CAM_DBG(CAM_CSIPHY, "value to be read from addr: 0x%x is 0x%x",
+				base_offset + (lane_count * offset_betwn_lane),
+				(cam_io_r(phy_base + base_offset + (lane_count * offset_betwn_lane))));
+			val |= ((cam_io_r(phy_base + base_offset + (lane_count * offset_betwn_lane))));
 		}
+
+		*counter |= (val << (i * 8));
+		CAM_DBG(CAM_CSIPHY, "COUNTER VALUE is 0x%x", *counter);
 	}
 
 	return;
 }
 
-static void __cam_csiphy_poll_3phase_pattern_status(
+static void __cam_csiphy_get_3phase_pattern_status(
 	struct csiphy_device *csiphy_dev)
 {
 	int i = 0;
@@ -1578,31 +1656,25 @@ static void __cam_csiphy_poll_3phase_pattern_status(
 		csiphy_dev->ctrl_reg->csiphy_bist_reg->num_status_reg;
 	struct csiphy_reg_t *csiphy_common_reg = NULL;
 	void __iomem *csiphybase = NULL;
-	uint32_t status1 = 0x00;
+	uint32_t base_offset = 0;
+	uint32_t lane_offset = 0;
+	uint32_t status1 = 0, status0 = 0;
+	uint32_t counter = 0;
+	uint32_t offset_betwn_lane = 0;
+	struct bist_reg_settings_t *bist_reg = NULL;
 
+	CAM_DBG(CAM_CSIPHY, "ENTER");
 	csiphybase = csiphy_dev->soc_info.reg_map[0].mem_base;
-
-	do {
-		usleep_range(2000, 2010);
-		for (i = 0; i < bist_status_arr_size; i++) {
-			csiphy_common_reg = &csiphy_dev->ctrl_reg->csiphy_bist_reg->bist_status_arr[i];
-			switch (csiphy_common_reg->csiphy_param_type) {
-			case CSIPHY_3PH_REGS:
-				status1 |= cam_io_r(csiphybase + csiphy_common_reg->reg_addr);
-			break;
-			}
-			if (status1 != 0) {
-				CAM_INFO(CAM_CSIPHY, "PN9 Pattern test is completed");
-				break;
-			}
-		}
-	} while (!status1);
+	bist_reg = csiphy_dev->ctrl_reg->csiphy_bist_reg;
+	base_offset = bist_reg->bist_sensor_data_3ph_status_base_offset;
+	offset_betwn_lane =
+		csiphy_dev->ctrl_reg->csiphy_reg.size_offset_betn_lanes;
 
 	/* This loop is to read every lane status value
 	 * in case if loop breaks with only last lane.
 	 */
 	for (i = 0; i < bist_status_arr_size; i++) {
-		csiphy_common_reg = &csiphy_dev->ctrl_reg->csiphy_bist_reg->bist_status_arr[i];
+		csiphy_common_reg = &bist_reg->bist_status_arr[i];
 		switch (csiphy_common_reg->csiphy_param_type) {
 		case CSIPHY_3PH_REGS:
 			status1 |= cam_io_r(csiphybase + csiphy_common_reg->reg_addr);
@@ -1610,44 +1682,97 @@ static void __cam_csiphy_poll_3phase_pattern_status(
 		}
 	}
 
-	if (status1 == csiphy_dev->ctrl_reg->csiphy_bist_reg->expected_status_val)
-		CAM_INFO(CAM_CSIPHY, "PN9 Pattern received successfully");
-	else
-		__cam_csiphy_read_3phase_bist_debug_status(csiphy_dev);
+	/* Read Status0 value to detect sensor related communication */
+	for (i = 0; i < CAM_CSIPHY_MAX_CPHY_LANES; i++) {
+		lane_offset = base_offset + (i * offset_betwn_lane);
+		status0 |= cam_io_r(csiphybase + lane_offset);
+	}
+
+
+	/* Read the Counter value for possible corrupted headers */
+	__cam_csiphy_read_3phase_bist_counter_status(csiphy_dev, &counter);
+
+	if ((status1 & PREAMBLE_PATTERN_BIST_DONE) &&
+		(status1 & bist_reg->error_status_val_3ph)) {
+		/**
+		 * This condition happen when CSIPHY try to read status after sensor
+		 * streamoff. In this case error bit is set due to postamble detection
+		 * which is bit(4). In this scenraio this is not consider as an error.
+		 * We need to check for status2/3 counter value to determine if there are
+		 * more header that is corrupted than 2. Counter always shows value of 2
+		 * with postamble packet.
+		 *
+		 */
+		if (counter <= PREAMBLE_MAX_ERR_COUNT_ALLOWED) {
+			CAM_INFO(CAM_CSIPHY,
+				"PN9 Pattern rxced succesfully after sensor streamoff:: counter value: 0x%x Status1: 0x%x Status0: 0x%x",
+				counter, status1, status0);
+		} else {
+			CAM_INFO(CAM_CSIPHY,
+				"PN9 Pattern is corrupted:: counter value: 0x%x Status1: 0x%x Status0: 0x%x",
+				counter, status1, status0);
+		}
+	} else if ((status1 & PREAMBLE_PATTERN_BIST_DONE) &&
+		!(status1 & bist_reg->error_status_val_3ph)) {
+		/**
+		 * This condition happen when CSIPHY try to read status with some counter
+		 * value is set to check against. In this case error bit is not expected
+		 * to be set.
+		 */
+		CAM_INFO(CAM_CSIPHY,
+			"PN9 Pattern rxced succesfully before sensor streamoff:: counter value: 0x%x Status1: 0x%x Status0: 0x%x",
+			counter, status1, status0);
+	} else {
+		CAM_INFO(CAM_CSIPHY,
+			"PN9 Pattern is corrupted:: counter value: 0x%x Status1: 0x%x Status0: 0x%x",
+			counter, status1, status0);
+	}
 
 	return;
 }
 
-static void __cam_csiphy_poll_preamble_status(
-	struct csiphy_device *csiphy_dev, int offset)
+static void __cam_csiphy_3ph_status_checker_ops(
+	struct csiphy_device *csiphy_dev, bool set)
 {
-	bool is_3phase = false;
-
-	is_3phase = csiphy_dev->csiphy_info[offset].csiphy_3phase;
-
-	if (is_3phase)
-		__cam_csiphy_poll_3phase_pattern_status(csiphy_dev);
-	else
-		__cam_csiphy_poll_2phase_pattern_status(csiphy_dev);
+	int i = 0;
+	void __iomem *csiphybase = NULL;
+	uint32_t base_offset = 0;
+	uint32_t read_back_value;
+	uint32_t lane_offset = 0;
+	uint32_t offset_betwn_lane = 0;
 
-	return;
+	csiphybase = csiphy_dev->soc_info.reg_map[0].mem_base;
+	base_offset =
+		csiphy_dev->ctrl_reg->csiphy_bist_reg->set_status_update_3ph_base_offset;
+	offset_betwn_lane =
+		csiphy_dev->ctrl_reg->csiphy_reg.size_offset_betn_lanes;
+	/* Set checker bit to read the correct status1 value */
+	for (i = 0; i < CAM_CSIPHY_MAX_CPHY_LANES; i++) {
+		lane_offset = base_offset + (i * offset_betwn_lane);
+		read_back_value = cam_io_r(csiphybase + lane_offset);
+		set ? (read_back_value |= PREAMBLE_PATTERN_SET_CHECKER) :
+			(read_back_value &= ~PREAMBLE_PATTERN_SET_CHECKER);
+		cam_io_w_mb(read_back_value, csiphybase + lane_offset);
+	}
 }
 
-static void csiphy_work_queue_ops(struct work_struct *work)
+static void __cam_csiphy_get_preamble_status(
+	struct csiphy_device *csiphy_dev, int offset)
 {
-	struct csiphy_work_queue *wq = NULL;
-	struct csiphy_device *csiphy_dev = NULL;
-	int32_t offset = -1;
+	bool is_3phase = false;
 
-	wq = container_of(work, struct csiphy_work_queue, work);
-	if (wq) {
-		csiphy_dev = wq->csiphy_dev;
-		offset = wq->acquire_idx;
+	is_3phase = csiphy_dev->csiphy_info[offset].csiphy_3phase;
 
-		__cam_csiphy_poll_preamble_status(csiphy_dev, offset);
+	if (is_3phase) {
+		__cam_csiphy_3ph_status_checker_ops(csiphy_dev, true);
+		__cam_csiphy_get_3phase_pattern_status(csiphy_dev);
+		__cam_csiphy_3ph_status_checker_ops(csiphy_dev, false);
+	} else {
+		__cam_csiphy_2ph_status_checker_ops(csiphy_dev, true);
+		__cam_csiphy_get_2phase_pattern_status(csiphy_dev);
+		__cam_csiphy_2ph_status_checker_ops(csiphy_dev, false);
 	}
-
-	kfree(wq);
+	return;
 }
 
 int32_t cam_csiphy_core_cfg(void *phy_dev,
@@ -1680,6 +1805,12 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 		return -EINVAL;
 	}
 
+	if (!g_phy_data[soc_info->index].base_address) {
+		CAM_ERR(CAM_CSIPHY, "CSIPHY hw is not avaialble at index: %d",
+			soc_info->index);
+		return -EINVAL;
+	}
+
 	csiphybase = soc_info->reg_map[0].mem_base;
 	csiphy_reg = &csiphy_dev->ctrl_reg->csiphy_reg;
 	status_reg_ptr = csiphy_reg->status_reg_params;
@@ -1898,6 +2029,9 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 			cam_csiphy_prgm_cmn_data(csiphy_dev, true);
 		}
 
+		if (csiphy_dev->preamble_enable)
+			__cam_csiphy_get_preamble_status(csiphy_dev, offset);
+
 		rc = cam_csiphy_disable_hw(csiphy_dev);
 		if (rc < 0)
 			CAM_ERR(CAM_CSIPHY, "Failed in csiphy release");
@@ -1953,6 +2087,7 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 			CAM_SECURE_MODE_NON_SECURE;
 
 		csiphy_dev->csiphy_cpas_cp_reg_mask[offset] = 0x0;
+		csiphy_dev->preamble_enable = 0;
 
 		rc = cam_destroy_device_hdl(release.dev_handle);
 		if (rc < 0)
@@ -2004,7 +2139,6 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 	}
 	case CAM_START_DEV: {
 		struct cam_start_stop_dev_cmd config;
-		struct csiphy_work_queue *wq;
 		int32_t offset;
 		int clk_vote_level = -1;
 
@@ -2184,19 +2318,6 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 			csiphy_dev->start_dev_count);
 		csiphy_dev->csiphy_state = CAM_CSIPHY_START;
 
-		if (csiphy_dev->preamble_enable) {
-			wq = kzalloc(sizeof(struct csiphy_work_queue),
-				GFP_ATOMIC);
-			if (wq) {
-				INIT_WORK((struct work_struct *)
-					&wq->work, csiphy_work_queue_ops);
-				wq->csiphy_dev = csiphy_dev;
-				wq->acquire_idx = offset;
-				queue_work(csiphy_dev->work_queue,
-					&wq->work);
-			}
-		}
-
 		CAM_INFO(CAM_CSIPHY,
 			"CAM_START_PHYDEV: CSIPHY_IDX: %d, Device_slot: %d, cp_mode: %d, Datarate: %llu, Settletime: %llu",
 			csiphy_dev->soc_info.index, offset,
@@ -2250,19 +2371,19 @@ release_mutex:
 	return rc;
 }
 
-void cam_csiphy_register_baseaddress(struct csiphy_device *csiphy_dev)
+int cam_csiphy_register_baseaddress(struct csiphy_device *csiphy_dev)
 {
 	int phy_idx;
 
 	if (!csiphy_dev) {
-		CAM_WARN(CAM_CSIPHY, "Data is NULL");
-		return;
+		CAM_ERR(CAM_CSIPHY, "Data is NULL");
+		return -EINVAL;
 	}
 
 	if (csiphy_dev->soc_info.index >= MAX_CSIPHY) {
 		CAM_ERR(CAM_CSIPHY, "Invalid soc index: %u Max soc index: %u",
 			csiphy_dev->soc_info.index, MAX_CSIPHY);
-		return;
+		return -EINVAL;
 	}
 
 	phy_idx = csiphy_dev->soc_info.index;
@@ -2273,4 +2394,6 @@ void cam_csiphy_register_baseaddress(struct csiphy_device *csiphy_dev)
 	g_phy_data[phy_idx].aon_sel_param =
 		csiphy_dev->ctrl_reg->csiphy_reg.aon_sel_params;
 	g_phy_data[phy_idx].enable_aon_support = false;
+
+	return 0;
 }

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.h

@@ -54,7 +54,7 @@ void cam_csiphy_shutdown(struct csiphy_device *csiphy_dev);
  *
  * This API registers base address per soc_idx
  */
-void cam_csiphy_register_baseaddress(struct csiphy_device *csiphy_dev);
+int cam_csiphy_register_baseaddress(struct csiphy_device *csiphy_dev);
 
 /**
  * @get_access : Get Access for the Main Camera over AON Camera

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c

@@ -16,15 +16,17 @@ static struct dentry *root_dentry;
 static void cam_csiphy_subdev_handle_message(
 		struct v4l2_subdev *sd,
 		enum cam_subdev_message_type_t message_type,
-		uint32_t data)
+		void *data)
 {
 	struct csiphy_device *csiphy_dev = v4l2_get_subdevdata(sd);
+	uint32_t data_idx;
 
 	switch (message_type) {
 	case CAM_SUBDEV_MESSAGE_IRQ_ERR:
+		data_idx = *(uint32_t *)data;
 		CAM_INFO(CAM_CSIPHY, "subdev index : %d CSIPHY index: %d",
-				csiphy_dev->soc_info.index, data);
-		if (data == csiphy_dev->soc_info.index) {
+				csiphy_dev->soc_info.index, data_idx);
+		if (data_idx == csiphy_dev->soc_info.index) {
 			cam_csiphy_common_status_reg_dump(csiphy_dev);
 
 			if (csiphy_dev->en_full_phy_reg_dump)
@@ -284,6 +286,7 @@ static int cam_csiphy_component_bind(struct device *dev,
 		new_csiphy_dev->csiphy_info[i].lane_cnt = 0;
 		new_csiphy_dev->csiphy_info[i].lane_assign = 0;
 		new_csiphy_dev->csiphy_info[i].lane_enable = 0;
+		new_csiphy_dev->csiphy_info[i].mipi_flags = 0;
 	}
 
 	new_csiphy_dev->ops.get_dev_info = NULL;
@@ -292,6 +295,7 @@ static int cam_csiphy_component_bind(struct device *dev,
 
 	new_csiphy_dev->acquire_count = 0;
 	new_csiphy_dev->start_dev_count = 0;
+	new_csiphy_dev->preamble_enable = 0;
 
 	cpas_parms.cam_cpas_client_cb = NULL;
 	cpas_parms.cell_index = new_csiphy_dev->soc_info.index;
@@ -313,19 +317,12 @@ static int cam_csiphy_component_bind(struct device *dev,
 	snprintf(wq_name, 32, "%s%d%s", "csiphy",
 		new_csiphy_dev->soc_info.index, "_wq");
 
-	new_csiphy_dev->work_queue = alloc_workqueue("wq_name",
-		WQ_UNBOUND | WQ_MEM_RECLAIM, 1);
-	if (!new_csiphy_dev->work_queue) {
-		CAM_ERR(CAM_CSIPHY,
-			"Error allocating workqueue for csiphy: %d",
-			new_csiphy_dev->soc_info.index);
-		rc = -ENOMEM;
-		goto csiphy_unregister_subdev;
+	rc = cam_csiphy_register_baseaddress(new_csiphy_dev);
+	if (rc) {
+		CAM_ERR(CAM_CSIPHY, "Failed to register baseaddress, rc: %d", rc);
+		goto cpas_unregister;
 	}
 
-	cam_csiphy_register_baseaddress(new_csiphy_dev);
-
-
 	CAM_DBG(CAM_CSIPHY, "%s component bound successfully",
 		pdev->name);
 
@@ -333,6 +330,8 @@ static int cam_csiphy_component_bind(struct device *dev,
 
 	return rc;
 
+cpas_unregister:
+	cam_cpas_unregister_client(new_csiphy_dev->cpas_handle);
 csiphy_unregister_subdev:
 	cam_unregister_subdev(&(new_csiphy_dev->v4l2_dev_str));
 csiphy_no_resource:

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h

@@ -28,7 +28,7 @@
 #include "cam_debug_util.h"
 #include "cam_context.h"
 
-#define MAX_CSIPHY                  6
+#define MAX_CSIPHY                  8
 
 #define CSIPHY_NUM_CLK_MAX          16
 
@@ -67,6 +67,11 @@
 #define DPHY_LANE_3    BIT(6)
 #define DPHY_CLK_LN    BIT(7)
 
+/* PRBS Pattern Macros */
+#define PREAMBLE_PATTERN_SET_CHECKER    BIT(4)
+#define PREAMBLE_PATTERN_BIST_DONE      BIT(0)
+#define PREAMBLE_MAX_ERR_COUNT_ALLOWED  2
+
 enum cam_csiphy_state {
 	CAM_CSIPHY_INIT,
 	CAM_CSIPHY_ACQUIRE,
@@ -214,13 +219,20 @@ struct data_rate_settings_t {
 };
 
 struct bist_reg_settings_t {
-	uint32_t expected_status_val;
-	ssize_t num_data_settings;
+	uint32_t error_status_val_3ph;
+	uint32_t error_status_val_2ph;
+	uint32_t set_status_update_3ph_base_offset;
+	uint32_t set_status_update_2ph_base_offset;
+	uint32_t bist_status_3ph_base_offset;
+	uint32_t bist_status_2ph_base_offset;
+	uint32_t bist_sensor_data_3ph_status_base_offset;
+	uint32_t bist_counter_3ph_base_offset;
+	uint32_t bist_counter_2ph_base_offset;
+	uint32_t number_of_counters;
 	ssize_t num_status_reg;
-	ssize_t num_status_err_check_reg;
+	ssize_t num_data_settings;
 	struct csiphy_reg_t *bist_arry;
 	struct csiphy_reg_t *bist_status_arr;
-	struct csiphy_reg_t *bist_status_err_check_arr;
 };
 
 /**
@@ -319,7 +331,6 @@ struct csiphy_work_queue {
  * @en_lane_status_reg_dump    : Debugfs flag to enable cphy/dphy lane status dump
  * @en_full_phy_reg_dump       : Debugfs flag to enable the dump for all the Phy registers
  * @preamble_enable            : To enable preamble pattern
- * @work_queue                 : Work queue to offload the work
  */
 struct csiphy_device {
 	char                           device_name[CAM_CTX_DEV_NAME_MAX_LENGTH];
@@ -354,7 +365,6 @@ struct csiphy_device {
 	bool                           en_lane_status_reg_dump;
 	bool                           en_full_phy_reg_dump;
 	uint16_t                       preamble_enable;
-	struct workqueue_struct       *work_queue;
 };
 
 /**

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h

@@ -364,8 +364,8 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x0258, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0254, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x025C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0248, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x024C, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0248, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x024C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0240, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0260, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS},
 	},
@@ -403,8 +403,8 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x0658, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0654, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x065C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0648, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x064C, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0648, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x064C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0640, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0660, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS},
 	},
@@ -442,13 +442,12 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x0A58, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A54, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A5C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0A48, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0A4C, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A48, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A4C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A40, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A60, 0xA8, 0x64, CSIPHY_DEFAULT_PARAMS},
 	},
 };
-
 struct csiphy_reg_t bist_arr_2_1_0[] = {
 	/* 3Phase BIST CONFIGURATION REG SET */
 	{0x02D4, 0x64, 0x00, CSIPHY_3PH_REGS},
@@ -469,36 +468,31 @@ struct csiphy_reg_t bist_arr_2_1_0[] = {
 };
 
 struct csiphy_reg_t bist_status_arr_2_1_0[] = {
-	/* STATUS1 for the BIST checker output for 3phase */
+
 	{0x0344, 0x00, 0x00, CSIPHY_3PH_REGS},
 	{0x0744, 0x00, 0x00, CSIPHY_3PH_REGS},
 	{0x0B44, 0x00, 0x00, CSIPHY_3PH_REGS},
-	/* STATUS0 for BIST checker output for 2phase */
 	{0x00C0, 0x00, 0x00, CSIPHY_2PH_REGS},
 	{0x04C0, 0x00, 0x00, CSIPHY_2PH_REGS},
 	{0x08C0, 0x00, 0x00, CSIPHY_2PH_REGS},
 	{0x0CC0, 0x00, 0x00, CSIPHY_2PH_REGS},
 };
 
-struct csiphy_reg_t bist_status_err_check_arr_2_1_0[] = {
-	/* STATUS2_3 for the BIST word error detection */
-	{0x0348, 0x00, 0x00, CSIPHY_3PH_REGS},
-	{0x0748, 0x00, 0x00, CSIPHY_3PH_REGS},
-	{0x0B48, 0x00, 0x00, CSIPHY_3PH_REGS},
-	{0x034C, 0x00, 0x00, CSIPHY_3PH_REGS},
-	{0x074C, 0x00, 0x00, CSIPHY_3PH_REGS},
-	{0x0B4C, 0x00, 0x00, CSIPHY_3PH_REGS},
-	/* STATUS */
-};
-
 struct bist_reg_settings_t bist_setting_2_1_0 = {
-	.expected_status_val = 0xB,
+	.error_status_val_3ph = 0x10,
+	.error_status_val_2ph = 0x10,
+	.set_status_update_3ph_base_offset = 0x0240,
+	.set_status_update_2ph_base_offset = 0x0050,
+	.bist_status_3ph_base_offset = 0x0344,
+	.bist_status_2ph_base_offset = 0x00C0,
+	.bist_sensor_data_3ph_status_base_offset = 0x0340,
+	.bist_counter_3ph_base_offset = 0x0348,
+	.bist_counter_2ph_base_offset = 0x00C8,
+	.number_of_counters = 2,
 	.num_data_settings = ARRAY_SIZE(bist_arr_2_1_0),
 	.bist_arry = bist_arr_2_1_0,
 	.num_status_reg = ARRAY_SIZE(bist_status_arr_2_1_0),
 	.bist_status_arr = bist_status_arr_2_1_0,
-	.num_status_err_check_reg = ARRAY_SIZE(bist_status_err_check_arr_2_1_0),
-	.bist_status_err_check_arr = bist_status_err_check_arr_2_1_0,
 };
 
 struct data_rate_settings_t data_rate_delta_table_2_1_0 = {
@@ -515,7 +509,7 @@ struct data_rate_settings_t data_rate_delta_table_2_1_0 = {
 						{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0278, 0x70, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
-						{0x028C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x026C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0214, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -528,7 +522,7 @@ struct data_rate_settings_t data_rate_delta_table_2_1_0 = {
 						{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0678, 0x70, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
-						{0x068C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x066C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0614, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -541,7 +535,7 @@ struct data_rate_settings_t data_rate_delta_table_2_1_0 = {
 						{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0A78, 0x70, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
-						{0x0A8C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0A6C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0A14, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},

drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c

@@ -2055,7 +2055,6 @@ int cam_sensor_core_power_up(struct cam_sensor_power_ctrl_t *ctrl,
 							"vreg %s %d",
 							soc_info->rgltr_name[j],
 							rc);
-						soc_info->rgltr[j] = NULL;
 						goto power_up_failed;
 					}
 
@@ -2150,7 +2149,6 @@ int cam_sensor_core_power_up(struct cam_sensor_power_ctrl_t *ctrl,
 						soc_info->rgltr_name[vreg_idx],
 						rc);
 
-					soc_info->rgltr[vreg_idx] = NULL;
 					goto power_up_failed;
 				}
 
@@ -2417,8 +2415,6 @@ int cam_sensor_util_power_down(struct cam_sensor_power_ctrl_t *ctrl,
 						"Reg: %s disable failed",
 						soc_info->rgltr_name[
 							ps->seq_val]);
-						soc_info->rgltr[ps->seq_val] =
-							NULL;
 						msm_cam_sensor_handle_reg_gpio(
 							pd->seq_type,
 							gpio_num_info,

drivers/camera_main.c

@@ -63,6 +63,11 @@
 #include "cam_csid_ppi100.h"
 #include "camera_main.h"
 
+#ifdef CONFIG_CAM_PRESIL
+extern int cam_presil_framework_dev_init_from_main(void);
+extern void cam_presil_framework_dev_exit_from_main(void);
+#endif
+
 struct camera_submodule_component {
 	int (*init)(void);
 	void (*exit)(void);
@@ -171,6 +176,12 @@ static const struct camera_submodule_component camera_custom[] = {
 #endif
 };
 
+static const struct camera_submodule_component camera_presil[] = {
+#ifdef CONFIG_CAM_PRESIL
+	{&cam_presil_framework_dev_init_from_main, &cam_presil_framework_dev_exit_from_main},
+#endif
+};
+
 static const struct camera_submodule submodule_table[] = {
 	{
 		.name = "Camera BASE",
@@ -226,6 +237,11 @@ static const struct camera_submodule submodule_table[] = {
 		.name = "Camera CUSTOM",
 		.num_component = ARRAY_SIZE(camera_custom),
 		.component = camera_custom,
+	},
+	{
+		.name = "Camera Presil",
+		.num_component = ARRAY_SIZE(camera_presil),
+		.component = camera_presil,
 	}
 };
 

include/uapi/camera/media/cam_isp.h

@@ -124,6 +124,7 @@
 #define CAM_ISP_GENERIC_BLOB_TYPE_BW_LIMITER_CFG            16
 #define CAM_ISP_GENERIC_BLOB_TYPE_FPS_CONFIG                17
 #define CAM_ISP_GENERIC_BLOB_TYPE_INIT_CONFIG               18
+#define CAM_ISP_GENERIC_BLOB_TYPE_RDI_LCR_CONFIG            19
 #define CAM_ISP_GENERIC_BLOB_TYPE_SFE_CLOCK_CONFIG          21
 #define CAM_ISP_GENERIC_BLOB_TYPE_SFE_CORE_CONFIG           22
 #define CAM_ISP_GENERIC_BLOB_TYPE_SFE_OUT_CONFIG            23
@@ -1002,6 +1003,32 @@ struct cam_isp_init_config {
 	__u32             additional_params[19];
 };
 
+/**
+ * struct cam_isp_lcr_rdi_config - RDI res id to be muxed to LCR
+ *
+ *    Configure RDI Res id for LCR
+ *
+ * @res_id                   : Out port Res id, it is same as the out port
+ *                             configured during acquire. It would vary
+ *                             as per SFE or IFE. Based on this res id,
+ *                             Mux register in IFE will be programmed.
+ *                             Examples:
+ *                             IFE:
+ *                             CAM_ISP_IFE_OUT_RES_RDI_0
+ *                             SFE:
+ *                             CAM_ISP_SFE_OUT_RES_RDI_0
+ *                             This blob is expected as a part of init packet for
+ *                             all LCR cases. For SHDR-LCR cases, this can be used
+ *                             per request. For non-shdr cases, this blob is not
+ *                             expected as the input to LCR will remain same throughout
+ *                             the session
+ * @reserved                 : Reserved field
+ */
+struct cam_isp_lcr_rdi_config {
+	__u32                                   res_id;
+	__u32                                   reserved[5];
+};
+
 #define CAM_ISP_ACQUIRE_COMMON_VER0         0x1000
 
 #define CAM_ISP_ACQUIRE_COMMON_SIZE_VER0    0x0

include/uapi/camera/media/cam_req_mgr.h

@@ -455,6 +455,8 @@ struct cam_mem_cache_ops_cmd {
  * @CAM_REQ_MGR_CSID_MISSING_PKT_HDR_DATA    : Lesser data received in packet header than expected
  * @CAM_REQ_MGR_CSID_ERR_ON_SENSOR_SWITCHING : Fatal Error encountered while switching the sensors
  * @CAM_REQ_MGR_CSID_UNBOUNDED_FRAME         : No EOF in the frame or the frame started with eof
+ * @CAM_REQ_MGR_ICP_NO_MEMORY                : ICP No Memory
+ * @CAM_REQ_MGR_ICP_ERROR_SYSTEM_FAILURE     : ICP system failure
  */
 #define CAM_REQ_MGR_ISP_UNREPORTED_ERROR                 0
 #define CAM_REQ_MGR_LINK_STALLED_ERROR                   BIT(0)
@@ -467,6 +469,8 @@ struct cam_mem_cache_ops_cmd {
 #define CAM_REQ_MGR_CSID_MISSING_PKT_HDR_DATA            BIT(7)
 #define CAM_REQ_MGR_CSID_ERR_ON_SENSOR_SWITCHING         BIT(8)
 #define CAM_REQ_MGR_CSID_UNBOUNDED_FRAME                 BIT(9)
+#define CAM_REQ_MGR_ICP_NO_MEMORY                        BIT(10)
+#define CAM_REQ_MGR_ICP_SYSTEM_FAILURE                   BIT(11)
 
 /**
  * struct cam_req_mgr_error_msg

include/uapi/camera/media/cam_sync.h

@@ -57,22 +57,41 @@
 #define CAM_SYNC_COMMON_EVENT_END         (CAM_SYNC_COMMON_EVENT_START + 50)
 
 /* ISP Sync event reason types */
-#define CAM_SYNC_ISP_EVENT_START          (CAM_SYNC_COMMON_EVENT_END + 1)
-#define CAM_SYNC_ISP_EVENT_UNKNOWN        (CAM_SYNC_ISP_EVENT_START + 0)
-#define CAM_SYNC_ISP_EVENT_BUBBLE         (CAM_SYNC_ISP_EVENT_START + 1)
-#define CAM_SYNC_ISP_EVENT_OVERFLOW       (CAM_SYNC_ISP_EVENT_START + 2)
-#define CAM_SYNC_ISP_EVENT_P2I_ERROR      (CAM_SYNC_ISP_EVENT_START + 3)
-#define CAM_SYNC_ISP_EVENT_VIOLATION      (CAM_SYNC_ISP_EVENT_START + 4)
-#define CAM_SYNC_ISP_EVENT_BUSIF_OVERFLOW (CAM_SYNC_ISP_EVENT_START + 5)
-#define CAM_SYNC_ISP_EVENT_FLUSH          (CAM_SYNC_ISP_EVENT_START + 6)
-#define CAM_SYNC_ISP_EVENT_HW_STOP        (CAM_SYNC_ISP_EVENT_START + 7)
-#define CAM_SYNC_ISP_EVENT_END            (CAM_SYNC_ISP_EVENT_START + 50)
+#define CAM_SYNC_ISP_EVENT_START                     (CAM_SYNC_COMMON_EVENT_END + 1)
+#define CAM_SYNC_ISP_EVENT_UNKNOWN                   (CAM_SYNC_ISP_EVENT_START + 0)
+#define CAM_SYNC_ISP_EVENT_BUBBLE                    (CAM_SYNC_ISP_EVENT_START + 1)
+#define CAM_SYNC_ISP_EVENT_OVERFLOW                  (CAM_SYNC_ISP_EVENT_START + 2)
+#define CAM_SYNC_ISP_EVENT_P2I_ERROR                 (CAM_SYNC_ISP_EVENT_START + 3)
+#define CAM_SYNC_ISP_EVENT_VIOLATION                 (CAM_SYNC_ISP_EVENT_START + 4)
+#define CAM_SYNC_ISP_EVENT_BUSIF_OVERFLOW            (CAM_SYNC_ISP_EVENT_START + 5)
+#define CAM_SYNC_ISP_EVENT_FLUSH                     (CAM_SYNC_ISP_EVENT_START + 6)
+#define CAM_SYNC_ISP_EVENT_HW_STOP                   (CAM_SYNC_ISP_EVENT_START + 7)
+#define CAM_SYNC_ISP_EVENT_RECOVERY_OVERFLOW         (CAM_SYNC_ISP_EVENT_START + 8)
+#define CAM_SYNC_ISP_EVENT_CSID_OUTPUT_FIFO_OVERFLOW (CAM_SYNC_ISP_EVENT_START + 9)
+#define CAM_SYNC_ISP_EVENT_CSID_RX_ERROR             (CAM_SYNC_ISP_EVENT_START + 10)
+#define CAM_SYNC_ISP_EVENT_CSID_SENSOR_SWITCH_ERROR  (CAM_SYNC_ISP_EVENT_START + 11)
+#define CAM_SYNC_ISP_EVENT_END                       (CAM_SYNC_ISP_EVENT_START + 50)
 
 /* ICP Sync event reason types */
 #define CAM_SYNC_ICP_EVENT_START                 (CAM_SYNC_ISP_EVENT_END + 1)
 #define CAM_SYNC_ICP_EVENT_UNKNOWN               (CAM_SYNC_ICP_EVENT_START + 0)
 #define CAM_SYNC_ICP_EVENT_FRAME_PROCESS_FAILURE (CAM_SYNC_ICP_EVENT_START + 1)
 #define CAM_SYNC_ICP_EVENT_CONFIG_ERR            (CAM_SYNC_ICP_EVENT_START + 2)
+#define CAM_SYNC_ICP_EVENT_NO_MEMORY             (CAM_SYNC_ICP_EVENT_START + 3)
+#define CAM_SYNC_ICP_EVENT_BAD_STATE             (CAM_SYNC_ICP_EVENT_START + 4)
+#define CAM_SYNC_ICP_EVENT_BAD_PARAM             (CAM_SYNC_ICP_EVENT_START + 5)
+#define CAM_SYNC_ICP_EVENT_BAD_ITEM              (CAM_SYNC_ICP_EVENT_START + 6)
+#define CAM_SYNC_ICP_EVENT_INVALID_FORMAT        (CAM_SYNC_ICP_EVENT_START + 7)
+#define CAM_SYNC_ICP_EVENT_UNSUPPORTED           (CAM_SYNC_ICP_EVENT_START + 8)
+#define CAM_SYNC_ICP_EVENT_OUT_OF_BOUND          (CAM_SYNC_ICP_EVENT_START + 9)
+#define CAM_SYNC_ICP_EVENT_TIME_OUT              (CAM_SYNC_ICP_EVENT_START + 10)
+#define CAM_SYNC_ICP_EVENT_ABORTED               (CAM_SYNC_ICP_EVENT_START + 11)
+#define CAM_SYNC_ICP_EVENT_HW_VIOLATION          (CAM_SYNC_ICP_EVENT_START + 12)
+#define CAM_SYNC_ICP_EVENT_CMD_ERROR             (CAM_SYNC_ICP_EVENT_START + 13)
+#define CAM_SYNC_ICP_EVENT_HFI_ERR_COMMAND_SIZE  (CAM_SYNC_ICP_EVENT_START + 14)
+#define CAM_SYNC_ICP_EVENT_HFI_ERR_MESSAGE_SIZE  (CAM_SYNC_ICP_EVENT_START + 15)
+#define CAM_SYNC_ICP_EVENT_HFI_ERR_QUEUE_EMPTY   (CAM_SYNC_ICP_EVENT_START + 16)
+#define CAM_SYNC_ICP_EVENT_HFI_ERR_QUEUE_FULL    (CAM_SYNC_ICP_EVENT_START + 17)
 #define CAM_SYNC_ICP_EVENT_END                   (CAM_SYNC_ICP_EVENT_START + 50)
 
 /* JPEG Sync event reason types */
@@ -84,6 +103,7 @@
 #define CAM_SYNC_JPEG_EVENT_CDM_CHANGE_BASE_ERR (CAM_SYNC_JPEG_EVENT_START + 4)
 #define CAM_SYNC_JPEG_EVENT_CDM_CONFIG_ERR      (CAM_SYNC_JPEG_EVENT_START + 5)
 #define CAM_SYNC_JPEG_EVENT_START_HW_ERR        (CAM_SYNC_JPEG_EVENT_START + 6)
+#define CAM_SYNC_JPEG_EVENT_START_HW_HANG       (CAM_SYNC_JPEG_EVENT_START + 7)
 #define CAM_SYNC_JPEG_EVENT_END                 (CAM_SYNC_JPEG_EVENT_START + 50)
 
 /* FD Sync event reason types */
@@ -125,10 +145,9 @@
 #define CAM_SYNC_CRE_EVENT_HW_ERR              (CAM_SYNC_CRE_EVENT_START + 5)
 #define CAM_SYNC_CRE_EVENT_END                 (CAM_SYNC_CRE_EVENT_START + 50)
 
-#define CAM_SYNC_EVENT_CNT                8
+#define CAM_SYNC_EVENT_MAX         8
 #define CAM_SYNC_EVENT_REASON_CODE_INDEX  0
 
-
 /**
  * struct cam_sync_ev_header - Event header for sync event notification
  *
@@ -152,7 +171,7 @@ struct cam_sync_ev_header_v2 {
 	__s32 sync_obj;
 	__s32 status;
 	uint32_t version;
-	uint32_t evt_param[CAM_SYNC_EVENT_CNT];
+	uint32_t evt_param[CAM_SYNC_EVENT_MAX];
 };
 
 /**