samsung-sm8650/android_kernel_samsung_sm8650-modules
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disp: msm: sde: add line counter logging

소스 검색 
Add logs to track the read/write line counters
and tear check configuration during key events.

Change-Id: Ife8afecc63a9008a8d9fc746d0ec8579a311b335
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
This commit is contained in:
Amine Najahi
2022-10-05 23:34:08 -04:00
committed by Gerrit - the friendly Code Review server
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커밋 2af644d192
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43
msm/sde/sde_encoder_phys_cmd.c
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@@ -207,6 +207,7 @@ static void _sde_encoder_phys_signal_frame_done(struct sde_encoder_phys *phys_en
struct sde_encoder_phys_cmd *cmd_enc;
struct sde_hw_ctl *ctl;
u32 scheduler_status = INVALID_CTL_STATUS, event = 0;
struct sde_hw_pp_vsync_info info[MAX_CHANNELS_PER_ENC] = {{0}};
cmd_enc = to_sde_encoder_phys_cmd(phys_enc);
ctl = phys_enc->hw_ctl;
@@ -230,9 +231,12 @@ static void _sde_encoder_phys_signal_frame_done(struct sde_encoder_phys *phys_en
if (ctl->ops.get_scheduler_status)
scheduler_status = ctl->ops.get_scheduler_status(ctl);
SDE_EVT32_IRQ(DRMID(phys_enc->parent), ctl->idx - CTL_0,
phys_enc->hw_pp->idx - PINGPONG_0, event, scheduler_status,
phys_enc->autorefresh_disable_trans);
sde_encoder_helper_get_pp_line_count(phys_enc->parent, info);
SDE_EVT32_IRQ(DRMID(phys_enc->parent), ctl->idx - CTL_0, phys_enc->hw_pp->idx - PINGPONG_0,
event, scheduler_status, phys_enc->autorefresh_disable_trans, info[0].pp_idx,
info[0].intf_idx, info[0].intf_frame_count, info[0].wr_ptr_line_count,
info[0].rd_ptr_line_count, info[1].pp_idx, info[1].intf_idx,
info[1].intf_frame_count, info[1].wr_ptr_line_count, info[1].rd_ptr_line_count);
/*
* For hw-fences, in the last frame during the autorefresh disable transition
@@ -338,12 +342,10 @@ static void sde_encoder_phys_cmd_te_rd_ptr_irq(void *arg, int irq_idx)
fence_ready = ctl->ops.get_hw_fence_status(ctl);
sde_encoder_helper_get_pp_line_count(phys_enc->parent, info);
SDE_EVT32_IRQ(DRMID(phys_enc->parent),
info[0].pp_idx, info[0].intf_idx,
info[0].wr_ptr_line_count, info[0].intf_frame_count, info[0].rd_ptr_line_count,
info[1].pp_idx, info[1].intf_idx,
info[1].wr_ptr_line_count, info[1].intf_frame_count, info[1].rd_ptr_line_count,
scheduler_status, fence_ready);
SDE_EVT32_IRQ(DRMID(phys_enc->parent), scheduler_status, fence_ready, info[0].pp_idx,
info[0].intf_idx, info[0].intf_frame_count, info[0].wr_ptr_line_count,
info[0].rd_ptr_line_count, info[1].pp_idx, info[1].intf_idx,
info[1].intf_frame_count, info[1].wr_ptr_line_count, info[1].rd_ptr_line_count);
if (phys_enc->parent_ops.handle_vblank_virt)
phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
@@ -379,10 +381,11 @@ static void sde_encoder_phys_cmd_wr_ptr_irq(void *arg, int irq_idx)
}
sde_encoder_helper_get_pp_line_count(phys_enc->parent, info);
SDE_EVT32_IRQ(DRMID(phys_enc->parent),
ctl->idx - CTL_0, event,
info[0].pp_idx, info[0].intf_idx, info[0].wr_ptr_line_count,
info[1].pp_idx, info[1].intf_idx, info[1].wr_ptr_line_count, qsync_mode);
SDE_EVT32_IRQ(DRMID(phys_enc->parent), ctl->idx - CTL_0, event, qsync_mode,
info[0].pp_idx, info[0].intf_idx, info[0].intf_frame_count,
info[0].wr_ptr_line_count, info[0].rd_ptr_line_count, info[1].pp_idx,
info[1].intf_idx, info[1].intf_frame_count, info[1].wr_ptr_line_count,
info[1].rd_ptr_line_count);
if (qsync_mode)
sde_encoder_override_tearcheck_rd_ptr(phys_enc);
@@ -1153,6 +1156,13 @@ static void sde_encoder_phys_cmd_tearcheck_config(
tc_cfg.sync_cfg_height,
tc_cfg.sync_threshold_start, tc_cfg.sync_threshold_continue);
SDE_EVT32(phys_enc->hw_pp->idx - PINGPONG_0, phys_enc->hw_intf->idx - INTF_0,
vsync_hz, mode->vtotal, vrefresh);
SDE_EVT32(tc_enable, tc_cfg.start_pos, tc_cfg.rd_ptr_irq, tc_cfg.wr_ptr_irq,
tc_cfg.hw_vsync_mode, tc_cfg.vsync_count, tc_cfg.vsync_init_val,
tc_cfg.sync_cfg_height, tc_cfg.sync_threshold_start,
tc_cfg.sync_threshold_continue);
if (phys_enc->has_intf_te) {
phys_enc->hw_intf->ops.setup_tearcheck(phys_enc->hw_intf,
&tc_cfg);
@@ -1953,6 +1963,7 @@ static void sde_encoder_phys_cmd_trigger_start(
struct sde_encoder_phys_cmd *cmd_enc =
to_sde_encoder_phys_cmd(phys_enc);
u32 frame_cnt;
struct sde_hw_pp_vsync_info info[MAX_CHANNELS_PER_ENC] = {{0}};
if (!phys_enc)
return;
@@ -1966,6 +1977,12 @@ static void sde_encoder_phys_cmd_trigger_start(
sde_encoder_helper_trigger_start(phys_enc);
}
sde_encoder_helper_get_pp_line_count(phys_enc->parent, info);
SDE_EVT32(DRMID(phys_enc->parent), frame_cnt, info[0].pp_idx, info[0].intf_idx,
info[0].intf_frame_count, info[0].wr_ptr_line_count, info[0].rd_ptr_line_count,
info[1].pp_idx, info[1].intf_idx, info[1].intf_frame_count,
info[1].wr_ptr_line_count, info[1].rd_ptr_line_count);
/* wr_ptr_wait_success is set true when wr_ptr arrives */
cmd_enc->wr_ptr_wait_success = false;
}