msm: camera: isp: Add HW register header for SFE v880

Add register header file for SFE 880 target. Modify
data structures, Macros in SFE top and SFE bus write/read files
accordingly. Update compatible dt match to include sfe 880.

CRs-Fixed: 3175256
Change-Id: I4205578ce473b69f01b3ce79b4f29547d957bb44
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_dev.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/slab.h>
@@ -12,6 +13,7 @@
 #include "cam_sfe_soc.h"
 #include "cam_sfe680.h"
 #include "cam_sfe780.h"
+#include "cam_sfe880.h"
 #include "cam_debug_util.h"
 #include "camera_main.h"
 
@@ -238,6 +240,10 @@ static const struct of_device_id cam_sfe_dt_match[] = {
 		.compatible = "qcom,sfe780",
 		.data = &cam_sfe780_hw_info,
 	},
+	{
+		.compatible = "qcom,sfe880",
+		.data = &cam_sfe880_hw_info,
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, cam_sfe_dt_match);

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_rd.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_SFE_BUS_RD_H_
@@ -30,6 +31,7 @@ struct cam_sfe_bus_rd_reg_offset_common {
 	uint32_t test_bus_ctrl;
 	uint32_t security_cfg;
 	uint32_t cons_violation_status;
+	uint32_t ccif_violation_status;
 	struct cam_irq_controller_reg_info irq_reg_info;
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.h

@@ -89,6 +89,7 @@ struct cam_sfe_bus_reg_offset_common {
 	uint32_t debug_status_top;
 	uint32_t test_bus_ctrl;
 	uint32_t top_irq_mask_0;
+	uint32_t qos_eos_cfg;
 	struct cam_irq_controller_reg_info irq_reg_info;
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_top/cam_sfe_top.h

@@ -20,7 +20,7 @@
 #define CAM_SHIFT_TOP_CORE_CFG_OPS_MODE_CFG    1
 #define CAM_SHIFT_TOP_CORE_CFG_FS_MODE_CFG     0
 
-#define CAM_SFE_TOP_DBG_REG_MAX                18
+#define CAM_SFE_TOP_DBG_REG_MAX                20
 #define CAM_SFE_TOP_TESTBUS_MAX                 2
 #define CAM_SFE_PERF_COUNTER_MAX                2
 
@@ -112,6 +112,7 @@ struct cam_sfe_top_common_reg_offset {
 	uint32_t num_sfe_mode;
 	uint32_t ipp_violation_mask;
 	uint32_t top_debug_testbus_reg;
+	uint32_t top_debug_nonccif_regstart_idx;
 	uint32_t top_cc_test_bus_supported;
 	uint32_t num_debug_registers;
 	uint32_t top_debug[CAM_SFE_TOP_DBG_REG_MAX];
@@ -154,7 +155,7 @@ struct cam_sfe_top_hw_info {
 	uint32_t                                  num_top_errors;
 	struct cam_sfe_top_err_irq_desc          *top_err_desc;
 	uint32_t                                  num_clc_module;
-	struct   cam_sfe_top_debug_info         (*clc_dbg_mod_info)[CAM_SFE_TOP_DBG_REG_MAX][8];
+	struct cam_sfe_top_debug_info           (*clc_dbg_mod_info)[CAM_SFE_TOP_DBG_REG_MAX][8];
 	uint32_t                                  num_of_testbus;
 	struct cam_sfe_testbus_info               test_bus_info[CAM_SFE_TOP_TESTBUS_MAX];
 };