disp: msm: dsi: Adjust DSI priority level

Sets DSI priority level to 7 before any commands are triggered.
This DSI priority setting is recommended by systems team as DSI 
and Lutdma uses same Xin for fetch.

Change-Id: Ife6dee5ed51874818168d92728f76108495b8727
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>

msm/dsi/dsi_ctrl_hw_cmn.c

@@ -8,6 +8,7 @@
 #include <linux/iopoll.h>
 
 #include "dsi_catalog.h"
+#include "dsi_ctrl.h"
 #include "dsi_ctrl_hw.h"
 #include "dsi_ctrl_reg.h"
 #include "dsi_hw.h"
@@ -23,6 +24,7 @@
 #define DSI_CTRL_VIDEO_MISR_ENABLE        BIT(16)
 #define DSI_CTRL_DMA_LINK_SEL             (BIT(12)|BIT(13))
 #define DSI_CTRL_MDP0_LINK_SEL            (BIT(20)|BIT(22))
+#define DSI_VBIF_CTRL_PRIORITY            0x07
 
 static bool dsi_dsc_compression_enabled(struct dsi_mode_info *mode)
 {
@@ -852,14 +854,15 @@ void dsi_ctrl_hw_cmn_cmd_engine_en(struct dsi_ctrl_hw *ctrl, bool on)
  * set, caller should make a separate call to trigger_command_dma() to
  * transmit the command.
  */
-void dsi_ctrl_hw_cmn_kickoff_command(struct dsi_ctrl_hw *ctrl,
+void dsi_ctrl_hw_cmn_kickoff_command(struct dsi_ctrl_hw *ctrl_hw,
 				    struct dsi_ctrl_cmd_dma_info *cmd,
 				    u32 flags)
 {
 	u32 reg = 0;
+	struct dsi_ctrl *ctrl = container_of(ctrl_hw, struct dsi_ctrl, hw);
 
 	/*Set BROADCAST_EN and EMBEDDED_MODE */
-	reg = DSI_R32(ctrl, DSI_COMMAND_MODE_DMA_CTRL);
+	reg = DSI_R32(ctrl_hw, DSI_COMMAND_MODE_DMA_CTRL);
 	if (cmd->en_broadcast)
 		reg |= BIT(31);
 	else
@@ -878,23 +881,29 @@ void dsi_ctrl_hw_cmn_kickoff_command(struct dsi_ctrl_hw *ctrl,
 	reg |= BIT(28);/* Select embedded mode */
 	reg &= ~BIT(24);/* packet type */
 	reg &= ~BIT(29);/* WC_SEL to 0 */
-	DSI_W32(ctrl, DSI_COMMAND_MODE_DMA_CTRL, reg);
+	DSI_W32(ctrl_hw, DSI_COMMAND_MODE_DMA_CTRL, reg);
 
-	reg = DSI_R32(ctrl, DSI_DMA_FIFO_CTRL);
+	reg = DSI_R32(ctrl_hw, DSI_DMA_FIFO_CTRL);
 	reg |= BIT(20);/* Disable write watermark*/
 	reg |= BIT(16);/* Disable read watermark */
 
-	DSI_W32(ctrl, DSI_DMA_FIFO_CTRL, reg);
-	DSI_W32(ctrl, DSI_DMA_CMD_OFFSET, cmd->offset);
-	DSI_W32(ctrl, DSI_DMA_CMD_LENGTH, (cmd->length & 0xFFFFFF));
+	DSI_W32(ctrl_hw, DSI_DMA_FIFO_CTRL, reg);
+	DSI_W32(ctrl_hw, DSI_DMA_CMD_OFFSET, cmd->offset);
+	DSI_W32(ctrl_hw, DSI_DMA_CMD_LENGTH, (cmd->length & 0xFFFFFF));
+
+	if (ctrl->version >= DSI_CTRL_VERSION_2_8) {
+		reg = DSI_R32(ctrl_hw, DSI_VBIF_CTRL);
+		reg |= (DSI_VBIF_CTRL_PRIORITY & 0x7);
+		DSI_W32(ctrl_hw, DSI_VBIF_CTRL, reg);
+	}
 
 	/* wait for writes to complete before kick off */
 	wmb();
 
 	if (!(flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER))
-		DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1);
+		DSI_W32(ctrl_hw, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1);
 
-	SDE_EVT32(ctrl->index, cmd->length, flags);
+	SDE_EVT32(ctrl_hw->index, cmd->length, flags);
 }
 
 /**