msm: camera: isp: Improve support for bus read/write error debug

Add support for new bus rd ccif violation on SFE v880. Add bus rd
constraint violation description and infrastructure to print the
description. Update constraint violations desc for bus wr on SFE
v880 header. Move the irq err mask to the headers, this way the
mask will be dependent on the error bits for a given target. Add
cons_chk_en_avail to indicate if constraint checker needs to be
activated. Cons checker needs to be enabled on Lanai to get cons
violation irq. Add support to skip false alert of constraint
violation of bus write on image address unalign and image width
unalign error bits.

Move macros for bus rd RUP and BUF done to bus_rd.h file.

CRs-Fixed: 3186604
Change-Id: Ifa48ca8de7666a044e9c9b3641de0915b6f16587
Signed-off-by: Sokchetra Eung <[email protected]>

drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_sfe_hw_intf.h

@@ -44,9 +44,9 @@ enum cam_sfe_hw_irq_regs {
 	CAM_SFE_IRQ_REGISTERS_MAX,
 };
 
-enum cam_sfe_bus_irq_regs {
-	CAM_SFE_IRQ_BUS_REG_STATUS0,
-	CAM_SFE_BUS_IRQ_REGISTERS_MAX,
+enum cam_sfe_bus_wr_irq_regs {
+	CAM_SFE_IRQ_BUS_WR_REG_STATUS0,
+	CAM_SFE_BUS_WR_IRQ_REGISTERS_MAX,
 };
 
 enum cam_sfe_bus_rd_irq_regs {
@@ -205,7 +205,7 @@ struct cam_sfe_top_irq_evt_payload {
 struct cam_sfe_bus_wr_irq_evt_payload {
 	struct list_head           list;
 	uint32_t                   core_index;
-	uint32_t                   irq_reg_val[CAM_SFE_BUS_IRQ_REGISTERS_MAX];
+	uint32_t                   irq_reg_val[CAM_SFE_BUS_WR_IRQ_REGISTERS_MAX];
 	uint32_t                   ccif_violation_status;
 	uint32_t                   overflow_status;
 	uint32_t                   image_size_violation_status;
@@ -224,6 +224,7 @@ struct cam_sfe_bus_wr_irq_evt_payload {
  * @core_index:              Index of SFE HW that generated this IRQ event
  * @irq_reg_val              Bus irq register status
  * @constraint_violation     constraint violation
+ * @ccif_violation:          CCIF violation
  * @error_type:              Identify different errors
  * @evt_id:                  IRQ event
  * @ts:                      Timestamp
@@ -234,6 +235,7 @@ struct cam_sfe_bus_rd_irq_evt_payload {
 	uint32_t                   irq_reg_val[
 		CAM_SFE_BUS_RD_IRQ_REGISTERS_MAX];
 	uint32_t                   constraint_violation;
+	uint32_t                   ccif_violation;
 	uint32_t                   error_type;
 	uint32_t                   evt_id;
 	struct cam_isp_timestamp   ts;

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe680.h

@@ -444,6 +444,47 @@ static struct cam_irq_register_set sfe680_bus_rd_irq_reg[1] = {
 	},
 };
 
+static struct cam_sfe_bus_rd_constraint_error_desc
+	sfe680_bus_rd_cons_error_desc[CAM_SFE_BUS_RD_CONS_ERR_MAX] = {
+	{
+		.bitmask    = BIT(0),
+		.error_desc = "Image Addr Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(1),
+		.error_desc = "Ubwc Addr Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(2),
+		.error_desc = "Stride Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(3),
+		.error_desc = "Y Unit Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(4),
+		.error_desc = "X Unit Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(5),
+		.error_desc = "Image width Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(6),
+		.error_desc = "Image height Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(7),
+		.error_desc = "Meta Stride Unalign Latch",
+	},
+};
+
+static struct cam_sfe_bus_rd_constraint_error_info sfe680_bus_rd_constraint_error_info = {
+	.constraint_error_list = sfe680_bus_rd_cons_error_desc,
+	.num_cons_err          = 8,
+};
+
 static struct cam_sfe_bus_rd_hw_info sfe680_bus_rd_hw_info = {
 	.common_reg = {
 		.hw_version                   = 0x00000400,
@@ -473,6 +514,10 @@ static struct cam_sfe_bus_rd_hw_info sfe680_bus_rd_hw_info = {
 			.unpacker_cfg             = 0x00000468,
 			.latency_buf_allocation   = 0x0000047C,
 			.system_cache_cfg         = 0x0000049C,
+			.debug_status_cfg         = 0x00000490,
+			.debug_status_0           = 0x00000494,
+			.debug_status_1           = 0x00000498,
+			.name                     = "Fetch0",
 		},
 		/* BUS Client 1 */
 		{
@@ -484,6 +529,10 @@ static struct cam_sfe_bus_rd_hw_info sfe680_bus_rd_hw_info = {
 			.unpacker_cfg             = 0x00000508,
 			.latency_buf_allocation   = 0x0000051C,
 			.system_cache_cfg         = 0x0000053C,
+			.debug_status_cfg         = 0x00000530,
+			.debug_status_0           = 0x00000534,
+			.debug_status_1           = 0x00000538,
+			.name                     = "Fetch1",
 		},
 		/* BUS Client 2 */
 		{
@@ -495,6 +544,10 @@ static struct cam_sfe_bus_rd_hw_info sfe680_bus_rd_hw_info = {
 			.unpacker_cfg             = 0x000005A8,
 			.latency_buf_allocation   = 0x000005BC,
 			.system_cache_cfg         = 0x000005DC,
+			.debug_status_cfg         = 0x000005D0,
+			.debug_status_0           = 0x000005D4,
+			.debug_status_1           = 0x000005D8,
+			.name                     = "Fetch2",
 		},
 	},
 	.num_bus_rd_resc = 3,
@@ -526,6 +579,135 @@ static struct cam_sfe_bus_rd_hw_info sfe680_bus_rd_hw_info = {
 	 * the minimum
 	 */
 	.latency_buf_allocation = 2048,
+	.irq_err_mask           = 0x1,
+	.constraint_error_info  = &sfe680_bus_rd_constraint_error_info,
+};
+
+static struct cam_sfe_bus_wr_constraint_error_desc
+	sfe680_bus_wr_cons_error_desc[CAM_SFE_BUS_CONS_ERR_MAX] = {
+	{
+		.bitmask = BIT(0),
+		.error_description = "PPC 1x1 input not supported"
+	},
+	{
+		.bitmask = BIT(1),
+		.error_description = "PPC 1x2 input not supported"
+	},
+	{
+		.bitmask = BIT(2),
+		.error_description = "PPC 2x1 input not supported"
+	},
+	{
+		.bitmask = BIT(3),
+		.error_description = "PPC 2x2 input not supported"
+	},
+	{
+		.bitmask = BIT(4),
+		.error_description = "Pack 8 BPP format not supported"
+	},
+	{
+		.bitmask = BIT(5),
+		.error_description = "Pack 16 format not supported"
+	},
+	{
+		.bitmask = BIT(6),
+		.error_description = "Pack 32 BPP format not supported"
+	},
+	{
+		.bitmask = BIT(7),
+		.error_description = "Pack 64 BPP format not supported"
+	},
+	{
+		.bitmask = BIT(8),
+		.error_description = "Pack MIPI 20 format not supported"
+	},
+	{
+		.bitmask = BIT(9),
+		.error_description = "Pack MIPI 14 format not supported"
+	},
+	{
+		.bitmask = BIT(10),
+		.error_description = "Pack MIPI 12 format not supported"
+	},
+	{
+		.bitmask = BIT(11),
+		.error_description = "Pack MIPI 10 format not supported"
+	},
+	{
+		.bitmask = BIT(12),
+		.error_description = "Pack 128 BPP format not supported"
+	},
+	{
+		.bitmask = BIT(13),
+		.error_description = "UBWC NV12 format not supported"
+	},
+	{
+		.bitmask = BIT(14),
+		.error_description = "UBWC NV12 4R format not supported"
+	},
+	{
+		.bitmask = BIT(15),
+		.error_description = "UBWC TP10 format not supported"
+	},
+	{
+		.bitmask = BIT(16),
+		.error_description = "Frame based Mode not supported"
+	},
+	{
+		.bitmask = BIT(17),
+		.error_description = "Index based Mode not supported"
+	},
+	{
+		.bitmask = BIT(18),
+		.error_description = "FIFO image addr unalign"
+	},
+	{
+		.bitmask = BIT(19),
+		.error_description = "FIFO ubwc addr unalign"
+	},
+	{
+		.bitmask = BIT(20),
+		.error_description = "FIFO frmheader addr unalign"
+	},
+	{
+		.bitmask = BIT(21),
+		.error_description = "Image address unalign"
+	},
+	{
+		.bitmask = BIT(22),
+		.error_description = "UBWC address unalign"
+	},
+	{
+		.bitmask = BIT(23),
+		.error_description = "Frame Header address unalign"
+	},
+	{
+		.bitmask = BIT(24),
+		.error_description = "Stride unalign"
+	},
+	{
+		.bitmask = BIT(25),
+		.error_description = "X Initialization unalign"
+	},
+	{
+		.bitmask = BIT(26),
+		.error_description = "Image Width unalign"
+	},
+	{
+		.bitmask = BIT(27),
+		.error_description = "Image Height unalign"
+	},
+	{
+		.bitmask = BIT(28),
+		.error_description = "Meta Stride unalign"
+	},
+};
+
+static struct cam_sfe_bus_wr_constraint_error_info sfe680_bus_wr_constraint_error_info = {
+	.constraint_error_list   = sfe680_bus_wr_cons_error_desc,
+	.num_cons_err            = 29,
+	.img_addr_unalign_shift  = 21,
+	.img_width_unalign_shift = 26,
 };
 
 static struct cam_irq_register_set sfe680_bus_wr_irq_reg[1] = {
@@ -1107,125 +1289,7 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.name          = "STATS_BHIST_2",
 		},
 	},
-	.num_cons_err = 29,
-	.constraint_error_list = {
-		{
-			.bitmask = BIT(0),
-			.error_description = "PPC 1x1 input not supported"
-		},
-		{
-			.bitmask = BIT(1),
-			.error_description = "PPC 1x2 input not supported"
-		},
-		{
-			.bitmask = BIT(2),
-			.error_description = "PPC 2x1 input not supported"
-		},
-		{
-			.bitmask = BIT(3),
-			.error_description = "PPC 2x2 input not supported"
-		},
-		{
-			.bitmask = BIT(4),
-			.error_description = "Pack 8 BPP format not supported"
-		},
-		{
-			.bitmask = BIT(5),
-			.error_description = "Pack 16 format not supported"
-		},
-		{
-			.bitmask = BIT(6),
-			.error_description = "Pack 32 BPP format not supported"
-		},
-		{
-			.bitmask = BIT(7),
-			.error_description = "Pack 64 BPP format not supported"
-		},
-		{
-			.bitmask = BIT(8),
-			.error_description = "Pack MIPI 20 format not supported"
-		},
-		{
-			.bitmask = BIT(9),
-			.error_description = "Pack MIPI 14 format not supported"
-		},
-		{
-			.bitmask = BIT(10),
-			.error_description = "Pack MIPI 12 format not supported"
-		},
-		{
-			.bitmask = BIT(11),
-			.error_description = "Pack MIPI 10 format not supported"
-		},
-		{
-			.bitmask = BIT(12),
-			.error_description = "Pack 128 BPP format not supported"
-		},
-		{
-			.bitmask = BIT(13),
-			.error_description = "UBWC NV12 format not supported"
-		},
-		{
-			.bitmask = BIT(14),
-			.error_description = "UBWC NV12 4R format not supported"
-		},
-		{
-			.bitmask = BIT(15),
-			.error_description = "UBWC TP10 format not supported"
-		},
-		{
-			.bitmask = BIT(16),
-			.error_description = "Frame based Mode not supported"
-		},
-		{
-			.bitmask = BIT(17),
-			.error_description = "Index based Mode not supported"
-		},
-		{
-			.bitmask = BIT(18),
-			.error_description = "FIFO image addr unalign"
-		},
-		{
-			.bitmask = BIT(19),
-			.error_description = "FIFO ubwc addr unalign"
-		},
-		{
-			.bitmask = BIT(20),
-			.error_description = "FIFO frmheader addr unalign"
-		},
-		{
-			.bitmask = BIT(21),
-			.error_description = "Image address unalign"
-		},
-		{
-			.bitmask = BIT(22),
-			.error_description = "UBWC address unalign"
-		},
-		{
-			.bitmask = BIT(23),
-			.error_description = "Frame Header address unalign"
-		},
-		{
-			.bitmask = BIT(24),
-			.error_description = "Stride unalign"
-		},
-		{
-			.bitmask = BIT(25),
-			.error_description = "X Initialization unalign"
-		},
-		{
-			.bitmask = BIT(26),
-			.error_description = "Image Width unalign"
-		},
-		{
-			.bitmask = BIT(27),
-			.error_description = "Image Height unalign"
-		},
-		{
-			.bitmask = BIT(28),
-			.error_description = "Meta Stride unalign"
-		},
-	},
+	.constraint_error_info = &sfe680_bus_wr_constraint_error_info,
 	.comp_done_shift = {
 		17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
 	},
@@ -1235,6 +1299,7 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 	.max_out_res          = CAM_ISP_SFE_OUT_RES_BASE + 13,
 	.pack_align_shift     = 0x5,
 	.max_bw_counter_limit = 0xFF,
+	.irq_err_mask         = 0xD0000000,
 };
 
 static struct cam_irq_register_set sfe680_top_irq_reg_set[1] = {

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe780.h

@@ -690,6 +690,47 @@ static struct cam_irq_register_set sfe780_bus_rd_irq_reg[1] = {
 	},
 };
 
+static struct cam_sfe_bus_rd_constraint_error_desc
+	sfe780_bus_rd_cons_error_desc[CAM_SFE_BUS_RD_CONS_ERR_MAX] = {
+	{
+		.bitmask    = BIT(0),
+		.error_desc = "Image Addr Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(1),
+		.error_desc = "Ubwc Addr Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(2),
+		.error_desc = "Stride Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(3),
+		.error_desc = "Y Unit Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(4),
+		.error_desc = "X Unit Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(5),
+		.error_desc = "Image width Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(6),
+		.error_desc = "Image height Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(7),
+		.error_desc = "Meta Stride Unalign Latch",
+	},
+};
+
+static struct cam_sfe_bus_rd_constraint_error_info sfe780_bus_rd_constraint_error_info = {
+	.constraint_error_list = sfe780_bus_rd_cons_error_desc,
+	.num_cons_err          = 8,
+};
+
 static struct cam_sfe_bus_rd_hw_info sfe780_bus_rd_hw_info = {
 	.common_reg = {
 		.hw_version                   = 0x00000400,
@@ -719,6 +760,10 @@ static struct cam_sfe_bus_rd_hw_info sfe780_bus_rd_hw_info = {
 			.latency_buf_allocation   = 0x0000047C,
 			.system_cache_cfg         = 0x0000049C,
 			.addr_cfg                 = 0x000004A4,
+			.debug_status_cfg         = 0x00000490,
+			.debug_status_0           = 0x00000494,
+			.debug_status_1           = 0x00000498,
+			.name                     = "Fetch0",
 		},
 		/* BUS Client 1 */
 		{
@@ -731,6 +776,10 @@ static struct cam_sfe_bus_rd_hw_info sfe780_bus_rd_hw_info = {
 			.latency_buf_allocation   = 0x0000051C,
 			.system_cache_cfg         = 0x0000053C,
 			.addr_cfg                 = 0x00000544,
+			.debug_status_cfg         = 0x00000530,
+			.debug_status_0           = 0x00000534,
+			.debug_status_1           = 0x00000538,
+			.name                     = "Fetch1",
 		},
 		/* BUS Client 2 */
 		{
@@ -743,6 +792,10 @@ static struct cam_sfe_bus_rd_hw_info sfe780_bus_rd_hw_info = {
 			.latency_buf_allocation   = 0x000005BC,
 			.system_cache_cfg         = 0x000005DC,
 			.addr_cfg                 = 0x000005E4,
+			.debug_status_cfg         = 0x000005D0,
+			.debug_status_0           = 0x000005D4,
+			.debug_status_1           = 0x000005D8,
+			.name                     = "Fetch2",
 		},
 	},
 	.num_bus_rd_resc = 3,
@@ -766,8 +819,137 @@ static struct cam_sfe_bus_rd_hw_info sfe780_bus_rd_hw_info = {
 			.max_height    = -1,
 		},
 	},
-	.top_irq_shift = 0x1,
+	.top_irq_shift          = 0x1,
 	.latency_buf_allocation = 2048,
+	.irq_err_mask           = 0x1,
+	.constraint_error_info  = &sfe780_bus_rd_constraint_error_info,
+};
+
+static struct cam_sfe_bus_wr_constraint_error_desc
+	sfe780_bus_wr_cons_error_desc[CAM_SFE_BUS_CONS_ERR_MAX] = {
+	{
+		.bitmask = BIT(0),
+		.error_description = "PPC 1x1 input not supported"
+	},
+	{
+		.bitmask = BIT(1),
+		.error_description = "PPC 1x2 input not supported"
+	},
+	{
+		.bitmask = BIT(2),
+		.error_description = "PPC 2x1 input not supported"
+	},
+	{
+		.bitmask = BIT(3),
+		.error_description = "PPC 2x2 input not supported"
+	},
+	{
+		.bitmask = BIT(4),
+		.error_description = "Pack 8 BPP format not supported"
+	},
+	{
+		.bitmask = BIT(5),
+		.error_description = "Pack 16 format not supported"
+	},
+	{
+		.bitmask = BIT(6),
+		.error_description = "Pack 32 BPP format not supported"
+	},
+	{
+		.bitmask = BIT(7),
+		.error_description = "Pack 64 BPP format not supported"
+	},
+	{
+		.bitmask = BIT(8),
+		.error_description = "Pack MIPI 20 format not supported"
+	},
+	{
+		.bitmask = BIT(9),
+		.error_description = "Pack MIPI 14 format not supported"
+	},
+	{
+		.bitmask = BIT(10),
+		.error_description = "Pack MIPI 12 format not supported"
+	},
+	{
+		.bitmask = BIT(11),
+		.error_description = "Pack MIPI 10 format not supported"
+	},
+	{
+		.bitmask = BIT(12),
+		.error_description = "Pack 128 BPP format not supported"
+	},
+	{
+		.bitmask = BIT(13),
+		.error_description = "UBWC NV12 format not supported"
+	},
+	{
+		.bitmask = BIT(14),
+		.error_description = "UBWC NV12 4R format not supported"
+	},
+	{
+		.bitmask = BIT(15),
+		.error_description = "UBWC TP10 format not supported"
+	},
+	{
+		.bitmask = BIT(16),
+		.error_description = "Frame based Mode not supported"
+	},
+	{
+		.bitmask = BIT(17),
+		.error_description = "Index based Mode not supported"
+	},
+	{
+		.bitmask = BIT(18),
+		.error_description = "FIFO image addr unalign"
+	},
+	{
+		.bitmask = BIT(19),
+		.error_description = "FIFO ubwc addr unalign"
+	},
+	{
+		.bitmask = BIT(20),
+		.error_description = "FIFO frmheader addr unalign"
+	},
+	{
+		.bitmask = BIT(21),
+		.error_description = "Image address unalign"
+	},
+	{
+		.bitmask = BIT(22),
+		.error_description = "UBWC address unalign"
+	},
+	{
+		.bitmask = BIT(23),
+		.error_description = "Frame Header address unalign"
+	},
+	{
+		.bitmask = BIT(24),
+		.error_description = "Stride unalign"
+	},
+	{
+		.bitmask = BIT(25),
+		.error_description = "X Initialization unalign"
+	},
+	{
+		.bitmask = BIT(26),
+		.error_description = "Image Width unalign"
+	},
+	{
+		.bitmask = BIT(27),
+		.error_description = "Image Height unalign"
+	},
+	{
+		.bitmask = BIT(28),
+		.error_description = "Meta Stride unalign"
+	},
+};
+
+static struct cam_sfe_bus_wr_constraint_error_info sfe780_bus_wr_constraint_error_info = {
+	.constraint_error_list   = sfe780_bus_wr_cons_error_desc,
+	.num_cons_err            = 29,
+	.img_addr_unalign_shift  = 21,
+	.img_width_unalign_shift = 26,
 };
 
 static struct cam_irq_register_set sfe780_bus_wr_irq_reg[1] = {
@@ -1487,134 +1669,17 @@ static struct cam_sfe_bus_wr_hw_info sfe780_bus_wr_hw_info = {
 			.name          = "STATS_RS_2",
 		},
 	},
-	.num_cons_err = 29,
-	.constraint_error_list = {
-		{
-			.bitmask = BIT(0),
-			.error_description = "PPC 1x1 input not supported"
-		},
-		{
-			.bitmask = BIT(1),
-			.error_description = "PPC 1x2 input not supported"
-		},
-		{
-			.bitmask = BIT(2),
-			.error_description = "PPC 2x1 input not supported"
-		},
-		{
-			.bitmask = BIT(3),
-			.error_description = "PPC 2x2 input not supported"
-		},
-		{
-			.bitmask = BIT(4),
-			.error_description = "Pack 8 BPP format not supported"
-		},
-		{
-			.bitmask = BIT(5),
-			.error_description = "Pack 16 format not supported"
-		},
-		{
-			.bitmask = BIT(6),
-			.error_description = "Pack 32 BPP format not supported"
-		},
-		{
-			.bitmask = BIT(7),
-			.error_description = "Pack 64 BPP format not supported"
-		},
-		{
-			.bitmask = BIT(8),
-			.error_description = "Pack MIPI 20 format not supported"
-		},
-		{
-			.bitmask = BIT(9),
-			.error_description = "Pack MIPI 14 format not supported"
-		},
-		{
-			.bitmask = BIT(10),
-			.error_description = "Pack MIPI 12 format not supported"
-		},
-		{
-			.bitmask = BIT(11),
-			.error_description = "Pack MIPI 10 format not supported"
-		},
-		{
-			.bitmask = BIT(12),
-			.error_description = "Pack 128 BPP format not supported"
-		},
-		{
-			.bitmask = BIT(13),
-			.error_description = "UBWC NV12 format not supported"
-		},
-		{
-			.bitmask = BIT(14),
-			.error_description = "UBWC NV12 4R format not supported"
-		},
-		{
-			.bitmask = BIT(15),
-			.error_description = "UBWC TP10 format not supported"
-		},
-		{
-			.bitmask = BIT(16),
-			.error_description = "Frame based Mode not supported"
-		},
-		{
-			.bitmask = BIT(17),
-			.error_description = "Index based Mode not supported"
-		},
-		{
-			.bitmask = BIT(18),
-			.error_description = "FIFO image addr unalign"
-		},
-		{
-			.bitmask = BIT(19),
-			.error_description = "FIFO ubwc addr unalign"
-		},
-		{
-			.bitmask = BIT(20),
-			.error_description = "FIFO frmheader addr unalign"
-		},
-		{
-			.bitmask = BIT(21),
-			.error_description = "Image address unalign"
-		},
-		{
-			.bitmask = BIT(22),
-			.error_description = "UBWC address unalign"
-		},
-		{
-			.bitmask = BIT(23),
-			.error_description = "Frame Header address unalign"
-		},
-		{
-			.bitmask = BIT(24),
-			.error_description = "Stride unalign"
-		},
-		{
-			.bitmask = BIT(25),
-			.error_description = "X Initialization unalign"
-		},
-		{
-			.bitmask = BIT(26),
-			.error_description = "Image Width unalign"
-		},
-		{
-			.bitmask = BIT(27),
-			.error_description = "Image Height unalign"
-		},
-		{
-			.bitmask = BIT(28),
-			.error_description = "Meta Stride unalign"
-		},
-	},
+	.constraint_error_info = &sfe780_bus_wr_constraint_error_info,
 	.comp_done_shift = {
 		17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
 	},
-	.num_comp_grp         = 10,
-	.line_done_cfg        = 0x11,
-	.top_irq_shift        = 0x0,
-	.max_out_res          = CAM_ISP_SFE_OUT_RES_BASE + 17,
-	.pack_align_shift     = 5,
-	.max_bw_counter_limit = 0xFF,
+	.num_comp_grp              = 10,
+	.line_done_cfg             = 0x11,
+	.top_irq_shift             = 0x0,
+	.max_out_res               = CAM_ISP_SFE_OUT_RES_BASE + 17,
+	.pack_align_shift          = 5,
+	.max_bw_counter_limit      = 0xFF,
+	.irq_err_mask              = 0xD0000000,
 };
 
 static struct cam_irq_register_set sfe780_top_irq_reg_set[1] = {

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe880.h

@@ -727,6 +727,48 @@ static struct cam_irq_register_set sfe880_bus_rd_irq_reg[1] = {
 	},
 };
 
+static struct cam_sfe_bus_rd_constraint_error_desc
+	sfe880_bus_rd_cons_error_desc[CAM_SFE_BUS_RD_CONS_ERR_MAX] = {
+	{
+		.bitmask    = BIT(0),
+		.error_desc = "Image Addr Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(1),
+		.error_desc = "Ubwc Addr Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(2),
+		.error_desc = "Stride Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(3),
+		.error_desc = "Y Unit Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(4),
+		.error_desc = "X Unit Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(5),
+		.error_desc = "Image width Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(6),
+		.error_desc = "Image height Unalign Latch",
+	},
+	{
+		.bitmask    = BIT(7),
+		.error_desc = "Meta Stride Unalign Latch",
+	},
+};
+
+static struct cam_sfe_bus_rd_constraint_error_info sfe880_bus_rd_constraint_error_info = {
+	.constraint_error_list = sfe880_bus_rd_cons_error_desc,
+	.num_cons_err          = 8,
+	.cons_chk_en_avail     = true,
+};
+
 static struct cam_sfe_bus_rd_hw_info sfe880_bus_rd_hw_info = {
 	.common_reg = {
 		.hw_version                   = 0x00000400,
@@ -757,6 +799,10 @@ static struct cam_sfe_bus_rd_hw_info sfe880_bus_rd_hw_info = {
 			.latency_buf_allocation   = 0x0000047C,
 			.system_cache_cfg         = 0x00000490,
 			.addr_cfg                 = 0x00000498,
+			.debug_status_cfg         = 0x000004A4,
+			.debug_status_0           = 0x000004A8,
+			.debug_status_1           = 0x000004AC,
+			.name                     = "Fetch0",
 		},
 		/* BUS Client 1 */
 		{
@@ -769,6 +815,10 @@ static struct cam_sfe_bus_rd_hw_info sfe880_bus_rd_hw_info = {
 			.latency_buf_allocation   = 0x0000051C,
 			.system_cache_cfg         = 0x00000530,
 			.addr_cfg                 = 0x00000538,
+			.debug_status_cfg         = 0x00000544,
+			.debug_status_0           = 0x00000548,
+			.debug_status_1           = 0x0000054C,
+			.name                     = "Fetch1",
 		},
 		/* BUS Client 2 */
 		{
@@ -781,6 +831,10 @@ static struct cam_sfe_bus_rd_hw_info sfe880_bus_rd_hw_info = {
 			.latency_buf_allocation   = 0x000005BC,
 			.system_cache_cfg         = 0x000005D0,
 			.addr_cfg                 = 0x000005D8,
+			.debug_status_cfg         = 0x000005E4,
+			.debug_status_0           = 0x000005E8,
+			.debug_status_1           = 0x000005EC,
+			.name                     = "Fetch2",
 		},
 	},
 	.num_bus_rd_resc = 3,
@@ -804,8 +858,148 @@ static struct cam_sfe_bus_rd_hw_info sfe880_bus_rd_hw_info = {
 			.max_height    = -1,
 		},
 	},
-	.top_irq_shift = 0x1,
+	.top_irq_shift          = 0x1,
 	.latency_buf_allocation = 2048,
+	.irq_err_mask           = 0x80000001,
+	.constraint_error_info  = &sfe880_bus_rd_constraint_error_info,
+};
+
+static struct cam_sfe_bus_wr_constraint_error_desc
+	sfe880_bus_wr_cons_error_desc[CAM_SFE_BUS_CONS_ERR_MAX] = {
+	{
+		.bitmask = BIT(0),
+		.error_description = "PPC 1x1 input not supported"
+	},
+	{
+		.bitmask = BIT(1),
+		.error_description = "PPC 1x2 input not supported"
+	},
+	{
+		.bitmask = BIT(2),
+		.error_description = "PPC 2x1 input not supported"
+	},
+	{
+		.bitmask = BIT(3),
+		.error_description = "PPC 2x2 input not supported"
+	},
+	{
+		.bitmask = BIT(4),
+		.error_description = "Pack 8 BPP format not supported"
+	},
+	{
+		.bitmask = BIT(5),
+		.error_description = "Pack 16 BPP format not supported"
+	},
+	{
+		.bitmask = BIT(6),
+		.error_description = "Pack 24 BPP format not supported"
+	},
+	{
+		.bitmask = BIT(7),
+		.error_description = "Pack 32 BPP format not supported"
+	},
+	{
+		.bitmask = BIT(8),
+		.error_description = "Pack 64 BPP format not supported"
+	},
+	{
+		.bitmask = BIT(9),
+		.error_description = "Pack MIPI 20 format not supported"
+	},
+	{
+		.bitmask = BIT(10),
+		.error_description = "Pack MIPI 14 format not supported"
+	},
+	{
+		.bitmask = BIT(11),
+		.error_description = "Pack MIPI 12 format not supported"
+	},
+	{
+		.bitmask = BIT(12),
+		.error_description = "Pack MIPI 10 format not supported"
+	},
+	{
+		.bitmask = BIT(13),
+		.error_description = "Pack 128 BPP format not supported"
+	},
+	{
+		.bitmask = BIT(14),
+		.error_description = "UBWC P16 format not supported"
+	},
+	{
+		.bitmask = BIT(15),
+		.error_description = "UBWC P10 format not supported"
+	},
+	{
+		.bitmask = BIT(16),
+		.error_description = "UBWC NV12 format not supported"
+	},
+	{
+		.bitmask = BIT(17),
+		.error_description = "UBWC NV12 4R format not supported"
+	},
+	{
+		.bitmask = BIT(18),
+		.error_description = "UBWC TP10 format not supported"
+	},
+	{
+		.bitmask = BIT(19),
+		.error_description = "Frame based Mode not supported"
+	},
+	{
+		.bitmask = BIT(20),
+		.error_description = "Index based Mode not supported"
+	},
+	{
+		.bitmask = BIT(21),
+		.error_description = "FIFO image addr unalign"
+	},
+	{
+		.bitmask = BIT(22),
+		.error_description = "FIFO ubwc addr unalign"
+	},
+	{
+		.bitmask = BIT(23),
+		.error_description = "FIFO frmheader addr unalign"
+	},
+	{
+		.bitmask = BIT(24),
+		.error_description = "Image address unalign"
+	},
+	{
+		.bitmask = BIT(25),
+		.error_description = "UBWC address unalign"
+	},
+	{
+		.bitmask = BIT(26),
+		.error_description = "Frame Header address unalign"
+	},
+	{
+		.bitmask = BIT(27),
+		.error_description = "Stride unalign"
+	},
+	{
+		.bitmask = BIT(28),
+		.error_description = "X Initialization unalign"
+	},
+	{
+		.bitmask = BIT(29),
+		.error_description = "Image Width unalign"
+	},
+	{
+		.bitmask = BIT(30),
+		.error_description = "Image Height unalign"
+	},
+	{
+		.bitmask = BIT(31),
+		.error_description = "Meta Stride unalign"
+	},
+};
+
+static struct cam_sfe_bus_wr_constraint_error_info sfe880_bus_wr_constraint_error_info = {
+	.constraint_error_list   = sfe880_bus_wr_cons_error_desc,
+	.num_cons_err            = 32,
+	.img_width_unalign_shift = 29,
 };
 
 static struct cam_irq_register_set sfe880_bus_wr_irq_reg[1] = {
@@ -1568,134 +1762,17 @@ static struct cam_sfe_bus_wr_hw_info sfe880_bus_wr_hw_info = {
 			.name         = "HDR_STATS"
 		},
 	},
-	.num_cons_err = 29,
-	.constraint_error_list = {
-		{
-			.bitmask = BIT(0),
-			.error_description = "PPC 1x1 input not supported"
-		},
-		{
-			.bitmask = BIT(1),
-			.error_description = "PPC 1x2 input not supported"
-		},
-		{
-			.bitmask = BIT(2),
-			.error_description = "PPC 2x1 input not supported"
-		},
-		{
-			.bitmask = BIT(3),
-			.error_description = "PPC 2x2 input not supported"
-		},
-		{
-			.bitmask = BIT(4),
-			.error_description = "Pack 8 BPP format not supported"
-		},
-		{
-			.bitmask = BIT(5),
-			.error_description = "Pack 16 format not supported"
-		},
-		{
-			.bitmask = BIT(6),
-			.error_description = "Pack 32 BPP format not supported"
-		},
-		{
-			.bitmask = BIT(7),
-			.error_description = "Pack 64 BPP format not supported"
-		},
-		{
-			.bitmask = BIT(8),
-			.error_description = "Pack MIPI 20 format not supported"
-		},
-		{
-			.bitmask = BIT(9),
-			.error_description = "Pack MIPI 14 format not supported"
-		},
-		{
-			.bitmask = BIT(10),
-			.error_description = "Pack MIPI 12 format not supported"
-		},
-		{
-			.bitmask = BIT(11),
-			.error_description = "Pack MIPI 10 format not supported"
-		},
-		{
-			.bitmask = BIT(12),
-			.error_description = "Pack 128 BPP format not supported"
-		},
-		{
-			.bitmask = BIT(13),
-			.error_description = "UBWC NV12 format not supported"
-		},
-		{
-			.bitmask = BIT(14),
-			.error_description = "UBWC NV12 4R format not supported"
-		},
-		{
-			.bitmask = BIT(15),
-			.error_description = "UBWC TP10 format not supported"
-		},
-		{
-			.bitmask = BIT(16),
-			.error_description = "Frame based Mode not supported"
-		},
-		{
-			.bitmask = BIT(17),
-			.error_description = "Index based Mode not supported"
-		},
-		{
-			.bitmask = BIT(18),
-			.error_description = "FIFO image addr unalign"
-		},
-		{
-			.bitmask = BIT(19),
-			.error_description = "FIFO ubwc addr unalign"
-		},
-		{
-			.bitmask = BIT(20),
-			.error_description = "FIFO frmheader addr unalign"
-		},
-		{
-			.bitmask = BIT(21),
-			.error_description = "Image address unalign"
-		},
-		{
-			.bitmask = BIT(22),
-			.error_description = "UBWC address unalign"
-		},
-		{
-			.bitmask = BIT(23),
-			.error_description = "Frame Header address unalign"
-		},
-		{
-			.bitmask = BIT(24),
-			.error_description = "Stride unalign"
-		},
-		{
-			.bitmask = BIT(25),
-			.error_description = "X Initialization unalign"
-		},
-		{
-			.bitmask = BIT(26),
-			.error_description = "Image Width unalign"
-		},
-		{
-			.bitmask = BIT(27),
-			.error_description = "Image Height unalign"
-		},
-		{
-			.bitmask = BIT(28),
-			.error_description = "Meta Stride unalign"
-		},
-	},
+	.constraint_error_info = &sfe880_bus_wr_constraint_error_info,
 	.comp_done_shift = {
 		17, 18, 19, 20, 21, 23, 24, 25, 26, 27, 22,
 	},
-	.num_comp_grp         = 11,
-	.line_done_cfg        = 0x11,
-	.top_irq_shift        = 0x0,
-	.max_out_res          = CAM_ISP_SFE_OUT_RES_BASE + 18,
-	.pack_align_shift     = 5,
-	.max_bw_counter_limit = 0xFF,
+	.num_comp_grp           = 11,
+	.line_done_cfg          = 0x11,
+	.top_irq_shift          = 0x0,
+	.max_out_res            = CAM_ISP_SFE_OUT_RES_BASE + 18,
+	.pack_align_shift       = 5,
+	.max_bw_counter_limit   = 0xFF,
+	.irq_err_mask           = 0xD0000000,
 };
 
 static struct cam_irq_register_set sfe880_top_irq_reg_set[1] = {

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_rd.c

@@ -32,10 +32,6 @@ static const char drv_name[] = "sfe_bus_rd";
 
 #define CAM_SFE_BUS_RD_PAYLOAD_MAX         16
 
-static uint32_t bus_rd_error_irq_mask[1] = {
-	0x00000001,
-};
-
 enum cam_sfe_bus_rd_unpacker_format {
 	BUS_RD_UNPACKER_FMT_PLAIN_128             = 0x0,
 	BUS_RD_UNPACKER_FMT_PLAIN_8               = 0x1,
@@ -75,8 +71,10 @@ struct cam_sfe_bus_rd_common_data {
 	cam_hw_mgr_event_cb_func                    event_cb;
 	bool                                        err_irq_subscribe;
 	uint32_t                                    sfe_debug_cfg;
+	uint32_t                                    irq_err_mask;
 
 	struct cam_sfe_bus_cache_dbg_cfg            cache_dbg_cfg;
+	bool                                        cons_chk_en_avail;
 };
 
 struct cam_sfe_bus_rd_rm_resource_data {
@@ -397,6 +395,71 @@ static int cam_sfe_bus_rd_print_dimensions(
 
 	return 0;
 }
+static void cam_sfe_bus_rd_print_constraint_error(struct cam_sfe_bus_rd_priv *bus_priv,
+	uint32_t cons_err, uint8_t *rm_name)
+{
+	struct cam_sfe_bus_rd_constraint_error_info *cons_err_info;
+	int i;
+
+	cons_err_info = bus_priv->bus_rd_hw_info->constraint_error_info;
+	for (i = 0; i < cons_err_info->num_cons_err; i++) {
+		if (cons_err_info->constraint_error_list[i].bitmask &
+			cons_err)
+			CAM_ERR(CAM_SFE, "RM: %s Error_desc: %s", rm_name,
+				cons_err_info->constraint_error_list[i].error_desc);
+	}
+}
+
+static void cam_sfe_bus_rd_get_constraint_error(struct cam_sfe_bus_rd_priv *bus_priv,
+	uint32_t constraint_err_status)
+{
+	struct cam_isp_resource_node *sfe_bus_rd = NULL;
+	struct cam_sfe_bus_rd_data   *sfe_bus_rd_data = NULL;
+	struct cam_sfe_bus_rd_rm_resource_data *rm_rsrc_data = NULL;
+	uint32_t bus_rd_resc_type, cons_err;
+	uint8_t *rm_name;
+	int i, j;
+
+	for (i = 0; i < bus_priv->num_bus_rd_resc; i++) {
+		bus_rd_resc_type =
+			bus_priv->bus_rd_hw_info->sfe_bus_rd_info[i].sfe_bus_rd_type;
+		if (bus_rd_resc_type < 0 ||
+			bus_rd_resc_type >= CAM_SFE_BUS_RD_MAX) {
+			CAM_ERR(CAM_SFE, "Invalid SFE RD resource type:%d",
+				bus_rd_resc_type);
+			return;
+		}
+
+		sfe_bus_rd = &bus_priv->sfe_bus_rd[bus_rd_resc_type];
+		if (!sfe_bus_rd || !sfe_bus_rd->res_priv) {
+			CAM_DBG(CAM_ISP, "SFE bus rd:%d in resc node or data is NULL", i);
+			continue;
+		}
+
+		sfe_bus_rd_data = sfe_bus_rd->res_priv;
+		for (j = 0; j < sfe_bus_rd_data->num_rm; j++) {
+			rm_rsrc_data = sfe_bus_rd_data->rm_res[j]->res_priv;
+			if (!rm_rsrc_data)
+				continue;
+
+			if (!(constraint_err_status & BIT(rm_rsrc_data->index)))
+				continue;
+
+			rm_name = sfe_bus_rd_data->rm_res[j]->res_name;
+			cons_err = cam_io_r_mb(
+				bus_priv->common_data.mem_base +
+				rm_rsrc_data->hw_regs->debug_status_0);
+			if (!cons_err)
+				continue;
+
+			CAM_ERR(CAM_SFE,
+				"Constraint Violation bitflag: 0x%x bus rd resc type: 0x%x",
+				cons_err, bus_rd_resc_type);
+			cam_sfe_bus_rd_print_constraint_error(bus_priv,
+				cons_err, rm_name);
+		}
+	}
+}
 
 static int cam_sfe_bus_acquire_rm(
 	struct cam_sfe_bus_rd_priv             *bus_rd_priv,
@@ -422,7 +485,7 @@ static int cam_sfe_bus_acquire_rm(
 
 	rm_res_local = &bus_rd_priv->bus_client[rm_idx];
 	if (rm_res_local->res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) {
-		CAM_ERR(CAM_SFE, "SFE:%u RM:%u res not available state:%d",
+		CAM_DBG(CAM_SFE, "SFE:%u RM:%u res not available state:%d",
 			bus_rd_priv->common_data.core_index, rm_idx,
 			rm_res_local->res_state);
 		return -EALREADY;
@@ -484,6 +547,8 @@ static int cam_sfe_bus_start_rm(struct cam_isp_resource_node *rm_res)
 	uint32_t width_in_bytes = 0;
 	struct cam_sfe_bus_rd_rm_resource_data  *rm_data;
 	struct cam_sfe_bus_rd_common_data       *common_data;
+	const uint32_t enable_cons_violation = 11 << 2;
+	uint32_t core_cfg_mask;
 
 	rm_data = rm_res->res_priv;
 	common_data = rm_data->common_data;
@@ -503,8 +568,17 @@ static int cam_sfe_bus_start_rm(struct cam_isp_resource_node *rm_res)
 		rm_data->hw_regs->latency_buf_allocation);
 
 	/* Ignore if already configured via CDM */
-	if (!rm_data->enable_disable_cfg_done)
-		cam_io_w_mb(0x1, common_data->mem_base + rm_data->hw_regs->cfg);
+	if (!rm_data->enable_disable_cfg_done) {
+		core_cfg_mask = CAM_SFE_BUS_RD_EN_CLIENT_CFG;
+		if (common_data->cons_chk_en_avail)
+			core_cfg_mask |= CAM_SFE_BUS_RD_EN_CONS_CHK_CFG;
+		cam_io_w_mb(core_cfg_mask,
+			common_data->mem_base + rm_data->hw_regs->cfg);
+	}
+
+	/* Enable constraint error detection */
+	cam_io_w_mb(enable_cons_violation,
+		common_data->mem_base + rm_data->hw_regs->debug_status_cfg);
 
 	rm_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING;
 
@@ -543,6 +617,7 @@ static int cam_sfe_bus_init_rm_resource(uint32_t index,
 	struct cam_isp_resource_node   *rm_res)
 {
 	struct cam_sfe_bus_rd_rm_resource_data *rsrc_data;
+	uint8_t *name;
 
 	rsrc_data = kzalloc(sizeof(struct cam_sfe_bus_rd_rm_resource_data),
 		GFP_KERNEL);
@@ -563,6 +638,10 @@ static int cam_sfe_bus_init_rm_resource(uint32_t index,
 	rm_res->start = cam_sfe_bus_start_rm;
 	rm_res->stop = cam_sfe_bus_stop_rm;
 	rm_res->hw_intf = bus_rd_priv->common_data.hw_intf;
+	name = bus_rd_priv->bus_rd_hw_info->bus_client_reg[index].name;
+	if (name)
+		scnprintf(rm_res->res_name, CAM_ISP_RES_NAME_LEN,
+			"%s", name);
 
 	return 0;
 }
@@ -646,26 +725,25 @@ static int cam_sfe_bus_rd_out_done_bottom_half(
 	status = evt_payload->irq_reg_val[CAM_SFE_IRQ_BUS_RD_REG_STATUS0];
 	cam_sfe_bus_rd_put_evt_payload(rsrc_data->common_data, &evt_payload);
 
-	if (status & 0x2)
+	if (status & CAM_SFE_BUS_RD_IRQ_RUP_DONE)
 		CAM_DBG(CAM_SFE, "Received SFE:%d BUS RD RUP",
 			rsrc_data->common_data->core_index);
 
-	if (status & 0x4)
+	if (status & CAM_SFE_BUS_RD_IRQ_RD0_BUF_DONE)
 		CAM_DBG(CAM_SFE, "Received SFE:%d BUS RD0 BUF DONE",
 			rsrc_data->common_data->core_index);
 
-	if (status & 0x8)
+	if (status & CAM_SFE_BUS_RD_IRQ_RD1_BUF_DONE)
 		CAM_DBG(CAM_SFE, "Received SFE:%d BUS RD1 BUF DONE",
 			rsrc_data->common_data->core_index);
 
-	if (status & 0x10)
+	if (status & CAM_SFE_BUS_RD_IRQ_RD2_BUF_DONE)
 		CAM_DBG(CAM_SFE, "Received SFE:%d BUS RD2 BUF DONE",
 			rsrc_data->common_data->core_index);
 
 	return rc;
 }
 
-
 static int cam_sfe_bus_rd_handle_irq_top_half(uint32_t evt_id,
 	struct cam_irq_th_payload *th_payload)
 {
@@ -690,28 +768,71 @@ static int cam_sfe_bus_rd_handle_irq_top_half(uint32_t evt_id,
 	evt_payload->constraint_violation = cam_io_r_mb(
 		bus_priv->common_data.mem_base +
 		bus_priv->common_data.common_reg->cons_violation_status);
-	if (evt_payload->constraint_violation) {
-		CAM_ERR(CAM_SFE, "SFE:%d constraint violation:0x%x",
-			bus_priv->common_data.core_index,
-			evt_payload->constraint_violation);
-		cam_irq_controller_disable_all(
-			bus_priv->common_data.bus_irq_controller);
+
+	if (bus_priv->common_data.irq_err_mask
+		& CAM_SFE_BUS_RD_IRQ_CCIF_VIOLATION) {
+		evt_payload->ccif_violation = cam_io_r_mb(
+			bus_priv->common_data.mem_base +
+			bus_priv->common_data.common_reg->ccif_violation_status);
 	}
+	cam_irq_controller_disable_all(bus_priv->common_data.bus_irq_controller);
 
 	cam_isp_hw_get_timestamp(&evt_payload->ts);
 	th_payload->evt_payload_priv = evt_payload;
 	return 0;
 }
 
+static int cam_sfe_bus_rd_get_rsrc_priv_data(struct cam_sfe_bus_rd_priv *bus_priv,
+	uint32_t target_rm_mask, void **rsrc_data_priv)
+{
+	struct cam_sfe_bus_rd_rm_resource_data *rm_rsrc_data;
+	struct cam_isp_resource_node           *sfe_bus_rd;
+	struct cam_sfe_bus_rd_data             *sfe_bus_rd_data;
+	uint32_t bus_rd_resc_type;
+	int i, j;
+
+	if (!bus_priv || !target_rm_mask || !rsrc_data_priv)
+		return -EINVAL;
+
+	for (i = 0; i < bus_priv->num_bus_rd_resc; i++) {
+		bus_rd_resc_type =
+			bus_priv->bus_rd_hw_info->sfe_bus_rd_info[i].sfe_bus_rd_type;
+		if (bus_rd_resc_type < 0 ||
+			(bus_rd_resc_type >= CAM_SFE_BUS_RD_MAX)) {
+			CAM_ERR(CAM_SFE, "Invalid SFE RD resource type:%d",
+				bus_rd_resc_type);
+			return -EINVAL;
+		}
+		sfe_bus_rd = &bus_priv->sfe_bus_rd[bus_rd_resc_type];
+		if (!sfe_bus_rd || !sfe_bus_rd->res_priv) {
+			CAM_DBG(CAM_SFE,
+				"SFE bus rd:%d in resc node or data is NULL", i);
+			continue;
+		}
+		sfe_bus_rd_data = sfe_bus_rd->res_priv;
+		for (j = 0; j < sfe_bus_rd_data->num_rm; j++) {
+			rm_rsrc_data = sfe_bus_rd_data->rm_res[j]->res_priv;
+			if (!rm_rsrc_data)
+				continue;
+			if (target_rm_mask & BIT(rm_rsrc_data->index)) {
+				*rsrc_data_priv = sfe_bus_rd_data->priv;
+				return 0;
+			}
+		}
+	}
+	return 0;
+}
+
 static int cam_sfe_bus_rd_handle_irq_bottom_half(
 	void  *handler_priv, void *evt_payload_priv)
 {
-	struct cam_sfe_bus_rd_irq_evt_payload *evt_payload;
-	struct cam_sfe_bus_rd_priv            *bus_priv;
-	struct cam_sfe_bus_rd_common_data     *common_data = NULL;
-	struct cam_isp_hw_event_info           evt_info;
-	struct cam_isp_hw_error_event_info     err_evt_info;
-	uint32_t status = 0, constraint_violation = 0;
+	struct cam_sfe_bus_rd_irq_evt_payload  *evt_payload;
+	struct cam_sfe_bus_rd_priv             *bus_priv;
+	struct cam_sfe_bus_rd_common_data      *common_data = NULL;
+	struct cam_isp_hw_event_info            evt_info;
+	struct cam_isp_hw_error_event_info      err_evt_info;
+	uint32_t status, constraint_violation, ccif_violation;
+	void *rsrc_data_priv = NULL;
 
 	if (!handler_priv || !evt_payload_priv)
 		return -EINVAL;
@@ -721,25 +842,50 @@ static int cam_sfe_bus_rd_handle_irq_bottom_half(
 	common_data = &bus_priv->common_data;
 	status = evt_payload->irq_reg_val[CAM_SFE_IRQ_BUS_RD_REG_STATUS0];
 	constraint_violation = evt_payload->constraint_violation;
+	ccif_violation = evt_payload->ccif_violation;
 	cam_sfe_bus_rd_put_evt_payload(common_data, &evt_payload);
 
-	if (status & 0x1) {
-		CAM_ERR(CAM_SFE, "SFE:%d Constraint violation status:0x%x",
+	if (!(status & bus_priv->common_data.irq_err_mask))
+		return 0;
+
+	if (status & CAM_SFE_BUS_RD_IRQ_CONS_VIOLATION) {
+		CAM_ERR(CAM_SFE, "SFE:[%d] Constraint Violation status 0x%x",
 			bus_priv->common_data.core_index,
 			constraint_violation);
+		cam_sfe_bus_rd_get_constraint_error(bus_priv,
+			constraint_violation);
+		cam_sfe_bus_rd_get_rsrc_priv_data(bus_priv, constraint_violation,
+			&rsrc_data_priv);
+	}
 
-		evt_info.hw_type  = CAM_ISP_HW_TYPE_SFE;
-		evt_info.hw_idx = bus_priv->common_data.core_index;
-		evt_info.res_type = CAM_ISP_RESOURCE_SFE_RD;
-		evt_info.res_id = CAM_SFE_BUS_RD_MAX;
-		err_evt_info.err_type = CAM_SFE_IRQ_STATUS_VIOLATION;
-		evt_info.event_data = (void *)&err_evt_info;
+	if (status & CAM_SFE_BUS_RD_IRQ_CCIF_VIOLATION) {
+		CAM_ERR(CAM_SFE, "SFE:[%d] CCIF Violation status 0x%x",
+			bus_priv->common_data.core_index,
+			ccif_violation);
+		cam_sfe_bus_rd_get_rsrc_priv_data(bus_priv, ccif_violation,
+			&rsrc_data_priv);
+	}
 
-		if (common_data->event_cb)
-			common_data->event_cb(NULL,
-				CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info);
+	if (!common_data->event_cb)
+		return 0;
+
+	evt_info.hw_type  = CAM_ISP_HW_TYPE_SFE;
+	evt_info.hw_idx = bus_priv->common_data.core_index;
+	evt_info.res_type = CAM_ISP_RESOURCE_SFE_RD;
+	evt_info.res_id = CAM_SFE_BUS_RD_MAX;
+	err_evt_info.err_type = CAM_SFE_IRQ_STATUS_VIOLATION;
+	evt_info.event_data = (void *)&err_evt_info;
+
+	if (!rsrc_data_priv) {
+		CAM_WARN(CAM_SFE,
+			"SFE:[%d] bus rd error notification failed, cb data is NULL",
+			bus_priv->common_data.core_index);
+		return 0;
 	}
 
+	common_data->event_cb(rsrc_data_priv,
+		CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info);
+
 	return 0;
 }
 
@@ -747,6 +893,7 @@ static int cam_sfe_bus_subscribe_error_irq(
 	struct cam_sfe_bus_rd_priv          *bus_priv)
 {
 	uint32_t sfe_top_irq_mask[CAM_SFE_IRQ_REGISTERS_MAX] = {0};
+	uint32_t bus_rd_err_irq_mask[CAM_SFE_BUS_RD_IRQ_REGISTERS_MAX] = {0};
 
 	/* Subscribe top IRQ */
 	sfe_top_irq_mask[0] = (1 << bus_priv->top_irq_shift);
@@ -773,10 +920,12 @@ static int cam_sfe_bus_subscribe_error_irq(
 		bus_priv->common_data.bus_irq_controller, sfe_top_irq_mask);
 
 	if (bus_priv->tasklet_info != NULL) {
+		bus_rd_err_irq_mask[0] = bus_priv->common_data.irq_err_mask;
+
 		bus_priv->error_irq_handle = cam_irq_controller_subscribe_irq(
 			bus_priv->common_data.bus_irq_controller,
 			CAM_IRQ_PRIORITY_0,
-			bus_rd_error_irq_mask,
+			bus_rd_err_irq_mask,
 			bus_priv,
 			cam_sfe_bus_rd_handle_irq_top_half,
 			cam_sfe_bus_rd_handle_irq_bottom_half,
@@ -1495,9 +1644,10 @@ static int cam_sfe_bus_rd_update_rm_core_cfg(
 	struct cam_sfe_bus_rd_data             *sfe_bus_rd_data = NULL;
 	struct cam_sfe_bus_rd_rm_resource_data *rm_data = NULL;
 	struct cam_cdm_utils_ops               *cdm_util_ops;
-	bool      enable_disable = false;
+	bool enable_disable;
 	uint32_t *reg_val_pair;
 	uint32_t  num_regval_pairs = 0, i, j, size = 0;
+	uint32_t hw_cfg = 0;
 
 	bus_priv   = (struct cam_sfe_bus_rd_priv  *) priv;
 	cmd_update =  (struct cam_isp_hw_get_cmd_update *) cmd_args;
@@ -1512,6 +1662,12 @@ static int cam_sfe_bus_rd_update_rm_core_cfg(
 		return -EINVAL;
 	}
 
+	if (enable_disable) {
+		hw_cfg = CAM_SFE_BUS_RD_EN_CLIENT_CFG;
+		if (sfe_bus_rd_data->common_data->cons_chk_en_avail)
+			hw_cfg |= CAM_SFE_BUS_RD_EN_CONS_CHK_CFG;
+	}
+
 	cdm_util_ops = sfe_bus_rd_data->cdm_util_ops;
 	if (!cdm_util_ops) {
 		CAM_ERR(CAM_SFE, "Invalid cdm ops: %pK",
@@ -1533,7 +1689,7 @@ static int cam_sfe_bus_rd_update_rm_core_cfg(
 		rm_data->enable_disable_cfg_done = true;
 
 		CAM_SFE_ADD_REG_VAL_PAIR(reg_val_pair, j,
-			rm_data->hw_regs->cfg, enable_disable);
+			rm_data->hw_regs->cfg, hw_cfg);
 		CAM_DBG(CAM_SFE, "SFE:%d RM:%d cfg:0x%x",
 			rm_data->common_data->core_index,
 			rm_data->index, reg_val_pair[j-1]);
@@ -1845,6 +2001,9 @@ int cam_sfe_bus_rd_init(
 	bus_priv->common_data.hw_intf           = hw_intf;
 	bus_priv->common_data.sfe_irq_controller = sfe_irq_controller;
 	bus_priv->common_data.common_reg        = &bus_rd_hw_info->common_reg;
+	bus_priv->common_data.irq_err_mask      = bus_rd_hw_info->irq_err_mask;
+	bus_priv->common_data.cons_chk_en_avail =
+		bus_rd_hw_info->constraint_error_info->cons_chk_en_avail;
 	bus_priv->top_irq_shift                 = bus_rd_hw_info->top_irq_shift;
 	bus_priv->latency_buf_allocation        = bus_rd_hw_info->latency_buf_allocation;
 	bus_priv->bus_rd_hw_info = bus_rd_hw_info;

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_rd.h

@@ -9,7 +9,20 @@
 
 #include "cam_sfe_bus.h"
 
-#define CAM_SFE_BUS_RD_MAX_CLIENTS 3
+#define CAM_SFE_BUS_RD_MAX_CLIENTS        3
+#define CAM_SFE_BUS_RD_CONS_ERR_MAX       32
+
+/* IRQ status bits */
+#define CAM_SFE_BUS_RD_IRQ_CONS_VIOLATION BIT(0)
+#define CAM_SFE_BUS_RD_IRQ_RUP_DONE       BIT(1)
+#define CAM_SFE_BUS_RD_IRQ_RD0_BUF_DONE   BIT(2)
+#define CAM_SFE_BUS_RD_IRQ_RD1_BUF_DONE   BIT(3)
+#define CAM_SFE_BUS_RD_IRQ_RD2_BUF_DONE   BIT(4)
+#define CAM_SFE_BUS_RD_IRQ_CCIF_VIOLATION BIT(31)
+
+/* Client core config selection */
+#define CAM_SFE_BUS_RD_EN_CLIENT_CFG      BIT(0)
+#define CAM_SFE_BUS_RD_EN_CONS_CHK_CFG    BIT(2)
 
 enum cam_sfe_bus_rd_type {
 	CAM_SFE_BUS_RD_RDI0,
@@ -18,6 +31,33 @@ enum cam_sfe_bus_rd_type {
 	CAM_SFE_BUS_RD_MAX,
 };
 
+/*
+ * struct cam_sfe_bus_rd_constraint_error_desc:
+ *
+ * @Brief:        Constraint error description
+ */
+struct cam_sfe_bus_rd_constraint_error_desc {
+	uint32_t bitmask;
+	char    *error_desc;
+};
+
+/*
+ * struct cam_sfe_bus_rd_constraint_error_info
+ *
+ * @Brief:        Constraint error info
+ *
+ * @constraint_error_list: Error description for various constraint errors.
+ * @num_cons_err:          Number of constraint violation errors.
+ * @cons_chk_en_avail:     Indicate if there is an option to enable constraint checker
+ *                         violation in core cfg reg for each client.
+ */
+struct cam_sfe_bus_rd_constraint_error_info {
+	struct cam_sfe_bus_rd_constraint_error_desc
+		*constraint_error_list;
+	uint32_t num_cons_err;
+	bool cons_chk_en_avail;
+};
+
 /*
  * struct cam_sfe_bus_rd_reg_offset_common:
  *
@@ -50,6 +90,10 @@ struct cam_sfe_bus_rd_reg_offset_bus_client {
 	uint32_t latency_buf_allocation;
 	uint32_t system_cache_cfg;
 	uint32_t addr_cfg;
+	uint32_t debug_status_cfg;
+	uint32_t debug_status_0;
+	uint32_t debug_status_1;
+	char    *name;
 };
 
 /*
@@ -76,6 +120,8 @@ struct cam_sfe_bus_rd_info {
  * @sfe_bus_rd_info:        SFE bus rd client info
  * @top_irq_shift:          Top irq shift val
  * @latency_buf_allocation: latency buf allocation
+ * @irq_err_mask:           IRQ error mask
+ * @constraint_error_info:  constraint violation errors info
  */
 struct cam_sfe_bus_rd_hw_info {
 	struct cam_sfe_bus_rd_reg_offset_common common_reg;
@@ -87,6 +133,8 @@ struct cam_sfe_bus_rd_hw_info {
 		sfe_bus_rd_info[CAM_SFE_BUS_RD_MAX];
 	uint32_t top_irq_shift;
 	uint32_t latency_buf_allocation;
+	uint32_t irq_err_mask;
+	struct cam_sfe_bus_rd_constraint_error_info *constraint_error_info;
 };
 
 /*

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.c

@@ -38,10 +38,6 @@ static const char drv_name[] = "sfe_bus_wr";
 #define MAX_REG_VAL_PAIR_SIZE    \
 	(MAX_BUF_UPDATE_REG_NUM * 2 * CAM_PACKET_MAX_PLANES)
 
-static uint32_t bus_wr_error_irq_mask[1] = {
-	0xD0000000,
-};
-
 enum cam_sfe_bus_wr_packer_format {
 	PACKER_FMT_PLAIN_128,
 	PACKER_FMT_PLAIN_8,
@@ -93,6 +89,7 @@ struct cam_sfe_bus_wr_common_data {
 	uint32_t                                    max_bw_counter_limit;
 	bool                                        err_irq_subscribe;
 	cam_hw_mgr_event_cb_func                    event_cb;
+	uint32_t                                    irq_err_mask;
 
 	uint32_t                                    sfe_debug_cfg;
 	struct cam_sfe_bus_cache_dbg_cfg            cache_dbg_cfg;
@@ -199,9 +196,8 @@ struct cam_sfe_bus_wr_priv {
 	int                                 bus_irq_handle;
 	int                                 error_irq_handle;
 	void                               *tasklet_info;
-	uint32_t                            num_cons_err;
-	struct cam_sfe_constraint_error_info      *constraint_error_list;
-	struct cam_sfe_bus_sfe_out_hw_info        *sfe_out_hw_info;
+	struct cam_sfe_bus_wr_constraint_error_info *constraint_error_info;
+	struct cam_sfe_bus_sfe_out_hw_info   *sfe_out_hw_info;
 };
 
 static int cam_sfe_bus_subscribe_error_irq(
@@ -447,17 +443,18 @@ static void cam_sfe_bus_wr_print_constraint_errors(
 	uint8_t *wm_name,
 	uint32_t constraint_errors)
 {
+	struct cam_sfe_bus_wr_constraint_error_info *constraint_err_info;
 	uint32_t i;
 
-	CAM_INFO(CAM_ISP, "Constraint violation bitflags: 0x%X",
+	CAM_ERR(CAM_ISP, "Constraint violation bitflags: 0x%X",
 		constraint_errors);
 
-	for (i = 0; i < bus_priv->num_cons_err; i++) {
-		if (bus_priv->constraint_error_list[i].bitmask &
+	constraint_err_info = bus_priv->constraint_error_info;
+	for (i = 0; i < constraint_err_info->num_cons_err; i++) {
+		if (constraint_err_info->constraint_error_list[i].bitmask &
 			constraint_errors) {
-			CAM_INFO(CAM_ISP, "WM: %s %s",
-				wm_name, bus_priv->constraint_error_list[i]
-				.error_description);
+			CAM_ERR(CAM_SFE, "WM: %s Error_desc: %s", wm_name,
+				constraint_err_info->constraint_error_list[i].error_description);
 		}
 	}
 }
@@ -466,11 +463,16 @@ static void cam_sfe_bus_wr_get_constraint_errors(
 	bool                       *skip_error_notify,
 	struct cam_sfe_bus_wr_priv *bus_priv)
 {
-	uint32_t i, j, constraint_errors, sfe_out_type;
+	uint32_t i, j, cons_err, sfe_out_type;
 	uint8_t *wm_name = NULL;
 	struct cam_isp_resource_node              *out_rsrc_node = NULL;
 	struct cam_sfe_bus_wr_out_data            *out_rsrc_data = NULL;
 	struct cam_sfe_bus_wr_wm_resource_data    *wm_data   = NULL;
+	struct cam_sfe_bus_wr_common_data         *common_data = NULL;
+	struct cam_sfe_bus_wr_constraint_error_info      *cons_err_info = NULL;
+	bool out_rsrc_is_rdi;
+
+	cons_err_info = bus_priv->constraint_error_info;
 
 	for (i = 0; i < bus_priv->num_out; i++) {
 		sfe_out_type = cam_sfe_bus_wr_get_out_type(bus_priv, i);
@@ -489,32 +491,52 @@ static void cam_sfe_bus_wr_get_constraint_errors(
 		}
 
 		out_rsrc_data = out_rsrc_node->res_priv;
+		common_data = out_rsrc_data->common_data;
+
+		if ((out_rsrc_data->out_type >= CAM_SFE_BUS_SFE_OUT_RDI0) &&
+			(out_rsrc_data->out_type <= CAM_SFE_BUS_SFE_OUT_RDI4))
+			out_rsrc_is_rdi = true;
+		else
+			out_rsrc_is_rdi = false;
+
 		for (j = 0; j < out_rsrc_data->num_wm; j++) {
 			wm_data = out_rsrc_data->wm_res[j].res_priv;
 			wm_name = out_rsrc_data->wm_res[j].res_name;
-			if (wm_data) {
-				constraint_errors = cam_io_r_mb(
-					bus_priv->common_data.mem_base +
-					wm_data->hw_regs->debug_status_1);
-				if (!constraint_errors)
-					continue;
+			if (!wm_data)
+				continue;
 
-				/*
-				 * Due to a HW bug in constraint checker skip addr unalign
-				 * for RDI clients
-				 */
-				if ((out_rsrc_data->out_type >= CAM_SFE_BUS_SFE_OUT_RDI0) &&
-					(out_rsrc_data->out_type <= CAM_SFE_BUS_SFE_OUT_RDI4) &&
-					(constraint_errors >> 21)) {
-					*skip_error_notify = true;
-					CAM_DBG(CAM_SFE, "WM: %s constraint_error: 0x%x",
-						wm_name, constraint_errors);
-					continue;
-				}
+			cons_err = cam_io_r_mb(common_data->mem_base +
+				wm_data->hw_regs->debug_status_1);
+			if (!cons_err)
+				continue;
+
+			/*
+			 * Due to HW bug in constraint checker which signals false alert,
+			 * skip image addr unalign constraint error for RDI WMs on
+			 * SFE v780 or older and skip image width unalign constraint error
+			 * for any WM when programmed in frame base mode.
+			 */
+
+			if (out_rsrc_is_rdi && (cons_err &
+				BIT(cons_err_info->img_addr_unalign_shift))) {
+				*skip_error_notify = true;
+				CAM_DBG(CAM_SFE,
+					"Ignoring Image Addr Unalign error on SFE[%u] out rsrc: %u WM: %s",
+				common_data->core_index, out_rsrc_data->out_type, wm_name);
+				continue;
+			}
 
-				cam_sfe_bus_wr_print_constraint_errors(
-					bus_priv, wm_name, constraint_errors);
+			if ((cons_err & BIT(cons_err_info->img_width_unalign_shift)) &&
+				(wm_data->en_cfg & BIT(16))) {
+				*skip_error_notify = true;
+				CAM_DBG(CAM_SFE,
+					"Ignoring Image Width Unalign error on SFE[%u] out rsrc: %u WM: %s in frame based mode",
+					common_data->core_index, out_rsrc_data->out_type, wm_name);
+				continue;
 			}
+
+			cam_sfe_bus_wr_print_constraint_errors(
+				bus_priv, wm_name, cons_err);
 		}
 	}
 }
@@ -1776,7 +1798,7 @@ static int cam_sfe_bus_handle_sfe_out_done_top_half(
 
 	th_payload->evt_payload_priv = evt_payload;
 
-	status_0 = th_payload->evt_status_arr[CAM_SFE_IRQ_BUS_REG_STATUS0];
+	status_0 = th_payload->evt_status_arr[CAM_SFE_IRQ_BUS_WR_REG_STATUS0];
 
 	if (status_0 & BIT(resource_data->comp_done_shift)) {
 		trace_cam_log_event("bufdone", "bufdone_IRQ",
@@ -1808,7 +1830,7 @@ static int cam_sfe_bus_handle_comp_done_bottom_half(
 	}
 
 	cam_sfe_irq_regs = evt_payload->irq_reg_val;
-	status_0 = cam_sfe_irq_regs[CAM_SFE_IRQ_BUS_REG_STATUS0];
+	status_0 = cam_sfe_irq_regs[CAM_SFE_IRQ_BUS_WR_REG_STATUS0];
 
 	if (status_0 & BIT(rsrc_data->comp_done_shift)) {
 		evt_payload->evt_id = CAM_ISP_HW_EVENT_DONE;
@@ -2313,7 +2335,7 @@ static int cam_sfe_bus_wr_irq_bottom_half(
 	void *handler_priv, void *evt_payload_priv)
 {
 	int i;
-	uint32_t status = 0, cons_violation = 0;
+	uint32_t status = 0;
 	bool skip_err_notify = false;
 	struct cam_sfe_bus_wr_priv            *bus_priv = handler_priv;
 	struct cam_sfe_bus_wr_common_data     *common_data;
@@ -2325,22 +2347,27 @@ static int cam_sfe_bus_wr_irq_bottom_half(
 
 	common_data = &bus_priv->common_data;
 
-	status = evt_payload->irq_reg_val[CAM_SFE_IRQ_BUS_REG_STATUS0];
-	cons_violation = (status >> 28) & 0x1;
+	status = evt_payload->irq_reg_val[CAM_SFE_IRQ_BUS_WR_REG_STATUS0];
 
-	CAM_ERR(CAM_SFE,
-		"SFE:%d status0 0x%x Image Size violation status 0x%x CCIF violation status 0x%x",
-		bus_priv->common_data.core_index, status,
-		evt_payload->image_size_violation_status,
-		evt_payload->ccif_violation_status);
+	if (status & CAM_SFE_BUS_WR_IRQ_CCIF_VIOLATION)
+		CAM_ERR(CAM_SFE, "SFE:%d status0 0x%x CCIF Violation status 0x%x",
+			bus_priv->common_data.core_index, status,
+			evt_payload->ccif_violation_status);
 
-	if (evt_payload->image_size_violation_status)
+	if (status & CAM_SFE_BUS_WR_IRQ_IMAGE_SIZE_VIOLATION) {
+		CAM_ERR(CAM_SFE, "SFE:%d status0 0x%x Image Size Violation status 0x%x",
+			bus_priv->common_data.core_index, status,
+			evt_payload->image_size_violation_status);
 		cam_sfe_bus_wr_print_violation_info(
 			evt_payload->image_size_violation_status,
 			bus_priv);
+	}
 
-	if (cons_violation)
+	if (status & CAM_SFE_BUS_WR_IRQ_CONS_VIOLATION) {
+		CAM_ERR(CAM_SFE, "SFE:%d status0 0x%x Constraint Violation",
+			bus_priv->common_data.core_index, status);
 		cam_sfe_bus_wr_get_constraint_errors(&skip_err_notify, bus_priv);
+	}
 
 	cam_sfe_bus_wr_put_evt_payload(common_data, &evt_payload);
 
@@ -2390,13 +2417,17 @@ static int cam_sfe_bus_wr_irq_bottom_half(
 static int cam_sfe_bus_subscribe_error_irq(
 	struct cam_sfe_bus_wr_priv          *bus_priv)
 {
+	struct cam_sfe_bus_wr_common_data *common_data;
 	uint32_t top_irq_reg_mask[CAM_SFE_IRQ_REGISTERS_MAX] = {0};
+	uint32_t bus_wr_error_irq_mask[CAM_SFE_BUS_WR_IRQ_REGISTERS_MAX] = {0};
 
 	/* Subscribe top IRQ */
 	top_irq_reg_mask[0] = (1 << bus_priv->top_irq_shift);
 
+	common_data = &bus_priv->common_data;
+
 	bus_priv->bus_irq_handle = cam_irq_controller_subscribe_irq(
-		bus_priv->common_data.sfe_irq_controller,
+		common_data->sfe_irq_controller,
 		CAM_IRQ_PRIORITY_0,
 		top_irq_reg_mask,
 		bus_priv,
@@ -2412,12 +2443,14 @@ static int cam_sfe_bus_subscribe_error_irq(
 		return -EFAULT;
 	}
 
-	cam_irq_controller_register_dependent(bus_priv->common_data.sfe_irq_controller,
-		bus_priv->common_data.bus_irq_controller, top_irq_reg_mask);
+	cam_irq_controller_register_dependent(common_data->sfe_irq_controller,
+		common_data->bus_irq_controller, top_irq_reg_mask);
 
 	if (bus_priv->tasklet_info != NULL) {
+		bus_wr_error_irq_mask[0] = common_data->irq_err_mask;
+
 		bus_priv->error_irq_handle = cam_irq_controller_subscribe_irq(
-			bus_priv->common_data.bus_irq_controller,
+			common_data->bus_irq_controller,
 			CAM_IRQ_PRIORITY_0,
 			bus_wr_error_irq_mask,
 			bus_priv,
@@ -2434,7 +2467,7 @@ static int cam_sfe_bus_subscribe_error_irq(
 		}
 	}
 
-	bus_priv->common_data.err_irq_subscribe = true;
+	common_data->err_irq_subscribe = true;
 	CAM_DBG(CAM_SFE, "BUS WR error irq subscribed");
 	return 0;
 }
@@ -3447,9 +3480,9 @@ int cam_sfe_bus_wr_init(
 	bus_priv->common_data.max_bw_counter_limit = hw_info->max_bw_counter_limit;
 	bus_priv->common_data.err_irq_subscribe    = false;
 	bus_priv->common_data.sfe_irq_controller   = sfe_irq_controller;
-	bus_priv->num_cons_err = hw_info->num_cons_err;
-	bus_priv->constraint_error_list = hw_info->constraint_error_list;
-	bus_priv->sfe_out_hw_info = hw_info->sfe_out_hw_info;
+	bus_priv->common_data.irq_err_mask         = hw_info->irq_err_mask;
+	bus_priv->constraint_error_info            = hw_info->constraint_error_info;
+	bus_priv->sfe_out_hw_info                  = hw_info->sfe_out_hw_info;
 	rc = cam_cpas_get_cpas_hw_version(&bus_priv->common_data.hw_version);
 	if (rc) {
 		CAM_ERR(CAM_SFE, "Failed to get hw_version rc:%d", rc);

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.h

@@ -14,6 +14,10 @@
 #define CAM_SFE_BUS_WR_MAX_SUB_GRPS       6
 #define CAM_SFE_BUS_CONS_ERR_MAX          32
 
+#define CAM_SFE_BUS_WR_IRQ_CONS_VIOLATION       BIT(28)
+#define CAM_SFE_BUS_WR_IRQ_CCIF_VIOLATION       BIT(30)
+#define CAM_SFE_BUS_WR_IRQ_IMAGE_SIZE_VIOLATION BIT(31)
+
 enum cam_sfe_bus_wr_src_grp {
 	CAM_SFE_BUS_WR_SRC_GRP_0,
 	CAM_SFE_BUS_WR_SRC_GRP_1,
@@ -62,15 +66,31 @@ enum cam_sfe_bus_sfe_out_type {
 };
 
 /*
- * struct cam_sfe_constraint_error_info:
+ * struct cam_sfe_constraint_error_desc:
  *
- * @Brief:        Constraint error info
+ * @Brief:        Constraint error desc
  */
-struct cam_sfe_constraint_error_info {
+struct cam_sfe_bus_wr_constraint_error_desc {
 	uint32_t  bitmask;
 	char     *error_description;
 };
 
+/*
+ * @brief:        Constraint error info
+ *
+ * @error_desc: Error description for various constraint errors.
+ * @num_cons_err: Number of constraint errors
+ * @img_addr_unalign_shift: shift for image address unalign error
+ * @img_width_unalign_shift: shift for image width unalign error
+ *
+ */
+struct cam_sfe_bus_wr_constraint_error_info {
+	struct cam_sfe_bus_wr_constraint_error_desc *constraint_error_list;
+	uint32_t num_cons_err;
+	uint32_t img_addr_unalign_shift;
+	uint32_t img_width_unalign_shift;
+};
+
 /*
  * struct cam_sfe_bus_reg_offset_common:
  *
@@ -152,20 +172,20 @@ struct cam_sfe_bus_sfe_out_hw_info {
  *
  * @Brief:            HW register info for entire Bus
  *
- * @common_reg:            Common register details
- * @num_client:            Total number of write clients
- * @bus_client_reg:        Bus client register info
- * @sfe_out_hw_info:       SFE output capability
- * @num_cons_err:          Number of contraint errors in list
- * @constraint_error_list: Static list of all constraint errors
- * @comp_done_shift:       List of buf done mask shift values for
- *                         each comp grp
- * @num_comp_grp:          Number of composite groups
- * @line_done_cfg:         Line done cfg for wr/rd sync
- * @top_irq_shift:         Mask shift for top level BUS WR irq
- * @max_out_res:           maximum number of sfe out res in uapi
- * @pack_align_shift:      Packer format alignment bit shift
- * @max_bw_counter_limit:  Max BW counter limit
+ * @common_reg:                Common register details
+ * @num_client:                Total number of write clients
+ * @bus_client_reg:            Bus client register info
+ * @sfe_out_hw_info:           SFE output capability
+ * @constraint_error_info:     Constraint Error information
+ * @comp_done_shift:           List of buf done mask shift values for
+ *                             each comp grp
+ * @num_comp_grp:              Number of composite groups
+ * @line_done_cfg:             Line done cfg for wr/rd sync
+ * @top_irq_shift:             Mask shift for top level BUS WR irq
+ * @max_out_res:               maximum number of sfe out res in uapi
+ * @pack_align_shift:          Packer format alignment bit shift
+ * @max_bw_counter_limit:      Max BW counter limit
+ * @irq_err_mask:              IRQ error mask
  */
 struct cam_sfe_bus_wr_hw_info {
 	struct cam_sfe_bus_reg_offset_common common_reg;
@@ -175,9 +195,8 @@ struct cam_sfe_bus_wr_hw_info {
 	uint32_t num_out;
 	struct cam_sfe_bus_sfe_out_hw_info
 		sfe_out_hw_info[CAM_SFE_BUS_SFE_OUT_MAX];
-	uint32_t num_cons_err;
-	struct cam_sfe_constraint_error_info
-		constraint_error_list[CAM_SFE_BUS_CONS_ERR_MAX];
+	struct cam_sfe_bus_wr_constraint_error_info
+		*constraint_error_info;
 	uint32_t comp_done_shift[CAM_SFE_BUS_WR_COMP_GRP_MAX];
 	uint32_t num_comp_grp;
 	uint32_t line_done_cfg;
@@ -185,6 +204,7 @@ struct cam_sfe_bus_wr_hw_info {
 	uint32_t max_out_res;
 	uint32_t pack_align_shift;
 	uint32_t max_bw_counter_limit;
+	uint32_t irq_err_mask;
 };
 
 /*

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_top/cam_sfe_top.c

@@ -1153,8 +1153,9 @@ int cam_sfe_top_reserve(void *device_priv,
 
 	if (top_priv->reserve_cnt) {
 		if (top_priv->priv_per_stream != args->priv) {
-			CAM_ERR(CAM_SFE,
-				"Acquiring same SFE[%u] HW res: %u for different streams");
+			CAM_DBG(CAM_SFE,
+				"Acquiring same SFE[%u] HW res: %u for different streams",
+				top_priv->common_data.hw_intf->hw_idx, acquire_args->res_id);
 			rc = -EINVAL;
 			return rc;
 		}