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msm: camera: common: Improve the CSID logging

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Improve CSID irq logging for better debugging.
Add support to dump the hw source clock.

CRs-Fixed: 2808577
Change-Id: I06608588ef7a6e0ebc174a1ba138f6e16a9094f2
Signed-off-by: Jigar Agrawal <jigar@codeaurora.org>
This commit is contained in:
Jigar Agrawal
2020-12-08 13:11:52 -08:00
parent c17872806b
commit 28a19c52e1
18 changed files with 330 additions and 112 deletions
Download Patch File Download Diff File Expand all files Collapse all files

65
drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c
View File

@@ -345,6 +345,41 @@ static int cam_ife_hw_mgr_is_rdi_res(uint32_t res_id)
return rc;
}
static int cam_ife_hw_mgr_dump_hw_src_clock(uint8_t hw_idx,
enum cam_isp_hw_type hw_type)
{
struct cam_isp_hw_intf_data *hw_intf_data = NULL;
struct cam_hw_intf *hw_intf = NULL;
uint8_t dummy_args;
switch (hw_type) {
case CAM_ISP_HW_TYPE_VFE:
if (!g_ife_hw_mgr.ife_devices[hw_idx]) {
CAM_ERR(CAM_ISP, "No vfe device added yet");
return -ENODEV;
}
hw_intf_data = g_ife_hw_mgr.ife_devices[hw_idx];
if (!hw_intf_data->hw_intf) {
CAM_ERR(CAM_ISP, "hw_intf is null");
return -EINVAL;
}
hw_intf = hw_intf_data->hw_intf;
if (hw_intf->hw_ops.process_cmd) {
hw_intf->hw_ops.process_cmd(hw_intf->hw_priv,
CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE,
(void *)&dummy_args, sizeof(uint8_t));
}
break;
default:
CAM_ERR(CAM_ISP, "Unsupported HW Type: %u", hw_type);
}
return 0;
}
static enum cam_ife_pix_path_res_id
cam_ife_hw_mgr_get_csid_rdi_type_for_offline(
uint32_t rd_res_type)
@@ -10116,20 +10151,26 @@ static int cam_ife_hw_mgr_handle_csid_error(
struct cam_isp_hw_error_event_data error_event_data = {0};
struct cam_ife_hw_event_recovery_data recovery_data = {0};
switch (event_info->err_type) {
if ((event_info->err_type & CAM_ISP_HW_ERROR_CSID_FATAL) &&
g_ife_hw_mgr.debug_cfg.enable_csid_recovery) {
case CAM_ISP_HW_ERROR_CSID_FATAL:
if (!g_ife_hw_mgr.debug_cfg.enable_csid_recovery)
break;
error_event_data.error_type = event_info->err_type;
cam_ife_hw_mgr_find_affected_ctx(&error_event_data,
event_info->hw_idx, &recovery_data);
break;
default:
CAM_ERR(CAM_ISP, "Invalid event ID %d",
}
if (event_info->err_type & CAM_ISP_HW_ERROR_CSID_OVERFLOW) {
if (cam_ife_hw_mgr_dump_hw_src_clock(event_info->hw_idx,
CAM_ISP_HW_TYPE_VFE))
CAM_ERR_RATE_LIMIT(CAM_ISP,
"VFE%d src_clk_rate dump failed");
}
if (event_info->err_type & ~(CAM_ISP_HW_ERROR_CSID_FATAL |
CAM_ISP_HW_ERROR_CSID_OVERFLOW)) {
CAM_ERR(CAM_ISP, "Invalid event ID 0x%x",
event_info->err_type);
rc = -EINVAL;
break;
}
return rc;
@@ -10197,8 +10238,9 @@ static int cam_ife_hw_mgr_handle_csid_event(
{
int rc = 0;
switch (evt_id) {
CAM_DBG(CAM_ISP, "CSID event %u", evt_id);
switch (evt_id) {
case CAM_ISP_HW_EVENT_ERROR:
rc = cam_ife_hw_mgr_handle_csid_error(event_info);
break;
@@ -10209,8 +10251,6 @@ static int cam_ife_hw_mgr_handle_csid_event(
break;
}
CAM_DBG(CAM_ISP, "CSID event %u", evt_id);
return rc;
}
@@ -10307,7 +10347,8 @@ static int cam_ife_hw_mgr_handle_hw_err(
spin_lock(&g_ife_hw_mgr.ctx_lock);
if (event_info->err_type == CAM_ISP_HW_ERROR_CSID_FATAL) {
if (event_info->err_type & (CAM_ISP_HW_ERROR_CSID_FATAL |
CAM_ISP_HW_ERROR_CSID_OVERFLOW)) {
rc = cam_ife_hw_mgr_handle_csid_event(ctx, event_info,
evt_id);
goto end;

14
drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h
View File

@@ -57,13 +57,13 @@ enum cam_isp_hw_event_type {
* ISP hardware event CAM_ISP_HW_EVENT_ERROR
*/
enum cam_isp_hw_err_type {
CAM_ISP_HW_ERROR_NONE,
CAM_ISP_HW_ERROR_OVERFLOW,
CAM_ISP_HW_ERROR_P2I_ERROR,
CAM_ISP_HW_ERROR_VIOLATION,
CAM_ISP_HW_ERROR_BUSIF_OVERFLOW,
CAM_ISP_HW_ERROR_CSID_FATAL,
CAM_ISP_HW_ERROR_MAX,
CAM_ISP_HW_ERROR_NONE = 0x0001,
CAM_ISP_HW_ERROR_OVERFLOW = 0x0002,
CAM_ISP_HW_ERROR_P2I_ERROR = 0x0004,
CAM_ISP_HW_ERROR_VIOLATION = 0x0008,
CAM_ISP_HW_ERROR_BUSIF_OVERFLOW = 0x0010,
CAM_ISP_HW_ERROR_CSID_FATAL = 0x0020,
CAM_ISP_HW_ERROR_CSID_OVERFLOW = 0x0040,
};
/**

4
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid480.h
View File

@@ -412,8 +412,8 @@ static struct cam_ife_csid_csi2_rx_reg_info
.lane_cfg_shift = 4,
.phy_type_shift = 24,
.phy_num_shift = 20,
.fatal_err_mask = 0x78000,
.part_fatal_err_mask = 0x1801800,
.fatal_err_mask = 0x4078000,
.part_fatal_err_mask = 0x1983800,
.non_fatal_err_mask = 0x380000,
};

1
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.h
View File

@@ -46,6 +46,7 @@
#define CAM_IFE_CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE BIT(6)
#define CAM_IFE_CSID_DEBUG_ENABLE_HBI_VBI_INFO BIT(7)
#define CAM_IFE_CSID_DEBUG_DISABLE_EARLY_EOF BIT(8)
#define CAM_IFE_DEBUG_ENABLE_UNMAPPED_VC_DT_IRQ BIT(9)
/* Binning supported masks. Binning support changes for specific paths
* and also for targets. With the mask, we handle the supported features

159
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.c
View File

@@ -48,28 +48,28 @@
static const struct cam_ife_csid_irq_desc ver1_rx_irq_desc[] = {
{
.desc = "DL0_EOT",
.desc = "PHY_DL0_EOT_CAPTURED",
},
{
.desc = "DL1_EOT",
.desc = "PHY_DL1_EOT_CAPTURED",
},
{
.desc = "DL2_EOT",
.desc = "PHY_DL2_EOT_CAPTURED",
},
{
.desc = "DL3_EOT",
.desc = "PHY_DL3_EOT_CAPTURED",
},
{
.desc = "DL0_SOT",
.desc = "PHY_DL0_SOT_CAPTURED",
},
{
.desc = "DL1_SOT",
.desc = "PHY_DL1_SOT_CAPTURED",
},
{
.desc = "DL2_SOT",
.desc = "PHY_DL2_SOT_CAPTURED",
},
{
.desc = "DL3_SOT",
.desc = "PHY_DL3_SOT_CAPTURED",
},
{
.desc = "LONG_PKT",
@@ -81,13 +81,13 @@ static const struct cam_ife_csid_irq_desc ver1_rx_irq_desc[] = {
.desc = "CPHY_PKT_HDR",
},
{
.desc = "ERROR_CPHY_EOT_RECEPTION",
.desc = "CPHY_EOT_RECEPTION: No EOT on lane/s",
},
{
.desc = "ERROR_CPHY_SOT_RECEPTION",
.desc = "CPHY_SOT_RECEPTION: Less SOTs on lane/s",
},
{
.desc = "ERROR_CPHY_PH_CRC",
.desc = "CSID:%d CPHY_PH_CRC CPHY: Pkt Hdr CRC mismatch",
},
{
.desc = "WARNING_ECC",
@@ -135,7 +135,7 @@ static const struct cam_ife_csid_irq_desc ver1_path_irq_desc[] = {
.desc = "Reset_Done",
},
{
.desc = "ERROR_FIFO_OVERFLOW",
.desc = "PATH_ERROR_O/P_FIFO_OVERFLOW: Slow IFE read",
},
{
.desc = "SUBSAMPLED_EOF",
@@ -173,18 +173,19 @@ static const struct cam_ife_csid_irq_desc ver1_path_irq_desc[] = {
{
.desc = "ERROR_LINE_COUNT",
},
{
.desc = "PATH_ERROR_CCIF_VIOLATION: Bad frame timings",
},
{
.desc = "FRAME_DROP",
},
{
.desc = "OVERFLOW_RECOVERY",
.desc =
"PATH_OVERFLOW_RECOVERY: Back pressure/output fifo ovrfl",
},
{
.desc = "ERROR_REC_CCIF_VIOLATION",
},
{
.desc = "CCIF_VIOLATION",
},
{
.desc = "VCDT_GRP0_SEL",
},
@@ -248,6 +249,10 @@ static int cam_ife_csid_ver1_set_debug(
csid_hw->debug_info.rx_mask |=
IFE_CSID_VER1_RX_CPHY_PKT_HDR_CAPTURED;
break;
case CAM_IFE_DEBUG_ENABLE_UNMAPPED_VC_DT_IRQ:
csid_hw->debug_info.rx_mask |=
IFE_CSID_VER1_RX_UNMAPPED_VC_DT;
break;
default:
break;
}
@@ -3814,6 +3819,16 @@ static int cam_ife_csid_ver1_handle_rx_debug_event(
val & csi2_reg->dt_mask,
val & csi2_reg->wc_mask);
break;
case IFE_CSID_VER1_RX_UNMAPPED_VC_DT:
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
csi2_reg->captured_long_pkt_0_addr);
CAM_ERR_RATE_LIMIT(CAM_ISP,
"CSID:%d UNMAPPED_VC_DT: VC:%d DT:%d WC:%d not mapped to any csid paths",
csid_hw->hw_intf->hw_idx, (val >> 22),
((val >> 16) & 0x3F), (val & 0xFFFF));
csid_hw->counters.error_irq_count++;
break;
default:
CAM_INFO_RATE_LIMIT(CAM_ISP,
"CSID[%d] RX_IRQ: %s",
@@ -3828,27 +3843,20 @@ static int cam_ife_csid_ver1_handle_rx_debug_event(
static int cam_ife_csid_ver1_handle_event_err(
struct cam_ife_csid_ver1_hw *csid_hw,
struct cam_ife_csid_ver1_evt_payload *evt_payload,
int err_type)
uint32_t err_type)
{
struct cam_isp_hw_event_info event_info;
int rc = 0;
int dummy = 0;
event_info.err_type = err_type;
event_info.hw_idx = evt_payload->hw_idx;
event_info.err_type = err_type;
switch (err_type) {
CAM_DBG(CAM_ISP, "CSID[%d] Error type %d",
csid_hw->hw_intf->hw_idx, err_type);
case CAM_ISP_HW_ERROR_CSID_FATAL:
rc = csid_hw->event_cb(NULL,
rc = csid_hw->event_cb((void *)&dummy,
CAM_ISP_HW_EVENT_ERROR, (void *)&event_info);
break;
default:
CAM_DBG(CAM_ISP, "CSID[%d] invalid error type %d",
csid_hw->hw_intf->hw_idx,
err_type);
break;
}
return rc;
}
@@ -3906,7 +3914,10 @@ static int cam_ife_csid_ver1_rx_bottom_half_handler(
struct cam_ife_csid_ver1_reg_info *csid_reg;
uint8_t *log_buf = NULL;
uint32_t irq_status;
uint32_t val;
uint32_t event_type = 0;
size_t len = 0;
struct cam_hw_soc_info *soc_info;
if (!csid_hw || !evt_payload) {
CAM_ERR(CAM_ISP,
@@ -3915,6 +3926,7 @@ static int cam_ife_csid_ver1_rx_bottom_half_handler(
return -EINVAL;
}
soc_info = &csid_hw->hw_info->soc_info;
csid_reg = (struct cam_ife_csid_ver1_reg_info *)
csid_hw->core_info->csid_reg;
csi2_reg = csid_reg->csi2_reg;
@@ -3925,26 +3937,40 @@ static int cam_ife_csid_ver1_rx_bottom_half_handler(
memset(log_buf, 0, sizeof(csid_hw->log_buf));
if (irq_status) {
cam_ife_csid_ver1_disable_csi2(csid_hw);
len += scnprintf(log_buf, CAM_IFE_CSID_LOG_BUF_LEN - len,
"Overflow:\n ");
if (irq_status & IFE_CSID_VER1_RX_LANE0_FIFO_OVERFLOW)
len += scnprintf(log_buf + len,
CAM_IFE_CSID_LOG_BUF_LEN - len, "LANE_0\n");
CAM_IFE_CSID_LOG_BUF_LEN - len,
"RX_ERROR_LANE0_FIFO_OVERFLOW: Skew/Less Data on lanes/ Slow csid clock:%luHz\n",
soc_info->applied_src_clk_rate);
if (irq_status & IFE_CSID_VER1_RX_LANE1_FIFO_OVERFLOW)
len += scnprintf(log_buf + len,
CAM_IFE_CSID_LOG_BUF_LEN - len, "LANE_1\n");
CAM_IFE_CSID_LOG_BUF_LEN - len,
"RX_ERROR_LANE1_FIFO_OVERFLOW: Skew/Less Data on lanes/ Slow csid clock:%luHz\n",
soc_info->applied_src_clk_rate);
if (irq_status & IFE_CSID_VER1_RX_LANE2_FIFO_OVERFLOW)
len += scnprintf(log_buf + len,
CAM_IFE_CSID_LOG_BUF_LEN - len, "LANE_2\n");
CAM_IFE_CSID_LOG_BUF_LEN - len,
"RX_ERROR_LANE2_FIFO_OVERFLOW: Skew/Less Data on lanes/ Slow csid clock:%luHz\n",
soc_info->applied_src_clk_rate);
if (irq_status & IFE_CSID_VER1_RX_LANE3_FIFO_OVERFLOW)
len += scnprintf(log_buf + len,
CAM_IFE_CSID_LOG_BUF_LEN - len, "LANE_3\n");
CAM_IFE_CSID_LOG_BUF_LEN - len,
"RX_ERROR_LANE3_FIFO_OVERFLOW: Skew/Less Data on lanes/ Slow csid clock:%luHz\n",
soc_info->applied_src_clk_rate);
if (irq_status & IFE_CSID_VER1_RX_TG_FIFO_OVERFLOW) {
event_type |= CAM_ISP_HW_ERROR_CSID_OVERFLOW;
len += scnprintf(log_buf + len,
CAM_IFE_CSID_LOG_BUF_LEN - len,
"RX_ERROR_TPG_FIFO_OVERFLOW: Backpressure from IFE\n");
}
}
irq_status = evt_payload->irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
@@ -3955,25 +3981,56 @@ static int cam_ife_csid_ver1_rx_bottom_half_handler(
len += scnprintf(log_buf, CAM_IFE_CSID_LOG_BUF_LEN - len,
"Part-fatal-errors:\n");
if (irq_status & IFE_CSID_VER1_RX_CPHY_EOT_RECEPTION)
if ((irq_status & IFE_CSID_VER1_RX_CPHY_EOT_RECEPTION) &&
(!csid_hw->rx_cfg.epd_supported))
len += scnprintf(log_buf + len,
CAM_IFE_CSID_LOG_BUF_LEN - len,
"CPHY_EOT_RECEPTION\n");
"CPHY_EOT_RECEPTION: No EOT on lane/s\n");
if (irq_status & IFE_CSID_VER1_RX_CPHY_SOT_RECEPTION)
len += scnprintf(log_buf + len,
CAM_IFE_CSID_LOG_BUF_LEN - len,
"CPHY_SOT_RECEPTION\n");
"CPHY_SOT_RECEPTION: Less SOTs on lane/s\n");
if (irq_status & IFE_CSID_VER1_RX_STREAM_UNDERFLOW)
if (irq_status & IFE_CSID_VER1_RX_CPHY_PH_CRC)
len += scnprintf(log_buf + len,
CAM_IFE_CSID_LOG_BUF_LEN - len,
"STREAM_UNDERFLOW\n");
"CPHY_PH_CRC CPHY: Pkt Hdr CRC mismatch\n");
if (irq_status & IFE_CSID_VER1_RX_ERROR_CRC)
len += scnprintf(log_buf + len,
CAM_IFE_CSID_LOG_BUF_LEN - len,
"ERROR_CRC CPHY: Long pkt payload CRC mismatch\n");
if (irq_status & IFE_CSID_VER1_RX_ERROR_ECC)
len += scnprintf(log_buf + len,
CAM_IFE_CSID_LOG_BUF_LEN - len,
"ERROR_ECC: Dphy pkt hdr errors unrecoverable\n");
if (irq_status & IFE_CSID_VER1_RX_MMAPPED_VC_DT) {
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
csi2_reg->captured_long_pkt_0_addr);
len += scnprintf(log_buf + len,
CAM_IFE_CSID_LOG_BUF_LEN - len,
"MMAPPED_VC_DT: VC:%d DT:%d mapped to more than 1 csid paths\n",
(val >> 22), ((val >> 16) & 0x3F));
}
if (irq_status & IFE_CSID_VER1_RX_STREAM_UNDERFLOW) {
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
csi2_reg->captured_long_pkt_0_addr);
len += scnprintf(log_buf + len,
CAM_IFE_CSID_LOG_BUF_LEN - len,
"ERROR_STREAM_UNDERFLOW: Fewer bytes rcvd than WC:%d in pkt hdr\n",
val & 0xFFFF);
}
if (irq_status & IFE_CSID_VER1_RX_UNBOUNDED_FRAME)
len += scnprintf(log_buf + len,
CAM_IFE_CSID_LOG_BUF_LEN - len,
"UNBOUNDED_FRAME\n");
"UNBOUNDED_FRAME: Frame started with EOF or No EOF\n");
}
if (len)
@@ -3981,8 +4038,11 @@ static int cam_ife_csid_ver1_rx_bottom_half_handler(
csid_hw->hw_intf->hw_idx, log_buf);
if (csid_hw->flags.fatal_err_detected)
event_type |= CAM_ISP_HW_ERROR_CSID_FATAL;
if (event_type)
cam_ife_csid_ver1_handle_event_err(csid_hw,
evt_payload, CAM_ISP_HW_ERROR_CSID_FATAL);
evt_payload, event_type);
return IRQ_HANDLED;
}
@@ -4028,6 +4088,11 @@ static int cam_ife_csid_ver1_path_bottom_half_handler(
irq_reg_tag[index],
log_buf);
if (evt_payload->irq_status[index] &
IFE_CSID_VER1_PATH_ERROR_FIFO_OVERFLOW)
cam_ife_csid_ver1_handle_event_err(csid_hw,
evt_payload, CAM_ISP_HW_ERROR_CSID_OVERFLOW);
return 0;
}
@@ -4156,12 +4221,22 @@ static int cam_ife_csid_ver1_rx_top_half(
if (status & csi2_reg->part_fatal_err_mask) {
if (status & IFE_CSID_VER1_RX_CPHY_EOT_RECEPTION)
if ((status & IFE_CSID_VER1_RX_CPHY_EOT_RECEPTION) &&
(!csid_hw->rx_cfg.epd_supported))
csid_hw->counters.error_irq_count++;
if (status & IFE_CSID_VER1_RX_CPHY_SOT_RECEPTION)
csid_hw->counters.error_irq_count++;
if (status & IFE_CSID_VER1_RX_CPHY_PH_CRC)
csid_hw->counters.error_irq_count++;
if (status & IFE_CSID_VER1_RX_ERROR_CRC)
csid_hw->counters.error_irq_count++;
if (status & IFE_CSID_VER1_RX_ERROR_ECC)
csid_hw->counters.error_irq_count++;
if (status & IFE_CSID_VER1_RX_STREAM_UNDERFLOW)
csid_hw->counters.error_irq_count++;

2
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.h
View File

@@ -25,7 +25,7 @@
#define IFE_CSID_VER1_RX_LANE1_FIFO_OVERFLOW BIT(16)
#define IFE_CSID_VER1_RX_LANE2_FIFO_OVERFLOW BIT(17)
#define IFE_CSID_VER1_RX_LANE3_FIFO_OVERFLOW BIT(18)
#define IFE_CSID_VER1_RX_CRC BIT(19)
#define IFE_CSID_VER1_RX_ERROR_CRC BIT(19)
#define IFE_CSID_VER1_RX_ERROR_ECC BIT(20)
#define IFE_CSID_VER1_RX_MMAPPED_VC_DT BIT(21)
#define IFE_CSID_VER1_RX_UNMAPPED_VC_DT BIT(22)

1
drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h
View File

@@ -147,6 +147,7 @@ enum cam_isp_hw_cmd_type {
CAM_ISP_HW_CMD_CSID_MUP_UPDATE,
CAM_ISP_HW_CMD_BUF_UPDATE,
CAM_ISP_HW_CMD_BUF_UPDATE_RM,
CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE,
CAM_ISP_HW_CMD_MAX,
};

4
drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#include <linux/iopoll.h>
@@ -75,7 +75,7 @@ static int cam_csid_ppi_enable_hw(struct cam_csid_ppi_hw *ppi_hw)
for (i = 0; i < soc_info->num_clk; i++) {
rc = cam_soc_util_clk_enable(soc_info->clk[i],
soc_info->clk_name[i], 0);
soc_info->clk_name[i], 0, NULL);
if (rc)
goto clk_disable;
}

4
drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/slab.h>
@@ -199,7 +199,7 @@ int cam_tfe_soc_enable_clk(struct cam_hw_soc_info *soc_info,
if (strcmp(clk_name, CAM_TFE_DSP_CLK_NAME) == 0) {
rc = cam_soc_util_clk_enable(soc_private->dsp_clk,
CAM_TFE_DSP_CLK_NAME, soc_private->dsp_clk_rate);
CAM_TFE_DSP_CLK_NAME, soc_private->dsp_clk_rate, NULL);
if (rc)
CAM_ERR(CAM_ISP,
"Error enable dsp clk failed rc=%d", rc);

3
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/delay.h>
@@ -509,6 +509,7 @@ int cam_vfe_process_cmd(void *hw_priv, uint32_t cmd_type,
case CAM_ISP_HW_CMD_ADD_WAIT:
case CAM_ISP_HW_CMD_ADD_WAIT_TRIGGER:
case CAM_ISP_HW_CMD_CAMIF_DATA:
case CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE:
case CAM_ISP_HW_CMD_BLANKING_UPDATE:
rc = core_info->vfe_top->hw_ops.process_cmd(
core_info->vfe_top->top_priv, cmd_type, cmd_args,

4
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/slab.h>
@@ -307,7 +307,7 @@ int cam_vfe_soc_enable_clk(struct cam_hw_soc_info *soc_info,
}
rc = cam_soc_util_clk_enable(soc_private->dsp_clk,
CAM_VFE_DSP_CLK_NAME, soc_private->dsp_clk_rate);
CAM_VFE_DSP_CLK_NAME, soc_private->dsp_clk_rate, NULL);
if (rc)
CAM_ERR(CAM_ISP,
"Error enable dsp clk failed rc=%d", rc);

28
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/slab.h>
@@ -169,6 +169,29 @@ static int cam_vfe_top_clock_update(
return rc;
}
static int cam_vfe_top_dump_info(
struct cam_vfe_top_ver2_priv *top_priv, uint32_t cmd_type)
{
struct cam_hw_soc_info *soc_info = top_priv->common_data.soc_info;
if (!soc_info) {
CAM_ERR(CAM_ISP, "Null soc_info");
return -EINVAL;
}
switch (cmd_type) {
case CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE:
CAM_INFO_RATE_LIMIT(CAM_ISP, "VFE%d src_clk_rate:%luHz",
soc_info->index, soc_info->applied_src_clk_rate);
break;
default:
CAM_ERR(CAM_ISP, "cmd_type: %u not supported", cmd_type);
break;
}
return 0;
}
static int cam_vfe_top_blanking_update(uint32_t cmd_type,
void *cmd_args, uint32_t arg_size)
{
@@ -794,6 +817,9 @@ int cam_vfe_top_process_cmd(void *device_priv, uint32_t cmd_type,
rc = cam_vfe_top_clock_update(top_priv, cmd_args,
arg_size);
break;
case CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE:
rc = cam_vfe_top_dump_info(top_priv, cmd_type);
break;
case CAM_ISP_HW_CMD_FE_UPDATE_IN_RD:
rc = cam_vfe_top_fs_update(top_priv, cmd_args,
arg_size);

29
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/slab.h>
@@ -190,6 +190,30 @@ static int cam_vfe_top_ver3_clock_update(
return rc;
}
static int cam_vfe_top_ver3_dump_info(
struct cam_vfe_top_ver3_priv *top_priv, uint32_t cmd_type)
{
struct cam_hw_soc_info *soc_info = top_priv->common_data.soc_info;
if (!soc_info) {
CAM_ERR(CAM_ISP, "Null soc_info");
return -EINVAL;
}
switch (cmd_type) {
case CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE:
CAM_INFO_RATE_LIMIT(CAM_ISP, "VFE%d src_clk_rate:%luHz",
soc_info->index, soc_info->applied_src_clk_rate);
break;
default:
CAM_ERR(CAM_ISP, "cmd_type: %u not supported", cmd_type);
break;
}
return 0;
}
static int cam_vfe_top_ver3_blanking_update(uint32_t cmd_type,
void *cmd_args, uint32_t arg_size)
{
@@ -731,6 +755,9 @@ int cam_vfe_top_ver3_process_cmd(void *device_priv, uint32_t cmd_type,
rc = cam_vfe_top_ver3_clock_update(top_priv, cmd_args,
arg_size);
break;
case CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE:
rc = cam_vfe_top_ver3_dump_info(top_priv, cmd_type);
break;
case CAM_ISP_HW_CMD_FE_UPDATE_IN_RD:
rc = cam_vfe_top_fs_update(top_priv, cmd_args,
arg_size);

26
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c
View File

@@ -246,6 +246,29 @@ static int cam_vfe_top_ver4_clock_update(
return rc;
}
static int cam_vfe_top_ver4_dump_info(
struct cam_vfe_top_ver4_priv *top_priv, uint32_t cmd_type)
{
struct cam_hw_soc_info *soc_info = top_priv->common_data.soc_info;
if (!soc_info) {
CAM_ERR(CAM_ISP, "Null soc_info");
return -EINVAL;
}
switch (cmd_type) {
case CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE:
CAM_INFO_RATE_LIMIT(CAM_ISP, "VFE%d src_clk_rate:%luHz",
soc_info->index, soc_info->applied_src_clk_rate);
break;
default:
CAM_ERR(CAM_ISP, "cmd_type: %u not supported", cmd_type);
break;
}
return 0;
}
static int cam_vfe_core_config_control(
struct cam_vfe_top_ver4_priv *top_priv,
void *cmd_args, uint32_t arg_size)
@@ -633,6 +656,9 @@ int cam_vfe_top_ver4_process_cmd(void *device_priv, uint32_t cmd_type,
rc = cam_vfe_top_ver4_clock_update(top_priv, cmd_args,
arg_size);
break;
case CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE:
rc = cam_vfe_top_ver4_dump_info(top_priv, cmd_type);
break;
case CAM_ISP_HW_CMD_FE_UPDATE_IN_RD:
rc = cam_vfe_top_fs_update(top_priv, cmd_args,
arg_size);

4
drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/
#include "cam_csiphy_soc.h"
@@ -130,8 +130,6 @@ int32_t cam_csiphy_status_dmp(struct csiphy_device *csiphy_dev)
return rc;
}
enum cam_vote_level get_clk_vote_default(struct csiphy_device *csiphy_dev,
int32_t index)
{

5
drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
@@ -2098,7 +2098,8 @@ int cam_sensor_core_power_up(struct cam_sensor_power_ctrl_t *ctrl,
for (j = 0; j < soc_info->num_clk; j++) {
rc = cam_soc_util_clk_enable(soc_info->clk[j],
soc_info->clk_name[j],
soc_info->clk_rate[0][j]);
soc_info->clk_rate[0][j],
NULL);
if (rc)
break;
}

38
drivers/cam_utils/cam_soc_util.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/of.h>
@@ -365,15 +365,16 @@ long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info,
*
* @clk: Clock structure information for which rate is to be set
* @clk_name: Name of the clock for which rate is being set
* @clk_rate Clock rate to be set
* @clk_rate: Clock rate to be set
* @applied_clk_rate: Final clock rate set to the clk
*
* @return: Success or failure
*/
static int cam_soc_util_set_clk_rate(struct clk *clk, const char *clk_name,
int64_t clk_rate)
int64_t clk_rate, unsigned long *applied_clk_rate)
{
int rc = 0;
long clk_rate_round;
long clk_rate_round = -1;
if (!clk || !clk_name)
return -EINVAL;
@@ -410,6 +411,9 @@ static int cam_soc_util_set_clk_rate(struct clk *clk, const char *clk_name,
}
}
if (applied_clk_rate)
*applied_clk_rate = clk_rate_round;
return rc;
}
@@ -458,7 +462,8 @@ int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info,
}
rc = cam_soc_util_set_clk_rate(clk,
soc_info->clk_name[src_clk_idx], clk_rate);
soc_info->clk_name[src_clk_idx], clk_rate,
&soc_info->applied_src_clk_rate);
if (rc) {
CAM_ERR(CAM_UTIL,
"SET_RATE Failed: src clk: %s, rate %lld, dev_name = %s rc: %d",
@@ -478,7 +483,8 @@ int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info,
clk = soc_info->clk[scl_clk_idx];
rc = cam_soc_util_set_clk_rate(clk,
soc_info->clk_name[scl_clk_idx],
soc_info->clk_rate[apply_level][scl_clk_idx]);
soc_info->clk_rate[apply_level][scl_clk_idx],
NULL);
if (rc) {
CAM_WARN(CAM_UTIL,
"SET_RATE Failed: scl clk: %s, rate %d dev_name = %s, rc: %d",
@@ -585,14 +591,15 @@ int cam_soc_util_get_option_clk_by_name(struct cam_hw_soc_info *soc_info,
}
int cam_soc_util_clk_enable(struct clk *clk, const char *clk_name,
int32_t clk_rate)
int32_t clk_rate, unsigned long *applied_clock_rate)
{
int rc = 0;
if (!clk || !clk_name)
return -EINVAL;
rc = cam_soc_util_set_clk_rate(clk, clk_name, clk_rate);
rc = cam_soc_util_set_clk_rate(clk, clk_name, clk_rate,
applied_clock_rate);
if (rc)
return rc;
@@ -632,6 +639,7 @@ int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
{
int i, rc = 0;
enum cam_vote_level apply_level;
unsigned long applied_clk_rate;
if ((soc_info->num_clk == 0) ||
(soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
@@ -651,9 +659,14 @@ int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
for (i = 0; i < soc_info->num_clk; i++) {
rc = cam_soc_util_clk_enable(soc_info->clk[i],
soc_info->clk_name[i],
soc_info->clk_rate[apply_level][i]);
soc_info->clk_rate[apply_level][i],
&applied_clk_rate);
if (rc)
goto clk_disable;
if (i == soc_info->src_clk_idx)
soc_info->applied_src_clk_rate = applied_clk_rate;
if (soc_info->cam_cx_ipeak_enable) {
CAM_DBG(CAM_UTIL,
"dev name = %s clk name = %s idx = %d\n"
@@ -911,6 +924,7 @@ int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
{
int i, rc = 0;
enum cam_vote_level apply_level;
unsigned long applied_clk_rate;
if ((soc_info->num_clk == 0) ||
(soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
@@ -940,7 +954,8 @@ int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
rc = cam_soc_util_set_clk_rate(soc_info->clk[i],
soc_info->clk_name[i],
soc_info->clk_rate[apply_level][i]);
soc_info->clk_rate[apply_level][i],
&applied_clk_rate);
if (rc < 0) {
CAM_DBG(CAM_UTIL,
"dev name = %s clk_name = %s idx = %d\n"
@@ -951,6 +966,9 @@ int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0);
break;
}
if (i == soc_info->src_clk_idx)
soc_info->applied_src_clk_rate = applied_clk_rate;
}
return rc;

7
drivers/cam_utils/cam_soc_util.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_SOC_UTIL_H_
@@ -160,6 +160,7 @@ struct cam_soc_gpio_data {
* @clk_level_valid: Indicates whether corresponding level is valid
* @scl_clk_count: Number of scalable clocks present
* @scl_clk_idx: Index of scalable clocks
* @applied_src_clk_rate Current clock rate of the core source clk
* @gpio_data: Pointer to gpio info
* @pinctrl_info: Pointer to pinctrl info
* @dentry: Debugfs entry
@@ -206,6 +207,7 @@ struct cam_hw_soc_info {
int32_t clk_rate[CAM_MAX_VOTE][CAM_SOC_MAX_CLK];
int32_t prev_clk_level;
int32_t src_clk_idx;
unsigned long applied_src_clk_rate;
bool clk_level_valid[CAM_MAX_VOTE];
int32_t scl_clk_count;
int32_t scl_clk_idx[CAM_SOC_MAX_CLK];
@@ -455,11 +457,12 @@ int cam_soc_util_clk_put(struct clk **clk);
* @clk: Clock that needs to be turned ON
* @clk_name: Clocks name associated with clk
* @clk_rate: Clocks rate associated with clk
* @applied_clock_rate Final Clock rate applied to the clk
*
* @return: Success or failure
*/
int cam_soc_util_clk_enable(struct clk *clk, const char *clk_name,
int32_t clk_rate);
int32_t clk_rate, unsigned long *applied_clock_rate);
/**
* cam_soc_util_set_clk_rate_level()