msm: camera: common: Improve the CSID logging
Improve CSID irq logging for better debugging. Add support to dump the hw source clock. CRs-Fixed: 2808577 Change-Id: I06608588ef7a6e0ebc174a1ba138f6e16a9094f2 Signed-off-by: Jigar Agrawal <jigar@codeaurora.org>
This commit is contained in:
@@ -345,6 +345,41 @@ static int cam_ife_hw_mgr_is_rdi_res(uint32_t res_id)
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return rc;
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return rc;
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}
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}
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static int cam_ife_hw_mgr_dump_hw_src_clock(uint8_t hw_idx,
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enum cam_isp_hw_type hw_type)
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{
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struct cam_isp_hw_intf_data *hw_intf_data = NULL;
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struct cam_hw_intf *hw_intf = NULL;
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uint8_t dummy_args;
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switch (hw_type) {
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case CAM_ISP_HW_TYPE_VFE:
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if (!g_ife_hw_mgr.ife_devices[hw_idx]) {
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CAM_ERR(CAM_ISP, "No vfe device added yet");
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return -ENODEV;
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}
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hw_intf_data = g_ife_hw_mgr.ife_devices[hw_idx];
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if (!hw_intf_data->hw_intf) {
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CAM_ERR(CAM_ISP, "hw_intf is null");
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return -EINVAL;
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}
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hw_intf = hw_intf_data->hw_intf;
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if (hw_intf->hw_ops.process_cmd) {
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hw_intf->hw_ops.process_cmd(hw_intf->hw_priv,
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CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE,
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(void *)&dummy_args, sizeof(uint8_t));
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}
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break;
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default:
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CAM_ERR(CAM_ISP, "Unsupported HW Type: %u", hw_type);
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}
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return 0;
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}
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static enum cam_ife_pix_path_res_id
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static enum cam_ife_pix_path_res_id
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cam_ife_hw_mgr_get_csid_rdi_type_for_offline(
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cam_ife_hw_mgr_get_csid_rdi_type_for_offline(
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uint32_t rd_res_type)
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uint32_t rd_res_type)
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@@ -10116,20 +10151,26 @@ static int cam_ife_hw_mgr_handle_csid_error(
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struct cam_isp_hw_error_event_data error_event_data = {0};
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struct cam_isp_hw_error_event_data error_event_data = {0};
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struct cam_ife_hw_event_recovery_data recovery_data = {0};
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struct cam_ife_hw_event_recovery_data recovery_data = {0};
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switch (event_info->err_type) {
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if ((event_info->err_type & CAM_ISP_HW_ERROR_CSID_FATAL) &&
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g_ife_hw_mgr.debug_cfg.enable_csid_recovery) {
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case CAM_ISP_HW_ERROR_CSID_FATAL:
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if (!g_ife_hw_mgr.debug_cfg.enable_csid_recovery)
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break;
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error_event_data.error_type = event_info->err_type;
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error_event_data.error_type = event_info->err_type;
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cam_ife_hw_mgr_find_affected_ctx(&error_event_data,
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cam_ife_hw_mgr_find_affected_ctx(&error_event_data,
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event_info->hw_idx, &recovery_data);
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event_info->hw_idx, &recovery_data);
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break;
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}
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default:
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CAM_ERR(CAM_ISP, "Invalid event ID %d",
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if (event_info->err_type & CAM_ISP_HW_ERROR_CSID_OVERFLOW) {
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if (cam_ife_hw_mgr_dump_hw_src_clock(event_info->hw_idx,
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CAM_ISP_HW_TYPE_VFE))
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CAM_ERR_RATE_LIMIT(CAM_ISP,
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"VFE%d src_clk_rate dump failed");
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}
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if (event_info->err_type & ~(CAM_ISP_HW_ERROR_CSID_FATAL |
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CAM_ISP_HW_ERROR_CSID_OVERFLOW)) {
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CAM_ERR(CAM_ISP, "Invalid event ID 0x%x",
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event_info->err_type);
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event_info->err_type);
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rc = -EINVAL;
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rc = -EINVAL;
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break;
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}
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}
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return rc;
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return rc;
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@@ -10197,8 +10238,9 @@ static int cam_ife_hw_mgr_handle_csid_event(
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{
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{
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int rc = 0;
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int rc = 0;
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switch (evt_id) {
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CAM_DBG(CAM_ISP, "CSID event %u", evt_id);
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switch (evt_id) {
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case CAM_ISP_HW_EVENT_ERROR:
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case CAM_ISP_HW_EVENT_ERROR:
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rc = cam_ife_hw_mgr_handle_csid_error(event_info);
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rc = cam_ife_hw_mgr_handle_csid_error(event_info);
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break;
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break;
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@@ -10209,8 +10251,6 @@ static int cam_ife_hw_mgr_handle_csid_event(
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break;
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break;
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}
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}
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CAM_DBG(CAM_ISP, "CSID event %u", evt_id);
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return rc;
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return rc;
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}
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}
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@@ -10298,16 +10338,17 @@ static int cam_ife_hw_mgr_handle_hw_err(
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void *ctx,
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void *ctx,
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void *evt_info)
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void *evt_info)
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{
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{
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struct cam_ife_hw_mgr_ctx *ife_hw_mgr_ctx;
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struct cam_ife_hw_mgr_ctx *ife_hw_mgr_ctx;
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struct cam_isp_hw_event_info *event_info = evt_info;
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struct cam_isp_hw_event_info *event_info = evt_info;
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uint32_t core_idx;
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uint32_t core_idx;
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struct cam_isp_hw_error_event_data error_event_data = {0};
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struct cam_isp_hw_error_event_data error_event_data = {0};
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struct cam_ife_hw_event_recovery_data recovery_data = {0};
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struct cam_ife_hw_event_recovery_data recovery_data = {0};
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int rc = -EINVAL;
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int rc = -EINVAL;
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spin_lock(&g_ife_hw_mgr.ctx_lock);
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spin_lock(&g_ife_hw_mgr.ctx_lock);
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if (event_info->err_type == CAM_ISP_HW_ERROR_CSID_FATAL) {
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if (event_info->err_type & (CAM_ISP_HW_ERROR_CSID_FATAL |
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CAM_ISP_HW_ERROR_CSID_OVERFLOW)) {
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rc = cam_ife_hw_mgr_handle_csid_event(ctx, event_info,
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rc = cam_ife_hw_mgr_handle_csid_event(ctx, event_info,
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evt_id);
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evt_id);
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goto end;
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goto end;
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@@ -57,13 +57,13 @@ enum cam_isp_hw_event_type {
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* ISP hardware event CAM_ISP_HW_EVENT_ERROR
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* ISP hardware event CAM_ISP_HW_EVENT_ERROR
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*/
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*/
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enum cam_isp_hw_err_type {
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enum cam_isp_hw_err_type {
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CAM_ISP_HW_ERROR_NONE,
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CAM_ISP_HW_ERROR_NONE = 0x0001,
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CAM_ISP_HW_ERROR_OVERFLOW,
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CAM_ISP_HW_ERROR_OVERFLOW = 0x0002,
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CAM_ISP_HW_ERROR_P2I_ERROR,
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CAM_ISP_HW_ERROR_P2I_ERROR = 0x0004,
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CAM_ISP_HW_ERROR_VIOLATION,
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CAM_ISP_HW_ERROR_VIOLATION = 0x0008,
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CAM_ISP_HW_ERROR_BUSIF_OVERFLOW,
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CAM_ISP_HW_ERROR_BUSIF_OVERFLOW = 0x0010,
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CAM_ISP_HW_ERROR_CSID_FATAL,
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CAM_ISP_HW_ERROR_CSID_FATAL = 0x0020,
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CAM_ISP_HW_ERROR_MAX,
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CAM_ISP_HW_ERROR_CSID_OVERFLOW = 0x0040,
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};
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};
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/**
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/**
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@@ -412,8 +412,8 @@ static struct cam_ife_csid_csi2_rx_reg_info
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.lane_cfg_shift = 4,
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.lane_cfg_shift = 4,
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.phy_type_shift = 24,
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.phy_type_shift = 24,
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.phy_num_shift = 20,
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.phy_num_shift = 20,
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.fatal_err_mask = 0x78000,
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.fatal_err_mask = 0x4078000,
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.part_fatal_err_mask = 0x1801800,
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.part_fatal_err_mask = 0x1983800,
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.non_fatal_err_mask = 0x380000,
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.non_fatal_err_mask = 0x380000,
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};
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};
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@@ -31,7 +31,7 @@
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#define CAM_IFE_CSID_HW_IDX_1 0x2
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#define CAM_IFE_CSID_HW_IDX_1 0x2
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#define CAM_IFE_CSID_HW_IDX_2 0x4
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#define CAM_IFE_CSID_HW_IDX_2 0x4
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#define CAM_IFE_CSID_LOG_BUF_LEN 512
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#define CAM_IFE_CSID_LOG_BUF_LEN 512
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/*
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/*
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* Debug values enable the corresponding interrupts and debug logs provide
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* Debug values enable the corresponding interrupts and debug logs provide
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@@ -46,6 +46,7 @@
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#define CAM_IFE_CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE BIT(6)
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#define CAM_IFE_CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE BIT(6)
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#define CAM_IFE_CSID_DEBUG_ENABLE_HBI_VBI_INFO BIT(7)
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#define CAM_IFE_CSID_DEBUG_ENABLE_HBI_VBI_INFO BIT(7)
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#define CAM_IFE_CSID_DEBUG_DISABLE_EARLY_EOF BIT(8)
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#define CAM_IFE_CSID_DEBUG_DISABLE_EARLY_EOF BIT(8)
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#define CAM_IFE_DEBUG_ENABLE_UNMAPPED_VC_DT_IRQ BIT(9)
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/* Binning supported masks. Binning support changes for specific paths
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/* Binning supported masks. Binning support changes for specific paths
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* and also for targets. With the mask, we handle the supported features
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* and also for targets. With the mask, we handle the supported features
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@@ -257,15 +258,15 @@ struct cam_ife_csid_debug_info {
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/*
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/*
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* struct cam_ife_csid_hw_flags: place holder for flags
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* struct cam_ife_csid_hw_flags: place holder for flags
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*
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*
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* @device_enabled: flag to indicate if device enabled
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* @device_enabled: flag to indicate if device enabled
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* @binning_enabled: flag to indicate if binning enabled
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* @binning_enabled: flag to indicate if binning enabled
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* @sof_irq_triggered: flag to indicate if sof irq triggered
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* @sof_irq_triggered: flag to indicate if sof irq triggered
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* @fatal_err_detected: flag to indicate if fatal err detected
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* @fatal_err_detected: flag to indicate if fatal err detected
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* @rx_enabled: flag to indicate if rx is enabled
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* @rx_enabled: flag to indicate if rx is enabled
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* @tpg_configured: flag to indicate if internal_tpg is configured
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* @tpg_configured: flag to indicate if internal_tpg is configured
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* @sfe_inline_shdr: flag to indicate if sfe is inline shdr
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* @sfe_inline_shdr: flag to indicate if sfe is inline shdr
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* @reset_awaited: flag to indicate if reset is awaited
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* @reset_awaited: flag to indicate if reset is awaited
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* @offline_mode: flag to indicate if csid in offline mode
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* @offline_mode: flag to indicate if csid in offline mode
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*/
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*/
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struct cam_ife_csid_hw_flags {
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struct cam_ife_csid_hw_flags {
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bool device_enabled;
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bool device_enabled;
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@@ -48,28 +48,28 @@
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static const struct cam_ife_csid_irq_desc ver1_rx_irq_desc[] = {
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static const struct cam_ife_csid_irq_desc ver1_rx_irq_desc[] = {
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{
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{
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.desc = "DL0_EOT",
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.desc = "PHY_DL0_EOT_CAPTURED",
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},
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},
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{
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{
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.desc = "DL1_EOT",
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.desc = "PHY_DL1_EOT_CAPTURED",
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},
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},
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{
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{
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.desc = "DL2_EOT",
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.desc = "PHY_DL2_EOT_CAPTURED",
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},
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},
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{
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{
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.desc = "DL3_EOT",
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.desc = "PHY_DL3_EOT_CAPTURED",
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},
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},
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{
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{
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.desc = "DL0_SOT",
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.desc = "PHY_DL0_SOT_CAPTURED",
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},
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},
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{
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{
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.desc = "DL1_SOT",
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.desc = "PHY_DL1_SOT_CAPTURED",
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},
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},
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{
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{
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.desc = "DL2_SOT",
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.desc = "PHY_DL2_SOT_CAPTURED",
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},
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},
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{
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{
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.desc = "DL3_SOT",
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.desc = "PHY_DL3_SOT_CAPTURED",
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},
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},
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{
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{
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.desc = "LONG_PKT",
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.desc = "LONG_PKT",
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@@ -81,13 +81,13 @@ static const struct cam_ife_csid_irq_desc ver1_rx_irq_desc[] = {
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.desc = "CPHY_PKT_HDR",
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.desc = "CPHY_PKT_HDR",
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},
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},
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{
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{
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.desc = "ERROR_CPHY_EOT_RECEPTION",
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.desc = "CPHY_EOT_RECEPTION: No EOT on lane/s",
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},
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},
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{
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{
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.desc = "ERROR_CPHY_SOT_RECEPTION",
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.desc = "CPHY_SOT_RECEPTION: Less SOTs on lane/s",
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},
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},
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{
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{
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.desc = "ERROR_CPHY_PH_CRC",
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.desc = "CSID:%d CPHY_PH_CRC CPHY: Pkt Hdr CRC mismatch",
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},
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},
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{
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{
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.desc = "WARNING_ECC",
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.desc = "WARNING_ECC",
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@@ -135,7 +135,7 @@ static const struct cam_ife_csid_irq_desc ver1_path_irq_desc[] = {
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.desc = "Reset_Done",
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.desc = "Reset_Done",
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},
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},
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{
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{
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.desc = "ERROR_FIFO_OVERFLOW",
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.desc = "PATH_ERROR_O/P_FIFO_OVERFLOW: Slow IFE read",
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},
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},
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{
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{
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.desc = "SUBSAMPLED_EOF",
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.desc = "SUBSAMPLED_EOF",
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@@ -173,18 +173,19 @@ static const struct cam_ife_csid_irq_desc ver1_path_irq_desc[] = {
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{
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{
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.desc = "ERROR_LINE_COUNT",
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.desc = "ERROR_LINE_COUNT",
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},
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},
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{
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.desc = "PATH_ERROR_CCIF_VIOLATION: Bad frame timings",
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},
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{
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{
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.desc = "FRAME_DROP",
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.desc = "FRAME_DROP",
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},
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},
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{
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{
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.desc = "OVERFLOW_RECOVERY",
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.desc =
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"PATH_OVERFLOW_RECOVERY: Back pressure/output fifo ovrfl",
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},
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},
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{
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{
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.desc = "ERROR_REC_CCIF_VIOLATION",
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.desc = "ERROR_REC_CCIF_VIOLATION",
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},
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},
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{
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.desc = "CCIF_VIOLATION",
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},
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{
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{
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.desc = "VCDT_GRP0_SEL",
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.desc = "VCDT_GRP0_SEL",
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},
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},
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@@ -248,6 +249,10 @@ static int cam_ife_csid_ver1_set_debug(
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csid_hw->debug_info.rx_mask |=
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csid_hw->debug_info.rx_mask |=
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IFE_CSID_VER1_RX_CPHY_PKT_HDR_CAPTURED;
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IFE_CSID_VER1_RX_CPHY_PKT_HDR_CAPTURED;
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break;
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break;
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case CAM_IFE_DEBUG_ENABLE_UNMAPPED_VC_DT_IRQ:
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csid_hw->debug_info.rx_mask |=
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IFE_CSID_VER1_RX_UNMAPPED_VC_DT;
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break;
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default:
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default:
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break;
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break;
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}
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}
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@@ -3814,6 +3819,16 @@ static int cam_ife_csid_ver1_handle_rx_debug_event(
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val & csi2_reg->dt_mask,
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val & csi2_reg->dt_mask,
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val & csi2_reg->wc_mask);
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val & csi2_reg->wc_mask);
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break;
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break;
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case IFE_CSID_VER1_RX_UNMAPPED_VC_DT:
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val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
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csi2_reg->captured_long_pkt_0_addr);
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CAM_ERR_RATE_LIMIT(CAM_ISP,
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"CSID:%d UNMAPPED_VC_DT: VC:%d DT:%d WC:%d not mapped to any csid paths",
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csid_hw->hw_intf->hw_idx, (val >> 22),
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((val >> 16) & 0x3F), (val & 0xFFFF));
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csid_hw->counters.error_irq_count++;
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break;
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default:
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default:
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CAM_INFO_RATE_LIMIT(CAM_ISP,
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CAM_INFO_RATE_LIMIT(CAM_ISP,
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"CSID[%d] RX_IRQ: %s",
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"CSID[%d] RX_IRQ: %s",
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@@ -3828,27 +3843,20 @@ static int cam_ife_csid_ver1_handle_rx_debug_event(
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static int cam_ife_csid_ver1_handle_event_err(
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static int cam_ife_csid_ver1_handle_event_err(
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struct cam_ife_csid_ver1_hw *csid_hw,
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struct cam_ife_csid_ver1_hw *csid_hw,
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struct cam_ife_csid_ver1_evt_payload *evt_payload,
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struct cam_ife_csid_ver1_evt_payload *evt_payload,
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int err_type)
|
uint32_t err_type)
|
||||||
{
|
{
|
||||||
struct cam_isp_hw_event_info event_info;
|
struct cam_isp_hw_event_info event_info;
|
||||||
int rc = 0;
|
int rc = 0;
|
||||||
|
int dummy = 0;
|
||||||
|
|
||||||
event_info.err_type = err_type;
|
|
||||||
event_info.hw_idx = evt_payload->hw_idx;
|
event_info.hw_idx = evt_payload->hw_idx;
|
||||||
|
event_info.err_type = err_type;
|
||||||
|
|
||||||
switch (err_type) {
|
CAM_DBG(CAM_ISP, "CSID[%d] Error type %d",
|
||||||
|
csid_hw->hw_intf->hw_idx, err_type);
|
||||||
|
|
||||||
case CAM_ISP_HW_ERROR_CSID_FATAL:
|
rc = csid_hw->event_cb((void *)&dummy,
|
||||||
rc = csid_hw->event_cb(NULL,
|
CAM_ISP_HW_EVENT_ERROR, (void *)&event_info);
|
||||||
CAM_ISP_HW_EVENT_ERROR, (void *)&event_info);
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
CAM_DBG(CAM_ISP, "CSID[%d] invalid error type %d",
|
|
||||||
csid_hw->hw_intf->hw_idx,
|
|
||||||
err_type);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return rc;
|
return rc;
|
||||||
}
|
}
|
||||||
@@ -3906,7 +3914,10 @@ static int cam_ife_csid_ver1_rx_bottom_half_handler(
|
|||||||
struct cam_ife_csid_ver1_reg_info *csid_reg;
|
struct cam_ife_csid_ver1_reg_info *csid_reg;
|
||||||
uint8_t *log_buf = NULL;
|
uint8_t *log_buf = NULL;
|
||||||
uint32_t irq_status;
|
uint32_t irq_status;
|
||||||
|
uint32_t val;
|
||||||
|
uint32_t event_type = 0;
|
||||||
size_t len = 0;
|
size_t len = 0;
|
||||||
|
struct cam_hw_soc_info *soc_info;
|
||||||
|
|
||||||
if (!csid_hw || !evt_payload) {
|
if (!csid_hw || !evt_payload) {
|
||||||
CAM_ERR(CAM_ISP,
|
CAM_ERR(CAM_ISP,
|
||||||
@@ -3915,6 +3926,7 @@ static int cam_ife_csid_ver1_rx_bottom_half_handler(
|
|||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
soc_info = &csid_hw->hw_info->soc_info;
|
||||||
csid_reg = (struct cam_ife_csid_ver1_reg_info *)
|
csid_reg = (struct cam_ife_csid_ver1_reg_info *)
|
||||||
csid_hw->core_info->csid_reg;
|
csid_hw->core_info->csid_reg;
|
||||||
csi2_reg = csid_reg->csi2_reg;
|
csi2_reg = csid_reg->csi2_reg;
|
||||||
@@ -3925,26 +3937,40 @@ static int cam_ife_csid_ver1_rx_bottom_half_handler(
|
|||||||
memset(log_buf, 0, sizeof(csid_hw->log_buf));
|
memset(log_buf, 0, sizeof(csid_hw->log_buf));
|
||||||
|
|
||||||
if (irq_status) {
|
if (irq_status) {
|
||||||
|
|
||||||
cam_ife_csid_ver1_disable_csi2(csid_hw);
|
cam_ife_csid_ver1_disable_csi2(csid_hw);
|
||||||
len += scnprintf(log_buf, CAM_IFE_CSID_LOG_BUF_LEN - len,
|
len += scnprintf(log_buf, CAM_IFE_CSID_LOG_BUF_LEN - len,
|
||||||
"Overflow:\n ");
|
"Overflow:\n ");
|
||||||
|
|
||||||
if (irq_status & IFE_CSID_VER1_RX_LANE0_FIFO_OVERFLOW)
|
if (irq_status & IFE_CSID_VER1_RX_LANE0_FIFO_OVERFLOW)
|
||||||
len += scnprintf(log_buf + len,
|
len += scnprintf(log_buf + len,
|
||||||
CAM_IFE_CSID_LOG_BUF_LEN - len, "LANE_0\n");
|
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
||||||
|
"RX_ERROR_LANE0_FIFO_OVERFLOW: Skew/Less Data on lanes/ Slow csid clock:%luHz\n",
|
||||||
|
soc_info->applied_src_clk_rate);
|
||||||
|
|
||||||
if (irq_status & IFE_CSID_VER1_RX_LANE1_FIFO_OVERFLOW)
|
if (irq_status & IFE_CSID_VER1_RX_LANE1_FIFO_OVERFLOW)
|
||||||
len += scnprintf(log_buf + len,
|
len += scnprintf(log_buf + len,
|
||||||
CAM_IFE_CSID_LOG_BUF_LEN - len, "LANE_1\n");
|
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
||||||
|
"RX_ERROR_LANE1_FIFO_OVERFLOW: Skew/Less Data on lanes/ Slow csid clock:%luHz\n",
|
||||||
|
soc_info->applied_src_clk_rate);
|
||||||
|
|
||||||
if (irq_status & IFE_CSID_VER1_RX_LANE2_FIFO_OVERFLOW)
|
if (irq_status & IFE_CSID_VER1_RX_LANE2_FIFO_OVERFLOW)
|
||||||
len += scnprintf(log_buf + len,
|
len += scnprintf(log_buf + len,
|
||||||
CAM_IFE_CSID_LOG_BUF_LEN - len, "LANE_2\n");
|
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
||||||
|
"RX_ERROR_LANE2_FIFO_OVERFLOW: Skew/Less Data on lanes/ Slow csid clock:%luHz\n",
|
||||||
|
soc_info->applied_src_clk_rate);
|
||||||
|
|
||||||
if (irq_status & IFE_CSID_VER1_RX_LANE3_FIFO_OVERFLOW)
|
if (irq_status & IFE_CSID_VER1_RX_LANE3_FIFO_OVERFLOW)
|
||||||
len += scnprintf(log_buf + len,
|
len += scnprintf(log_buf + len,
|
||||||
CAM_IFE_CSID_LOG_BUF_LEN - len, "LANE_3\n");
|
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
||||||
|
"RX_ERROR_LANE3_FIFO_OVERFLOW: Skew/Less Data on lanes/ Slow csid clock:%luHz\n",
|
||||||
|
soc_info->applied_src_clk_rate);
|
||||||
|
|
||||||
|
if (irq_status & IFE_CSID_VER1_RX_TG_FIFO_OVERFLOW) {
|
||||||
|
event_type |= CAM_ISP_HW_ERROR_CSID_OVERFLOW;
|
||||||
|
len += scnprintf(log_buf + len,
|
||||||
|
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
||||||
|
"RX_ERROR_TPG_FIFO_OVERFLOW: Backpressure from IFE\n");
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
irq_status = evt_payload->irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
irq_status = evt_payload->irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
||||||
@@ -3955,25 +3981,56 @@ static int cam_ife_csid_ver1_rx_bottom_half_handler(
|
|||||||
len += scnprintf(log_buf, CAM_IFE_CSID_LOG_BUF_LEN - len,
|
len += scnprintf(log_buf, CAM_IFE_CSID_LOG_BUF_LEN - len,
|
||||||
"Part-fatal-errors:\n");
|
"Part-fatal-errors:\n");
|
||||||
|
|
||||||
if (irq_status & IFE_CSID_VER1_RX_CPHY_EOT_RECEPTION)
|
if ((irq_status & IFE_CSID_VER1_RX_CPHY_EOT_RECEPTION) &&
|
||||||
|
(!csid_hw->rx_cfg.epd_supported))
|
||||||
len += scnprintf(log_buf + len,
|
len += scnprintf(log_buf + len,
|
||||||
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
||||||
"CPHY_EOT_RECEPTION\n");
|
"CPHY_EOT_RECEPTION: No EOT on lane/s\n");
|
||||||
|
|
||||||
if (irq_status & IFE_CSID_VER1_RX_CPHY_SOT_RECEPTION)
|
if (irq_status & IFE_CSID_VER1_RX_CPHY_SOT_RECEPTION)
|
||||||
len += scnprintf(log_buf + len,
|
len += scnprintf(log_buf + len,
|
||||||
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
||||||
"CPHY_SOT_RECEPTION\n");
|
"CPHY_SOT_RECEPTION: Less SOTs on lane/s\n");
|
||||||
|
|
||||||
if (irq_status & IFE_CSID_VER1_RX_STREAM_UNDERFLOW)
|
if (irq_status & IFE_CSID_VER1_RX_CPHY_PH_CRC)
|
||||||
len += scnprintf(log_buf + len,
|
len += scnprintf(log_buf + len,
|
||||||
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
||||||
"STREAM_UNDERFLOW\n");
|
"CPHY_PH_CRC CPHY: Pkt Hdr CRC mismatch\n");
|
||||||
|
|
||||||
|
if (irq_status & IFE_CSID_VER1_RX_ERROR_CRC)
|
||||||
|
len += scnprintf(log_buf + len,
|
||||||
|
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
||||||
|
"ERROR_CRC CPHY: Long pkt payload CRC mismatch\n");
|
||||||
|
|
||||||
|
if (irq_status & IFE_CSID_VER1_RX_ERROR_ECC)
|
||||||
|
len += scnprintf(log_buf + len,
|
||||||
|
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
||||||
|
"ERROR_ECC: Dphy pkt hdr errors unrecoverable\n");
|
||||||
|
|
||||||
|
if (irq_status & IFE_CSID_VER1_RX_MMAPPED_VC_DT) {
|
||||||
|
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
||||||
|
csi2_reg->captured_long_pkt_0_addr);
|
||||||
|
|
||||||
|
len += scnprintf(log_buf + len,
|
||||||
|
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
||||||
|
"MMAPPED_VC_DT: VC:%d DT:%d mapped to more than 1 csid paths\n",
|
||||||
|
(val >> 22), ((val >> 16) & 0x3F));
|
||||||
|
}
|
||||||
|
|
||||||
|
if (irq_status & IFE_CSID_VER1_RX_STREAM_UNDERFLOW) {
|
||||||
|
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
||||||
|
csi2_reg->captured_long_pkt_0_addr);
|
||||||
|
|
||||||
|
len += scnprintf(log_buf + len,
|
||||||
|
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
||||||
|
"ERROR_STREAM_UNDERFLOW: Fewer bytes rcvd than WC:%d in pkt hdr\n",
|
||||||
|
val & 0xFFFF);
|
||||||
|
}
|
||||||
|
|
||||||
if (irq_status & IFE_CSID_VER1_RX_UNBOUNDED_FRAME)
|
if (irq_status & IFE_CSID_VER1_RX_UNBOUNDED_FRAME)
|
||||||
len += scnprintf(log_buf + len,
|
len += scnprintf(log_buf + len,
|
||||||
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
CAM_IFE_CSID_LOG_BUF_LEN - len,
|
||||||
"UNBOUNDED_FRAME\n");
|
"UNBOUNDED_FRAME: Frame started with EOF or No EOF\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
if (len)
|
if (len)
|
||||||
@@ -3981,8 +4038,11 @@ static int cam_ife_csid_ver1_rx_bottom_half_handler(
|
|||||||
csid_hw->hw_intf->hw_idx, log_buf);
|
csid_hw->hw_intf->hw_idx, log_buf);
|
||||||
|
|
||||||
if (csid_hw->flags.fatal_err_detected)
|
if (csid_hw->flags.fatal_err_detected)
|
||||||
|
event_type |= CAM_ISP_HW_ERROR_CSID_FATAL;
|
||||||
|
|
||||||
|
if (event_type)
|
||||||
cam_ife_csid_ver1_handle_event_err(csid_hw,
|
cam_ife_csid_ver1_handle_event_err(csid_hw,
|
||||||
evt_payload, CAM_ISP_HW_ERROR_CSID_FATAL);
|
evt_payload, event_type);
|
||||||
|
|
||||||
return IRQ_HANDLED;
|
return IRQ_HANDLED;
|
||||||
}
|
}
|
||||||
@@ -4028,6 +4088,11 @@ static int cam_ife_csid_ver1_path_bottom_half_handler(
|
|||||||
irq_reg_tag[index],
|
irq_reg_tag[index],
|
||||||
log_buf);
|
log_buf);
|
||||||
|
|
||||||
|
if (evt_payload->irq_status[index] &
|
||||||
|
IFE_CSID_VER1_PATH_ERROR_FIFO_OVERFLOW)
|
||||||
|
cam_ife_csid_ver1_handle_event_err(csid_hw,
|
||||||
|
evt_payload, CAM_ISP_HW_ERROR_CSID_OVERFLOW);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -4156,12 +4221,22 @@ static int cam_ife_csid_ver1_rx_top_half(
|
|||||||
|
|
||||||
if (status & csi2_reg->part_fatal_err_mask) {
|
if (status & csi2_reg->part_fatal_err_mask) {
|
||||||
|
|
||||||
if (status & IFE_CSID_VER1_RX_CPHY_EOT_RECEPTION)
|
if ((status & IFE_CSID_VER1_RX_CPHY_EOT_RECEPTION) &&
|
||||||
|
(!csid_hw->rx_cfg.epd_supported))
|
||||||
csid_hw->counters.error_irq_count++;
|
csid_hw->counters.error_irq_count++;
|
||||||
|
|
||||||
if (status & IFE_CSID_VER1_RX_CPHY_SOT_RECEPTION)
|
if (status & IFE_CSID_VER1_RX_CPHY_SOT_RECEPTION)
|
||||||
csid_hw->counters.error_irq_count++;
|
csid_hw->counters.error_irq_count++;
|
||||||
|
|
||||||
|
if (status & IFE_CSID_VER1_RX_CPHY_PH_CRC)
|
||||||
|
csid_hw->counters.error_irq_count++;
|
||||||
|
|
||||||
|
if (status & IFE_CSID_VER1_RX_ERROR_CRC)
|
||||||
|
csid_hw->counters.error_irq_count++;
|
||||||
|
|
||||||
|
if (status & IFE_CSID_VER1_RX_ERROR_ECC)
|
||||||
|
csid_hw->counters.error_irq_count++;
|
||||||
|
|
||||||
if (status & IFE_CSID_VER1_RX_STREAM_UNDERFLOW)
|
if (status & IFE_CSID_VER1_RX_STREAM_UNDERFLOW)
|
||||||
csid_hw->counters.error_irq_count++;
|
csid_hw->counters.error_irq_count++;
|
||||||
|
|
||||||
@@ -4349,7 +4424,7 @@ static irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|||||||
|
|
||||||
switch (i) {
|
switch (i) {
|
||||||
case CAM_IFE_CSID_IRQ_REG_RX:
|
case CAM_IFE_CSID_IRQ_REG_RX:
|
||||||
cam_ife_csid_ver1_rx_top_half(
|
cam_ife_csid_ver1_rx_top_half(
|
||||||
status, csid_hw, &need_rx_bh);
|
status, csid_hw, &need_rx_bh);
|
||||||
break;
|
break;
|
||||||
case CAM_IFE_CSID_IRQ_REG_IPP:
|
case CAM_IFE_CSID_IRQ_REG_IPP:
|
||||||
|
@@ -25,7 +25,7 @@
|
|||||||
#define IFE_CSID_VER1_RX_LANE1_FIFO_OVERFLOW BIT(16)
|
#define IFE_CSID_VER1_RX_LANE1_FIFO_OVERFLOW BIT(16)
|
||||||
#define IFE_CSID_VER1_RX_LANE2_FIFO_OVERFLOW BIT(17)
|
#define IFE_CSID_VER1_RX_LANE2_FIFO_OVERFLOW BIT(17)
|
||||||
#define IFE_CSID_VER1_RX_LANE3_FIFO_OVERFLOW BIT(18)
|
#define IFE_CSID_VER1_RX_LANE3_FIFO_OVERFLOW BIT(18)
|
||||||
#define IFE_CSID_VER1_RX_CRC BIT(19)
|
#define IFE_CSID_VER1_RX_ERROR_CRC BIT(19)
|
||||||
#define IFE_CSID_VER1_RX_ERROR_ECC BIT(20)
|
#define IFE_CSID_VER1_RX_ERROR_ECC BIT(20)
|
||||||
#define IFE_CSID_VER1_RX_MMAPPED_VC_DT BIT(21)
|
#define IFE_CSID_VER1_RX_MMAPPED_VC_DT BIT(21)
|
||||||
#define IFE_CSID_VER1_RX_UNMAPPED_VC_DT BIT(22)
|
#define IFE_CSID_VER1_RX_UNMAPPED_VC_DT BIT(22)
|
||||||
|
@@ -147,6 +147,7 @@ enum cam_isp_hw_cmd_type {
|
|||||||
CAM_ISP_HW_CMD_CSID_MUP_UPDATE,
|
CAM_ISP_HW_CMD_CSID_MUP_UPDATE,
|
||||||
CAM_ISP_HW_CMD_BUF_UPDATE,
|
CAM_ISP_HW_CMD_BUF_UPDATE,
|
||||||
CAM_ISP_HW_CMD_BUF_UPDATE_RM,
|
CAM_ISP_HW_CMD_BUF_UPDATE_RM,
|
||||||
|
CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE,
|
||||||
CAM_ISP_HW_CMD_MAX,
|
CAM_ISP_HW_CMD_MAX,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0-only
|
// SPDX-License-Identifier: GPL-2.0-only
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <linux/iopoll.h>
|
#include <linux/iopoll.h>
|
||||||
@@ -75,7 +75,7 @@ static int cam_csid_ppi_enable_hw(struct cam_csid_ppi_hw *ppi_hw)
|
|||||||
|
|
||||||
for (i = 0; i < soc_info->num_clk; i++) {
|
for (i = 0; i < soc_info->num_clk; i++) {
|
||||||
rc = cam_soc_util_clk_enable(soc_info->clk[i],
|
rc = cam_soc_util_clk_enable(soc_info->clk[i],
|
||||||
soc_info->clk_name[i], 0);
|
soc_info->clk_name[i], 0, NULL);
|
||||||
if (rc)
|
if (rc)
|
||||||
goto clk_disable;
|
goto clk_disable;
|
||||||
}
|
}
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0-only
|
// SPDX-License-Identifier: GPL-2.0-only
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
|
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
@@ -199,7 +199,7 @@ int cam_tfe_soc_enable_clk(struct cam_hw_soc_info *soc_info,
|
|||||||
|
|
||||||
if (strcmp(clk_name, CAM_TFE_DSP_CLK_NAME) == 0) {
|
if (strcmp(clk_name, CAM_TFE_DSP_CLK_NAME) == 0) {
|
||||||
rc = cam_soc_util_clk_enable(soc_private->dsp_clk,
|
rc = cam_soc_util_clk_enable(soc_private->dsp_clk,
|
||||||
CAM_TFE_DSP_CLK_NAME, soc_private->dsp_clk_rate);
|
CAM_TFE_DSP_CLK_NAME, soc_private->dsp_clk_rate, NULL);
|
||||||
if (rc)
|
if (rc)
|
||||||
CAM_ERR(CAM_ISP,
|
CAM_ERR(CAM_ISP,
|
||||||
"Error enable dsp clk failed rc=%d", rc);
|
"Error enable dsp clk failed rc=%d", rc);
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0-only
|
// SPDX-License-Identifier: GPL-2.0-only
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
|
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <linux/delay.h>
|
#include <linux/delay.h>
|
||||||
@@ -509,6 +509,7 @@ int cam_vfe_process_cmd(void *hw_priv, uint32_t cmd_type,
|
|||||||
case CAM_ISP_HW_CMD_ADD_WAIT:
|
case CAM_ISP_HW_CMD_ADD_WAIT:
|
||||||
case CAM_ISP_HW_CMD_ADD_WAIT_TRIGGER:
|
case CAM_ISP_HW_CMD_ADD_WAIT_TRIGGER:
|
||||||
case CAM_ISP_HW_CMD_CAMIF_DATA:
|
case CAM_ISP_HW_CMD_CAMIF_DATA:
|
||||||
|
case CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE:
|
||||||
case CAM_ISP_HW_CMD_BLANKING_UPDATE:
|
case CAM_ISP_HW_CMD_BLANKING_UPDATE:
|
||||||
rc = core_info->vfe_top->hw_ops.process_cmd(
|
rc = core_info->vfe_top->hw_ops.process_cmd(
|
||||||
core_info->vfe_top->top_priv, cmd_type, cmd_args,
|
core_info->vfe_top->top_priv, cmd_type, cmd_args,
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0-only
|
// SPDX-License-Identifier: GPL-2.0-only
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
|
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
@@ -307,7 +307,7 @@ int cam_vfe_soc_enable_clk(struct cam_hw_soc_info *soc_info,
|
|||||||
}
|
}
|
||||||
|
|
||||||
rc = cam_soc_util_clk_enable(soc_private->dsp_clk,
|
rc = cam_soc_util_clk_enable(soc_private->dsp_clk,
|
||||||
CAM_VFE_DSP_CLK_NAME, soc_private->dsp_clk_rate);
|
CAM_VFE_DSP_CLK_NAME, soc_private->dsp_clk_rate, NULL);
|
||||||
if (rc)
|
if (rc)
|
||||||
CAM_ERR(CAM_ISP,
|
CAM_ERR(CAM_ISP,
|
||||||
"Error enable dsp clk failed rc=%d", rc);
|
"Error enable dsp clk failed rc=%d", rc);
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0-only
|
// SPDX-License-Identifier: GPL-2.0-only
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
|
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
@@ -169,6 +169,29 @@ static int cam_vfe_top_clock_update(
|
|||||||
return rc;
|
return rc;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int cam_vfe_top_dump_info(
|
||||||
|
struct cam_vfe_top_ver2_priv *top_priv, uint32_t cmd_type)
|
||||||
|
{
|
||||||
|
struct cam_hw_soc_info *soc_info = top_priv->common_data.soc_info;
|
||||||
|
|
||||||
|
if (!soc_info) {
|
||||||
|
CAM_ERR(CAM_ISP, "Null soc_info");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (cmd_type) {
|
||||||
|
case CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE:
|
||||||
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "VFE%d src_clk_rate:%luHz",
|
||||||
|
soc_info->index, soc_info->applied_src_clk_rate);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
CAM_ERR(CAM_ISP, "cmd_type: %u not supported", cmd_type);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
static int cam_vfe_top_blanking_update(uint32_t cmd_type,
|
static int cam_vfe_top_blanking_update(uint32_t cmd_type,
|
||||||
void *cmd_args, uint32_t arg_size)
|
void *cmd_args, uint32_t arg_size)
|
||||||
{
|
{
|
||||||
@@ -794,6 +817,9 @@ int cam_vfe_top_process_cmd(void *device_priv, uint32_t cmd_type,
|
|||||||
rc = cam_vfe_top_clock_update(top_priv, cmd_args,
|
rc = cam_vfe_top_clock_update(top_priv, cmd_args,
|
||||||
arg_size);
|
arg_size);
|
||||||
break;
|
break;
|
||||||
|
case CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE:
|
||||||
|
rc = cam_vfe_top_dump_info(top_priv, cmd_type);
|
||||||
|
break;
|
||||||
case CAM_ISP_HW_CMD_FE_UPDATE_IN_RD:
|
case CAM_ISP_HW_CMD_FE_UPDATE_IN_RD:
|
||||||
rc = cam_vfe_top_fs_update(top_priv, cmd_args,
|
rc = cam_vfe_top_fs_update(top_priv, cmd_args,
|
||||||
arg_size);
|
arg_size);
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0-only
|
// SPDX-License-Identifier: GPL-2.0-only
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
|
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
@@ -190,6 +190,30 @@ static int cam_vfe_top_ver3_clock_update(
|
|||||||
return rc;
|
return rc;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int cam_vfe_top_ver3_dump_info(
|
||||||
|
struct cam_vfe_top_ver3_priv *top_priv, uint32_t cmd_type)
|
||||||
|
{
|
||||||
|
struct cam_hw_soc_info *soc_info = top_priv->common_data.soc_info;
|
||||||
|
|
||||||
|
if (!soc_info) {
|
||||||
|
CAM_ERR(CAM_ISP, "Null soc_info");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (cmd_type) {
|
||||||
|
case CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE:
|
||||||
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "VFE%d src_clk_rate:%luHz",
|
||||||
|
soc_info->index, soc_info->applied_src_clk_rate);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
CAM_ERR(CAM_ISP, "cmd_type: %u not supported", cmd_type);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
static int cam_vfe_top_ver3_blanking_update(uint32_t cmd_type,
|
static int cam_vfe_top_ver3_blanking_update(uint32_t cmd_type,
|
||||||
void *cmd_args, uint32_t arg_size)
|
void *cmd_args, uint32_t arg_size)
|
||||||
{
|
{
|
||||||
@@ -731,6 +755,9 @@ int cam_vfe_top_ver3_process_cmd(void *device_priv, uint32_t cmd_type,
|
|||||||
rc = cam_vfe_top_ver3_clock_update(top_priv, cmd_args,
|
rc = cam_vfe_top_ver3_clock_update(top_priv, cmd_args,
|
||||||
arg_size);
|
arg_size);
|
||||||
break;
|
break;
|
||||||
|
case CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE:
|
||||||
|
rc = cam_vfe_top_ver3_dump_info(top_priv, cmd_type);
|
||||||
|
break;
|
||||||
case CAM_ISP_HW_CMD_FE_UPDATE_IN_RD:
|
case CAM_ISP_HW_CMD_FE_UPDATE_IN_RD:
|
||||||
rc = cam_vfe_top_fs_update(top_priv, cmd_args,
|
rc = cam_vfe_top_fs_update(top_priv, cmd_args,
|
||||||
arg_size);
|
arg_size);
|
||||||
|
@@ -246,6 +246,29 @@ static int cam_vfe_top_ver4_clock_update(
|
|||||||
return rc;
|
return rc;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int cam_vfe_top_ver4_dump_info(
|
||||||
|
struct cam_vfe_top_ver4_priv *top_priv, uint32_t cmd_type)
|
||||||
|
{
|
||||||
|
struct cam_hw_soc_info *soc_info = top_priv->common_data.soc_info;
|
||||||
|
|
||||||
|
if (!soc_info) {
|
||||||
|
CAM_ERR(CAM_ISP, "Null soc_info");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (cmd_type) {
|
||||||
|
case CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE:
|
||||||
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "VFE%d src_clk_rate:%luHz",
|
||||||
|
soc_info->index, soc_info->applied_src_clk_rate);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
CAM_ERR(CAM_ISP, "cmd_type: %u not supported", cmd_type);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
static int cam_vfe_core_config_control(
|
static int cam_vfe_core_config_control(
|
||||||
struct cam_vfe_top_ver4_priv *top_priv,
|
struct cam_vfe_top_ver4_priv *top_priv,
|
||||||
void *cmd_args, uint32_t arg_size)
|
void *cmd_args, uint32_t arg_size)
|
||||||
@@ -633,6 +656,9 @@ int cam_vfe_top_ver4_process_cmd(void *device_priv, uint32_t cmd_type,
|
|||||||
rc = cam_vfe_top_ver4_clock_update(top_priv, cmd_args,
|
rc = cam_vfe_top_ver4_clock_update(top_priv, cmd_args,
|
||||||
arg_size);
|
arg_size);
|
||||||
break;
|
break;
|
||||||
|
case CAM_ISP_HW_DUMP_HW_SRC_CLK_RATE:
|
||||||
|
rc = cam_vfe_top_ver4_dump_info(top_priv, cmd_type);
|
||||||
|
break;
|
||||||
case CAM_ISP_HW_CMD_FE_UPDATE_IN_RD:
|
case CAM_ISP_HW_CMD_FE_UPDATE_IN_RD:
|
||||||
rc = cam_vfe_top_fs_update(top_priv, cmd_args,
|
rc = cam_vfe_top_fs_update(top_priv, cmd_args,
|
||||||
arg_size);
|
arg_size);
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0-only
|
// SPDX-License-Identifier: GPL-2.0-only
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
|
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "cam_csiphy_soc.h"
|
#include "cam_csiphy_soc.h"
|
||||||
@@ -130,8 +130,6 @@ int32_t cam_csiphy_status_dmp(struct csiphy_device *csiphy_dev)
|
|||||||
return rc;
|
return rc;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
enum cam_vote_level get_clk_vote_default(struct csiphy_device *csiphy_dev,
|
enum cam_vote_level get_clk_vote_default(struct csiphy_device *csiphy_dev,
|
||||||
int32_t index)
|
int32_t index)
|
||||||
{
|
{
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0-only
|
// SPDX-License-Identifier: GPL-2.0-only
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
|
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <linux/kernel.h>
|
#include <linux/kernel.h>
|
||||||
@@ -2098,7 +2098,8 @@ int cam_sensor_core_power_up(struct cam_sensor_power_ctrl_t *ctrl,
|
|||||||
for (j = 0; j < soc_info->num_clk; j++) {
|
for (j = 0; j < soc_info->num_clk; j++) {
|
||||||
rc = cam_soc_util_clk_enable(soc_info->clk[j],
|
rc = cam_soc_util_clk_enable(soc_info->clk[j],
|
||||||
soc_info->clk_name[j],
|
soc_info->clk_name[j],
|
||||||
soc_info->clk_rate[0][j]);
|
soc_info->clk_rate[0][j],
|
||||||
|
NULL);
|
||||||
if (rc)
|
if (rc)
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0-only
|
// SPDX-License-Identifier: GPL-2.0-only
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
|
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <linux/of.h>
|
#include <linux/of.h>
|
||||||
@@ -361,19 +361,20 @@ long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info,
|
|||||||
/**
|
/**
|
||||||
* cam_soc_util_set_clk_rate()
|
* cam_soc_util_set_clk_rate()
|
||||||
*
|
*
|
||||||
* @brief: Sets the given rate for the clk requested for
|
* @brief: Sets the given rate for the clk requested for
|
||||||
*
|
*
|
||||||
* @clk: Clock structure information for which rate is to be set
|
* @clk: Clock structure information for which rate is to be set
|
||||||
* @clk_name: Name of the clock for which rate is being set
|
* @clk_name: Name of the clock for which rate is being set
|
||||||
* @clk_rate Clock rate to be set
|
* @clk_rate: Clock rate to be set
|
||||||
|
* @applied_clk_rate: Final clock rate set to the clk
|
||||||
*
|
*
|
||||||
* @return: Success or failure
|
* @return: Success or failure
|
||||||
*/
|
*/
|
||||||
static int cam_soc_util_set_clk_rate(struct clk *clk, const char *clk_name,
|
static int cam_soc_util_set_clk_rate(struct clk *clk, const char *clk_name,
|
||||||
int64_t clk_rate)
|
int64_t clk_rate, unsigned long *applied_clk_rate)
|
||||||
{
|
{
|
||||||
int rc = 0;
|
int rc = 0;
|
||||||
long clk_rate_round;
|
long clk_rate_round = -1;
|
||||||
|
|
||||||
if (!clk || !clk_name)
|
if (!clk || !clk_name)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
@@ -410,6 +411,9 @@ static int cam_soc_util_set_clk_rate(struct clk *clk, const char *clk_name,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (applied_clk_rate)
|
||||||
|
*applied_clk_rate = clk_rate_round;
|
||||||
|
|
||||||
return rc;
|
return rc;
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -458,7 +462,8 @@ int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info,
|
|||||||
}
|
}
|
||||||
|
|
||||||
rc = cam_soc_util_set_clk_rate(clk,
|
rc = cam_soc_util_set_clk_rate(clk,
|
||||||
soc_info->clk_name[src_clk_idx], clk_rate);
|
soc_info->clk_name[src_clk_idx], clk_rate,
|
||||||
|
&soc_info->applied_src_clk_rate);
|
||||||
if (rc) {
|
if (rc) {
|
||||||
CAM_ERR(CAM_UTIL,
|
CAM_ERR(CAM_UTIL,
|
||||||
"SET_RATE Failed: src clk: %s, rate %lld, dev_name = %s rc: %d",
|
"SET_RATE Failed: src clk: %s, rate %lld, dev_name = %s rc: %d",
|
||||||
@@ -478,7 +483,8 @@ int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info,
|
|||||||
clk = soc_info->clk[scl_clk_idx];
|
clk = soc_info->clk[scl_clk_idx];
|
||||||
rc = cam_soc_util_set_clk_rate(clk,
|
rc = cam_soc_util_set_clk_rate(clk,
|
||||||
soc_info->clk_name[scl_clk_idx],
|
soc_info->clk_name[scl_clk_idx],
|
||||||
soc_info->clk_rate[apply_level][scl_clk_idx]);
|
soc_info->clk_rate[apply_level][scl_clk_idx],
|
||||||
|
NULL);
|
||||||
if (rc) {
|
if (rc) {
|
||||||
CAM_WARN(CAM_UTIL,
|
CAM_WARN(CAM_UTIL,
|
||||||
"SET_RATE Failed: scl clk: %s, rate %d dev_name = %s, rc: %d",
|
"SET_RATE Failed: scl clk: %s, rate %d dev_name = %s, rc: %d",
|
||||||
@@ -585,14 +591,15 @@ int cam_soc_util_get_option_clk_by_name(struct cam_hw_soc_info *soc_info,
|
|||||||
}
|
}
|
||||||
|
|
||||||
int cam_soc_util_clk_enable(struct clk *clk, const char *clk_name,
|
int cam_soc_util_clk_enable(struct clk *clk, const char *clk_name,
|
||||||
int32_t clk_rate)
|
int32_t clk_rate, unsigned long *applied_clock_rate)
|
||||||
{
|
{
|
||||||
int rc = 0;
|
int rc = 0;
|
||||||
|
|
||||||
if (!clk || !clk_name)
|
if (!clk || !clk_name)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
rc = cam_soc_util_set_clk_rate(clk, clk_name, clk_rate);
|
rc = cam_soc_util_set_clk_rate(clk, clk_name, clk_rate,
|
||||||
|
applied_clock_rate);
|
||||||
if (rc)
|
if (rc)
|
||||||
return rc;
|
return rc;
|
||||||
|
|
||||||
@@ -630,8 +637,9 @@ int cam_soc_util_clk_disable(struct clk *clk, const char *clk_name)
|
|||||||
int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
|
int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
|
||||||
enum cam_vote_level clk_level)
|
enum cam_vote_level clk_level)
|
||||||
{
|
{
|
||||||
int i, rc = 0;
|
int i, rc = 0;
|
||||||
enum cam_vote_level apply_level;
|
enum cam_vote_level apply_level;
|
||||||
|
unsigned long applied_clk_rate;
|
||||||
|
|
||||||
if ((soc_info->num_clk == 0) ||
|
if ((soc_info->num_clk == 0) ||
|
||||||
(soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
|
(soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
|
||||||
@@ -651,9 +659,14 @@ int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
|
|||||||
for (i = 0; i < soc_info->num_clk; i++) {
|
for (i = 0; i < soc_info->num_clk; i++) {
|
||||||
rc = cam_soc_util_clk_enable(soc_info->clk[i],
|
rc = cam_soc_util_clk_enable(soc_info->clk[i],
|
||||||
soc_info->clk_name[i],
|
soc_info->clk_name[i],
|
||||||
soc_info->clk_rate[apply_level][i]);
|
soc_info->clk_rate[apply_level][i],
|
||||||
|
&applied_clk_rate);
|
||||||
if (rc)
|
if (rc)
|
||||||
goto clk_disable;
|
goto clk_disable;
|
||||||
|
|
||||||
|
if (i == soc_info->src_clk_idx)
|
||||||
|
soc_info->applied_src_clk_rate = applied_clk_rate;
|
||||||
|
|
||||||
if (soc_info->cam_cx_ipeak_enable) {
|
if (soc_info->cam_cx_ipeak_enable) {
|
||||||
CAM_DBG(CAM_UTIL,
|
CAM_DBG(CAM_UTIL,
|
||||||
"dev name = %s clk name = %s idx = %d\n"
|
"dev name = %s clk name = %s idx = %d\n"
|
||||||
@@ -911,6 +924,7 @@ int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
|
|||||||
{
|
{
|
||||||
int i, rc = 0;
|
int i, rc = 0;
|
||||||
enum cam_vote_level apply_level;
|
enum cam_vote_level apply_level;
|
||||||
|
unsigned long applied_clk_rate;
|
||||||
|
|
||||||
if ((soc_info->num_clk == 0) ||
|
if ((soc_info->num_clk == 0) ||
|
||||||
(soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
|
(soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
|
||||||
@@ -940,7 +954,8 @@ int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
|
|||||||
|
|
||||||
rc = cam_soc_util_set_clk_rate(soc_info->clk[i],
|
rc = cam_soc_util_set_clk_rate(soc_info->clk[i],
|
||||||
soc_info->clk_name[i],
|
soc_info->clk_name[i],
|
||||||
soc_info->clk_rate[apply_level][i]);
|
soc_info->clk_rate[apply_level][i],
|
||||||
|
&applied_clk_rate);
|
||||||
if (rc < 0) {
|
if (rc < 0) {
|
||||||
CAM_DBG(CAM_UTIL,
|
CAM_DBG(CAM_UTIL,
|
||||||
"dev name = %s clk_name = %s idx = %d\n"
|
"dev name = %s clk_name = %s idx = %d\n"
|
||||||
@@ -951,6 +966,9 @@ int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
|
|||||||
cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0);
|
cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (i == soc_info->src_clk_idx)
|
||||||
|
soc_info->applied_src_clk_rate = applied_clk_rate;
|
||||||
}
|
}
|
||||||
|
|
||||||
return rc;
|
return rc;
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
|
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef _CAM_SOC_UTIL_H_
|
#ifndef _CAM_SOC_UTIL_H_
|
||||||
@@ -160,6 +160,7 @@ struct cam_soc_gpio_data {
|
|||||||
* @clk_level_valid: Indicates whether corresponding level is valid
|
* @clk_level_valid: Indicates whether corresponding level is valid
|
||||||
* @scl_clk_count: Number of scalable clocks present
|
* @scl_clk_count: Number of scalable clocks present
|
||||||
* @scl_clk_idx: Index of scalable clocks
|
* @scl_clk_idx: Index of scalable clocks
|
||||||
|
* @applied_src_clk_rate Current clock rate of the core source clk
|
||||||
* @gpio_data: Pointer to gpio info
|
* @gpio_data: Pointer to gpio info
|
||||||
* @pinctrl_info: Pointer to pinctrl info
|
* @pinctrl_info: Pointer to pinctrl info
|
||||||
* @dentry: Debugfs entry
|
* @dentry: Debugfs entry
|
||||||
@@ -206,6 +207,7 @@ struct cam_hw_soc_info {
|
|||||||
int32_t clk_rate[CAM_MAX_VOTE][CAM_SOC_MAX_CLK];
|
int32_t clk_rate[CAM_MAX_VOTE][CAM_SOC_MAX_CLK];
|
||||||
int32_t prev_clk_level;
|
int32_t prev_clk_level;
|
||||||
int32_t src_clk_idx;
|
int32_t src_clk_idx;
|
||||||
|
unsigned long applied_src_clk_rate;
|
||||||
bool clk_level_valid[CAM_MAX_VOTE];
|
bool clk_level_valid[CAM_MAX_VOTE];
|
||||||
int32_t scl_clk_count;
|
int32_t scl_clk_count;
|
||||||
int32_t scl_clk_idx[CAM_SOC_MAX_CLK];
|
int32_t scl_clk_idx[CAM_SOC_MAX_CLK];
|
||||||
@@ -455,11 +457,12 @@ int cam_soc_util_clk_put(struct clk **clk);
|
|||||||
* @clk: Clock that needs to be turned ON
|
* @clk: Clock that needs to be turned ON
|
||||||
* @clk_name: Clocks name associated with clk
|
* @clk_name: Clocks name associated with clk
|
||||||
* @clk_rate: Clocks rate associated with clk
|
* @clk_rate: Clocks rate associated with clk
|
||||||
|
* @applied_clock_rate Final Clock rate applied to the clk
|
||||||
*
|
*
|
||||||
* @return: Success or failure
|
* @return: Success or failure
|
||||||
*/
|
*/
|
||||||
int cam_soc_util_clk_enable(struct clk *clk, const char *clk_name,
|
int cam_soc_util_clk_enable(struct clk *clk, const char *clk_name,
|
||||||
int32_t clk_rate);
|
int32_t clk_rate, unsigned long *applied_clock_rate);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* cam_soc_util_set_clk_rate_level()
|
* cam_soc_util_set_clk_rate_level()
|
||||||
|
Reference in New Issue
Block a user