samsung-sm8650/android_kernel_samsung_sm8650-modules
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

msm: camera: common: Improve the CSID logging

Browse Source 
Improve CSID irq logging for better debugging.
Add support to dump the hw source clock.

CRs-Fixed: 2808577
Change-Id: I06608588ef7a6e0ebc174a1ba138f6e16a9094f2
Signed-off-by: Jigar Agrawal <jigar@codeaurora.org>
This commit is contained in:
Jigar Agrawal
2020-12-08 13:11:52 -08:00
parent c17872806b
commit 28a19c52e1
18 changed files with 330 additions and 112 deletions
Download Patch File Download Diff File Expand all files Collapse all files

48
drivers/cam_utils/cam_soc_util.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/of.h>
@@ -361,19 +361,20 @@ long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info,
/**
* cam_soc_util_set_clk_rate()
*
* @brief: Sets the given rate for the clk requested for
* @brief: Sets the given rate for the clk requested for
*
* @clk: Clock structure information for which rate is to be set
* @clk_name: Name of the clock for which rate is being set
* @clk_rate Clock rate to be set
* @clk: Clock structure information for which rate is to be set
* @clk_name: Name of the clock for which rate is being set
* @clk_rate: Clock rate to be set
* @applied_clk_rate: Final clock rate set to the clk
*
* @return: Success or failure
*/
static int cam_soc_util_set_clk_rate(struct clk *clk, const char *clk_name,
int64_t clk_rate)
int64_t clk_rate, unsigned long *applied_clk_rate)
{
int rc = 0;
long clk_rate_round;
long clk_rate_round = -1;
if (!clk || !clk_name)
return -EINVAL;
@@ -410,6 +411,9 @@ static int cam_soc_util_set_clk_rate(struct clk *clk, const char *clk_name,
}
}
if (applied_clk_rate)
*applied_clk_rate = clk_rate_round;
return rc;
}
@@ -458,7 +462,8 @@ int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info,
}
rc = cam_soc_util_set_clk_rate(clk,
soc_info->clk_name[src_clk_idx], clk_rate);
soc_info->clk_name[src_clk_idx], clk_rate,
&soc_info->applied_src_clk_rate);
if (rc) {
CAM_ERR(CAM_UTIL,
"SET_RATE Failed: src clk: %s, rate %lld, dev_name = %s rc: %d",
@@ -478,7 +483,8 @@ int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info,
clk = soc_info->clk[scl_clk_idx];
rc = cam_soc_util_set_clk_rate(clk,
soc_info->clk_name[scl_clk_idx],
soc_info->clk_rate[apply_level][scl_clk_idx]);
soc_info->clk_rate[apply_level][scl_clk_idx],
NULL);
if (rc) {
CAM_WARN(CAM_UTIL,
"SET_RATE Failed: scl clk: %s, rate %d dev_name = %s, rc: %d",
@@ -585,14 +591,15 @@ int cam_soc_util_get_option_clk_by_name(struct cam_hw_soc_info *soc_info,
}
int cam_soc_util_clk_enable(struct clk *clk, const char *clk_name,
int32_t clk_rate)
int32_t clk_rate, unsigned long *applied_clock_rate)
{
int rc = 0;
if (!clk || !clk_name)
return -EINVAL;
rc = cam_soc_util_set_clk_rate(clk, clk_name, clk_rate);
rc = cam_soc_util_set_clk_rate(clk, clk_name, clk_rate,
applied_clock_rate);
if (rc)
return rc;
@@ -630,8 +637,9 @@ int cam_soc_util_clk_disable(struct clk *clk, const char *clk_name)
int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
enum cam_vote_level clk_level)
{
int i, rc = 0;
enum cam_vote_level apply_level;
int i, rc = 0;
enum cam_vote_level apply_level;
unsigned long applied_clk_rate;
if ((soc_info->num_clk == 0) ||
(soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
@@ -651,9 +659,14 @@ int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
for (i = 0; i < soc_info->num_clk; i++) {
rc = cam_soc_util_clk_enable(soc_info->clk[i],
soc_info->clk_name[i],
soc_info->clk_rate[apply_level][i]);
soc_info->clk_rate[apply_level][i],
&applied_clk_rate);
if (rc)
goto clk_disable;
if (i == soc_info->src_clk_idx)
soc_info->applied_src_clk_rate = applied_clk_rate;
if (soc_info->cam_cx_ipeak_enable) {
CAM_DBG(CAM_UTIL,
"dev name = %s clk name = %s idx = %d\n"
@@ -911,6 +924,7 @@ int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
{
int i, rc = 0;
enum cam_vote_level apply_level;
unsigned long applied_clk_rate;
if ((soc_info->num_clk == 0) ||
(soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
@@ -940,7 +954,8 @@ int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
rc = cam_soc_util_set_clk_rate(soc_info->clk[i],
soc_info->clk_name[i],
soc_info->clk_rate[apply_level][i]);
soc_info->clk_rate[apply_level][i],
&applied_clk_rate);
if (rc < 0) {
CAM_DBG(CAM_UTIL,
"dev name = %s clk_name = %s idx = %d\n"
@@ -951,6 +966,9 @@ int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0);
break;
}
if (i == soc_info->src_clk_idx)
soc_info->applied_src_clk_rate = applied_clk_rate;
}
return rc;