qcacmn: HAL changes for REO config for Beryllium
Add changes to HAL APIs for REO config for WCN7850 Change-Id: I91191a47c4782672fa19d45099cde05ee4cd04b1 CRs-Fixed: 2891049
此提交包含在：
Rakesh Pillai
@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2017-2019, 2021 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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@@ -38,6 +38,7 @@
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/* SW headers */
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#include "hal_api.h"
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#include "hal_rx_hw_defines.h"
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/*---------------------------------------------------------------------------
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Preprocessor definitions and constants
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@@ -77,9 +78,44 @@
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#define HAL_GET_TLV(desc) (((struct tlv_32_hdr *) desc)->tlv_tag)
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#define HAL_OFFSET_DW(_block, _field) (HAL_OFFSET(_block, _field) >> 2)
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#define HAL_OFFSET_QW(_block, _field) (HAL_OFFSET(_block, _field) >> 3)
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/* dword offsets in REO cmd TLV */
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#define CMD_HEADER_DW_OFFSET 0
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/* TODO: See if the following definition is available in HW headers */
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#define HAL_REO_OWNED 4
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#define HAL_REO_QUEUE_DESC 8
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/* TODO: Using associated link desc counter 1 for Rx. Check with FW on
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* how these counters are assigned
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*/
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#define HAL_RX_LINK_DESC_CNTR 1
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/* TODO: Following definition should be from HW headers */
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#define HAL_DESC_REO_OWNED 4
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#ifndef TID_TO_WME_AC
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/**
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* enum hal_wme_access_category: Access category enums
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* @WME_AC_BE: best effort
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* @WME_AC_BK: background
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* @WME_AC_VI: video
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* @WME_AC_VO: voice
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*/
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enum hal_wme_access_category {
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WME_AC_BE,
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WME_AC_BK,
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WME_AC_VI,
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WME_AC_VO
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};
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#define TID_TO_WME_AC(_tid) ( \
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(((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
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(((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
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(((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
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WME_AC_VO)
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#endif
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#define HAL_NON_QOS_TID 16
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/**
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* enum reo_unblock_cache_type: Enum for unblock type in REO unblock command
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* @UNBLOCK_RES_INDEX: Unblock a block resource
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@@ -122,25 +158,6 @@ enum reo_cmd_exec_status {
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HAL_REO_CMD_DRAIN = 0xff
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};
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/**
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* enum hal_reo_cmd_type: Enum for REO command type
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* @CMD_GET_QUEUE_STATS: Get REO queue status/stats
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* @CMD_FLUSH_QUEUE: Flush all frames in REO queue
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* @CMD_FLUSH_CACHE: Flush descriptor entries in the cache
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* @CMD_UNBLOCK_CACHE: Unblock a descriptor’s address that was blocked
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* earlier with a ‘REO_FLUSH_CACHE’ command
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* @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list
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* @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings
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*/
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enum hal_reo_cmd_type {
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CMD_GET_QUEUE_STATS = 0,
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CMD_FLUSH_QUEUE = 1,
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CMD_FLUSH_CACHE = 2,
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CMD_UNBLOCK_CACHE = 3,
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CMD_FLUSH_TIMEOUT_LIST = 4,
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CMD_UPDATE_RX_REO_QUEUE = 5
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};
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/**
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* struct hal_reo_cmd_params_std: Standard REO command parameters
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* @need_status: Status required for the command
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@@ -490,57 +507,317 @@ union hal_reo_status {
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struct hal_reo_update_rx_queue_status rx_queue_status;
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};
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/* Prototypes */
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#ifdef HAL_DISABLE_NON_BA_2K_JUMP_ERROR
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static inline uint32_t hal_update_non_ba_win_size(int tid,
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uint32_t ba_window_size)
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{
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return ba_window_size;
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}
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#else
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static inline uint32_t hal_update_non_ba_win_size(int tid,
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uint32_t ba_window_size)
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{
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if ((ba_window_size == 1) && (tid != HAL_NON_QOS_TID))
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ba_window_size++;
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return ba_window_size;
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}
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#endif
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#define BLOCK_RES_MASK 0xF
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static inline uint8_t hal_find_one_bit(uint8_t x)
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{
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uint8_t y = (x & (~x + 1)) & BLOCK_RES_MASK;
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uint8_t pos;
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for (pos = 0; y; y >>= 1)
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pos++;
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return pos-1;
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}
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static inline uint8_t hal_find_zero_bit(uint8_t x)
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{
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uint8_t y = (~x & (x+1)) & BLOCK_RES_MASK;
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uint8_t pos;
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for (pos = 0; y; y >>= 1)
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pos++;
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return pos-1;
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}
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/* REO command ring routines */
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void hal_reo_cmd_set_descr_addr(uint32_t *reo_desc,
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enum hal_reo_cmd_type type,
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uint32_t paddr_lo,
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uint8_t paddr_hi);
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int hal_reo_cmd_queue_stats(hal_ring_handle_t hal_ring_hdl,
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hal_soc_handle_t hal_soc_hdl,
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struct hal_reo_cmd_params *cmd);
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int hal_reo_cmd_flush_queue(hal_ring_handle_t hal_ring_hdl,
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hal_soc_handle_t hal_soc_hdl,
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struct hal_reo_cmd_params *cmd);
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int hal_reo_cmd_flush_cache(hal_ring_handle_t hal_ring_hdl,
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hal_soc_handle_t hal_soc_hdl,
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struct hal_reo_cmd_params *cmd);
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int hal_reo_cmd_unblock_cache(hal_ring_handle_t hal_ring_hdl,
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hal_soc_handle_t hal_soc_hdl,
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struct hal_reo_cmd_params *cmd);
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int hal_reo_cmd_flush_timeout_list(hal_ring_handle_t hal_ring_hdl,
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hal_soc_handle_t hal_soc_hdl,
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struct hal_reo_cmd_params *cmd);
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int hal_reo_cmd_update_rx_queue(hal_ring_handle_t hal_ring_hdl,
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hal_soc_handle_t hal_soc_hdl,
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struct hal_reo_cmd_params *cmd);
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/* REO status ring routines */
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void hal_reo_queue_stats_status(uint32_t *reo_desc,
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struct hal_reo_queue_status *st,
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hal_soc_handle_t hal_soc_hdl);
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void hal_reo_flush_queue_status(uint32_t *reo_desc,
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struct hal_reo_flush_queue_status *st,
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hal_soc_handle_t hal_soc_hdl);
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void hal_reo_flush_cache_status(uint32_t *reo_desc,
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struct hal_reo_flush_cache_status *st,
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hal_soc_handle_t hal_soc_hdl);
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void hal_reo_unblock_cache_status(uint32_t *reo_desc,
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hal_soc_handle_t hal_soc_hdl,
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struct hal_reo_unblk_cache_status *st);
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void hal_reo_flush_timeout_list_status(
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uint32_t *reo_desc,
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struct hal_reo_flush_timeout_list_status *st,
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hal_soc_handle_t hal_soc_hdl);
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void hal_reo_desc_thres_reached_status(
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uint32_t *reo_desc,
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struct hal_reo_desc_thres_reached_status *st,
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hal_soc_handle_t hal_soc_hdl);
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void hal_reo_rx_update_queue_status(uint32_t *reo_desc,
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struct hal_reo_update_rx_queue_status *st,
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hal_soc_handle_t hal_soc_hdl);
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/**
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* hal_uniform_desc_hdr_setup - setup reo_queue_ext descritpro
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* @owner - owner info
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* @buffer_type - buffer type
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*/
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static inline void
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hal_uniform_desc_hdr_setup(uint32_t *desc, uint32_t owner, uint32_t buffer_type)
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{
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HAL_DESC_SET_FIELD(desc, HAL_UNIFORM_DESCRIPTOR_HEADER, OWNER,
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owner);
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HAL_DESC_SET_FIELD(desc, HAL_UNIFORM_DESCRIPTOR_HEADER, BUFFER_TYPE,
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buffer_type);
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}
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/**
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* hal_reo_send_cmd() - Send reo cmd using the params provided.
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* @hal_soc_hdl: HAL soc handle
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* @hal_soc_hdl: srng handle
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* @cmd: cmd ID
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* @cmd_params: command params
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*
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* Return: cmd number
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*/
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static inline int
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hal_reo_send_cmd(hal_soc_handle_t hal_soc_hdl,
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hal_ring_handle_t hal_ring_hdl,
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enum hal_reo_cmd_type cmd,
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struct hal_reo_cmd_params *cmd_params)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (!hal_soc || !hal_soc->ops) {
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hal_err("hal handle is NULL");
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QDF_BUG(0);
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return -EINVAL;
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}
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if (hal_soc->ops->hal_reo_send_cmd)
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return hal_soc->ops->hal_reo_send_cmd(hal_soc_hdl, hal_ring_hdl,
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cmd, cmd_params);
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return -EINVAL;
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}
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/* REO Status ring routines */
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static inline void
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hal_reo_queue_stats_status(hal_ring_desc_t ring_desc,
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struct hal_reo_queue_status *st,
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hal_soc_handle_t hal_soc_hdl)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (!hal_soc || !hal_soc->ops) {
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hal_err("hal handle is NULL");
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QDF_BUG(0);
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return;
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}
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if (hal_soc->ops->hal_reo_queue_stats_status)
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return hal_soc->ops->hal_reo_queue_stats_status(ring_desc, st,
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hal_soc_hdl);
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}
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static inline void
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hal_reo_flush_queue_status(hal_ring_desc_t ring_desc,
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struct hal_reo_flush_queue_status *st,
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hal_soc_handle_t hal_soc_hdl)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (!hal_soc || !hal_soc->ops) {
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hal_err("hal handle is NULL");
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QDF_BUG(0);
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return;
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}
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if (hal_soc->ops->hal_reo_flush_queue_status)
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return hal_soc->ops->hal_reo_flush_queue_status(ring_desc, st,
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hal_soc_hdl);
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}
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static inline void
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hal_reo_flush_cache_status(hal_ring_desc_t ring_desc,
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struct hal_reo_flush_cache_status *st,
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hal_soc_handle_t hal_soc_hdl)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (!hal_soc || !hal_soc->ops) {
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hal_err("hal handle is NULL");
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QDF_BUG(0);
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return;
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}
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if (hal_soc->ops->hal_reo_flush_cache_status)
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return hal_soc->ops->hal_reo_flush_cache_status(ring_desc, st,
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hal_soc_hdl);
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}
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static inline void
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hal_reo_unblock_cache_status(hal_ring_desc_t ring_desc,
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hal_soc_handle_t hal_soc_hdl,
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struct hal_reo_unblk_cache_status *st)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (!hal_soc || !hal_soc->ops) {
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hal_err("hal handle is NULL");
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QDF_BUG(0);
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return;
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}
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if (hal_soc->ops->hal_reo_unblock_cache_status)
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return hal_soc->ops->hal_reo_unblock_cache_status(ring_desc,
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hal_soc_hdl,
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st);
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}
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static inline void hal_reo_flush_timeout_list_status(
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hal_ring_desc_t ring_desc,
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struct hal_reo_flush_timeout_list_status *st,
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hal_soc_handle_t hal_soc_hdl)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (!hal_soc || !hal_soc->ops) {
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hal_err("hal handle is NULL");
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QDF_BUG(0);
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return;
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}
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if (hal_soc->ops->hal_reo_flush_timeout_list_status)
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return hal_soc->ops->hal_reo_flush_timeout_list_status(
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ring_desc, st,
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hal_soc_hdl);
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}
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static inline void hal_reo_desc_thres_reached_status(
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hal_ring_desc_t ring_desc,
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struct hal_reo_desc_thres_reached_status *st,
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hal_soc_handle_t hal_soc_hdl)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (!hal_soc || !hal_soc->ops) {
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hal_err("hal handle is NULL");
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QDF_BUG(0);
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return;
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}
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if (hal_soc->ops->hal_reo_desc_thres_reached_status)
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return hal_soc->ops->hal_reo_desc_thres_reached_status(
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ring_desc, st,
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hal_soc_hdl);
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}
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static inline void
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hal_reo_rx_update_queue_status(hal_ring_desc_t ring_desc,
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struct hal_reo_update_rx_queue_status *st,
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hal_soc_handle_t hal_soc_hdl)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (!hal_soc || !hal_soc->ops) {
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hal_err("hal handle is NULL");
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QDF_BUG(0);
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return;
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}
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if (hal_soc->ops->hal_reo_rx_update_queue_status)
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return hal_soc->ops->hal_reo_rx_update_queue_status(
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ring_desc, st, hal_soc_hdl);
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}
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static inline void hal_reo_qdesc_setup(hal_soc_handle_t hal_soc_hdl, int tid,
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uint32_t ba_window_size,
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uint32_t start_seq, void *hw_qdesc_vaddr,
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qdf_dma_addr_t hw_qdesc_paddr,
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int pn_type)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (!hal_soc || !hal_soc->ops) {
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hal_err("hal handle is NULL");
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QDF_BUG(0);
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return;
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}
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if (hal_soc->ops->hal_reo_qdesc_setup)
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hal_soc->ops->hal_reo_qdesc_setup(hal_soc_hdl, tid,
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ba_window_size, start_seq,
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hw_qdesc_vaddr,
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hw_qdesc_paddr, pn_type);
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}
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/**
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* hal_get_ba_aging_timeout - Retrieve BA aging timeout
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*
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* @hal_soc: Opaque HAL SOC handle
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* @ac: Access category
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* @value: timeout duration in millisec
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*/
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static inline void hal_get_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl,
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uint8_t ac,
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uint32_t *value)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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hal_soc->ops->hal_get_ba_aging_timeout(hal_soc_hdl, ac, value);
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}
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/**
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* hal_set_aging_timeout - Set BA aging timeout
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*
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* @hal_soc: Opaque HAL SOC handle
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* @ac: Access category in millisec
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* @value: timeout duration value
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*/
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static inline void hal_set_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl,
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uint8_t ac,
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uint32_t value)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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hal_soc->ops->hal_set_ba_aging_timeout(hal_soc_hdl, ac, value);
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}
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/**
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* hal_get_reo_reg_base_offset() - Get REO register base offset
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* @hal_soc_hdl: HAL soc handle
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*
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* Return: REO register base
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*/
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static inline uint32_t hal_get_reo_reg_base_offset(hal_soc_handle_t hal_soc_hdl)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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return hal_soc->ops->hal_get_reo_reg_base_offset();
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}
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static inline uint32_t
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hal_gen_reo_remap_val(hal_soc_handle_t hal_soc_hdl,
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enum hal_reo_remap_reg remap_reg,
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uint8_t *ix0_map)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (!hal_soc || !hal_soc->ops) {
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hal_err("hal handle is NULL");
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QDF_BUG(0);
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return 0;
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}
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if (hal_soc->ops->hal_gen_reo_remap_val)
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return hal_soc->ops->hal_gen_reo_remap_val(remap_reg, ix0_map);
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return 0;
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}
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/* Function Proto-types */
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/**
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* hal_reo_init_cmd_ring() - Initialize descriptors of REO command SRNG
|
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* with command number
|
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* @hal_soc: Handle to HAL SoC structure
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* @hal_ring: Handle to HAL SRNG structure
|
||||
*
|
||||
* Return: none
|
||||
*/
|
||||
void hal_reo_init_cmd_ring(hal_soc_handle_t hal_soc_hdl,
|
||||
hal_ring_handle_t hal_ring_hdl);
|
||||
|
||||
#endif /* _HAL_REO_H */
|
||||
|
||||
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