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@@ -258,6 +258,7 @@ enum reg_domain {
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ETSI4_WORLD = 0x30,
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ETSI8_WORLD = 0x3D,
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ETSI9_WORLD = 0x3E,
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+ ETSI11_WORLD = 0x26,
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APL1_WORLD = 0x52,
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APL1_ETSIC = 0x55,
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@@ -547,6 +548,7 @@ enum reg_domains_5g {
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ETSI4,
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ETSI8,
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ETSI9,
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+ ETSI11,
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APL1,
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APL2,
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APL4,
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@@ -591,6 +593,7 @@ const struct reg_domain_pair g_reg_dmn_pairs[] = {
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{ETSI4_WORLD, ETSI4, WORLD},
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{ETSI8_WORLD, ETSI8, WORLD},
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{ETSI9_WORLD, ETSI9, WORLD},
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+ {ETSI11_WORLD, ETSI11, WORLD},
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{APL1_WORLD, APL1, WORLD},
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{APL1_ETSIC, APL1, ETSIC},
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@@ -688,6 +691,8 @@ enum reg_rules_5g {
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CHAN_5170_5250_2,
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CHAN_5170_5250_3,
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CHAN_5170_5250_4,
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+ CHAN_5170_5250_5,
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+ CHAN_5170_5250_6,
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CHAN_5170_5330_1,
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CHAN_5250_5330_1,
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CHAN_5250_5330_2,
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@@ -695,15 +700,18 @@ enum reg_rules_5g {
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CHAN_5250_5330_4,
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CHAN_5250_5330_5,
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CHAN_5250_5330_6,
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+ CHAN_5250_5330_7,
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CHAN_5490_5730_1,
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CHAN_5490_5730_2,
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CHAN_5490_5730_3,
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CHAN_5490_5710_1,
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CHAN_5490_5710_2,
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+ CHAN_5490_5710_3,
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CHAN_5490_5590_1,
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CHAN_5490_5590_2,
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CHAN_5490_5570_1,
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CHAN_5490_5650_1,
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+ CHAN_5490_5650_2,
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CHAN_5490_5670_1,
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CHAN_5490_5630_1,
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CHAN_5650_5730_1,
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@@ -713,6 +721,8 @@ enum reg_rules_5g {
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CHAN_5735_5835_3,
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CHAN_5735_5835_4,
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CHAN_5735_5835_5,
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+ CHAN_5735_5835_6,
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+ CHAN_5735_5875_1,
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CHAN_5735_5815_1,
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CHAN_5735_5775_1,
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};
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@@ -726,31 +736,38 @@ const struct regulatory_rule reg_rules_5g[] = {
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[CHAN_5170_5250_2] = {5170, 5250, 80, 23, 0},
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[CHAN_5170_5250_3] = {5170, 5250, 80, 20, 0},
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[CHAN_5170_5250_4] = {5170, 5250, 80, 30, 0},
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+ [CHAN_5170_5250_5] = {5170, 5250, 80, 24, 0},
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+ [CHAN_5170_5250_6] = {5170, 5250, 80, 18, 0},
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[CHAN_5170_5330_1] = {5170, 5330, 160, 20, REGULATORY_CHAN_NO_IR},
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[CHAN_5250_5330_1] = {5250, 5330, 80, 23, REGULATORY_CHAN_RADAR},
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[CHAN_5250_5330_2] = {5250, 5330, 80, 20, REGULATORY_CHAN_RADAR},
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- [CHAN_5250_5330_3] = {5250, 5330, 80, 17, REGULATORY_CHAN_RADAR},
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+ [CHAN_5250_5330_3] = {5250, 5330, 80, 18, REGULATORY_CHAN_RADAR},
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[CHAN_5250_5330_4] = {5250, 5330, 80, 30, REGULATORY_CHAN_RADAR},
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[CHAN_5250_5330_5] = {5250, 5330, 80, 23, 0},
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[CHAN_5250_5330_6] = {5250, 5330, 80, 30, 0},
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- [CHAN_5490_5730_1] = {5490, 5730, 160, 23, REGULATORY_CHAN_RADAR},
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+ [CHAN_5250_5330_7] = {5250, 5330, 80, 24, REGULATORY_CHAN_RADAR},
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+ [CHAN_5490_5730_1] = {5490, 5730, 160, 24, REGULATORY_CHAN_RADAR},
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[CHAN_5490_5730_2] = {5490, 5730, 160, 30, REGULATORY_CHAN_RADAR},
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[CHAN_5490_5730_3] = {5490, 5730, 160, 20, REGULATORY_CHAN_NO_IR},
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[CHAN_5490_5710_1] = {5490, 5710, 160, 30, REGULATORY_CHAN_RADAR},
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[CHAN_5490_5710_2] = {5490, 5710, 160, 20, REGULATORY_CHAN_RADAR},
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- [CHAN_5490_5590_1] = {5490, 5590, 80, 23, REGULATORY_CHAN_RADAR},
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+ [CHAN_5490_5710_3] = {5490, 5710, 160, 27, REGULATORY_CHAN_RADAR},
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+ [CHAN_5490_5590_1] = {5490, 5590, 80, 24, REGULATORY_CHAN_RADAR},
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[CHAN_5490_5590_2] = {5490, 5590, 80, 30, 0},
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[CHAN_5490_5570_1] = {5490, 5570, 80, 30, REGULATORY_CHAN_RADAR},
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[CHAN_5490_5650_1] = {5490, 5650, 160, 23, REGULATORY_CHAN_RADAR},
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+ [CHAN_5490_5650_2] = {5490, 5650, 160, 24, REGULATORY_CHAN_RADAR},
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[CHAN_5490_5670_1] = {5490, 5670, 160, 20, REGULATORY_CHAN_RADAR},
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[CHAN_5490_5630_1] = {5490, 5630, 80, 30, REGULATORY_CHAN_RADAR},
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- [CHAN_5650_5730_1] = {5650, 5730, 80, 23, REGULATORY_CHAN_RADAR},
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+ [CHAN_5650_5730_1] = {5650, 5730, 80, 24, REGULATORY_CHAN_RADAR},
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[CHAN_5650_5730_2] = {5650, 5730, 80, 30, 0},
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[CHAN_5735_5835_1] = {5735, 5835, 80, 23, 0},
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[CHAN_5735_5835_2] = {5735, 5835, 80, 30, 0},
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[CHAN_5735_5835_3] = {5735, 5835, 80, 20, 0},
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[CHAN_5735_5835_4] = {5735, 5835, 80, 27, 0},
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[CHAN_5735_5835_5] = {5735, 5835, 80, 20, REGULATORY_CHAN_NO_IR},
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+ [CHAN_5735_5835_6] = {5735, 5835, 80, 24, 0},
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+ [CHAN_5735_5875_1] = {5735, 5875, 20, 27, 0},
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[CHAN_5735_5815_1] = {5735, 5815, 80, 30, 0},
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[CHAN_5735_5775_1] = {5735, 5775, 40, 23, 0},
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};
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@@ -760,37 +777,37 @@ const struct regdomain regdomains_5g[] = {
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[FCC1] = {CTL_FCC, DFS_FCC_REG, 2, 6, 3, {CHAN_5170_5250_1,
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CHAN_5250_5330_1,
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- CHAN_5735_5835_1} },
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+ CHAN_5735_5835_2} },
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- [FCC2] = {CTL_FCC, DFS_CN_REG, 2, 6, 3, {CHAN_5170_5250_2,
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+ [FCC2] = {CTL_FCC, DFS_FCC_REG, 2, 6, 3, {CHAN_5170_5250_2,
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CHAN_5250_5330_1,
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- CHAN_5735_5835_1} },
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+ CHAN_5735_5835_2} },
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- [FCC3] = {CTL_FCC, DFS_FCC_REG, 2, 6, 4, {CHAN_5170_5250_2,
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- CHAN_5250_5330_1,
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+ [FCC3] = {CTL_FCC, DFS_FCC_REG, 2, 6, 4, {CHAN_5170_5250_5,
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+ CHAN_5250_5330_7,
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CHAN_5490_5730_1,
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- CHAN_5735_5835_1} },
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+ CHAN_5735_5835_2} },
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[FCC4] = {CTL_FCC, DFS_FCC_REG, 2, 6, 4, {CHAN_4940_4990_1,
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CHAN_5170_5250_1,
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- CHAN_5250_5330_1,
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- CHAN_5735_5835_1} },
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+ CHAN_5250_5330_7,
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+ CHAN_5735_5835_2} },
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- [FCC6] = {CTL_FCC, DFS_FCC_REG, 2, 6, 5, {CHAN_5170_5250_2,
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- CHAN_5250_5330_1,
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+ [FCC6] = {CTL_FCC, DFS_FCC_REG, 2, 6, 5, {CHAN_5170_5250_5,
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+ CHAN_5250_5330_7,
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CHAN_5490_5590_1,
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CHAN_5650_5730_1,
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- CHAN_5735_5835_1} },
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+ CHAN_5735_5835_2} },
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[FCC8] = {CTL_FCC, DFS_FCC_REG, 2, 6, 4, {CHAN_5170_5250_4,
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- CHAN_5250_5330_1,
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+ CHAN_5250_5330_7,
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CHAN_5490_5730_1,
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- CHAN_5735_5835_1} },
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+ CHAN_5735_5835_2} },
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- [FCC11] = {CTL_FCC, DFS_FCC_REG, 2, 6, 4, {CHAN_5170_5250_2,
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- CHAN_5250_5330_1,
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- CHAN_5490_5650_1,
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- CHAN_5735_5835_1} },
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+ [FCC11] = {CTL_FCC, DFS_FCC_REG, 2, 6, 4, {CHAN_5170_5250_5,
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+ CHAN_5250_5330_7,
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+ CHAN_5490_5650_2,
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+ CHAN_5735_5835_6} },
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[ETSI1] = {CTL_ETSI, DFS_ETSI_REG, 5, 0, 3, {CHAN_5170_5250_2,
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CHAN_5250_5330_1,
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@@ -799,7 +816,7 @@ const struct regdomain regdomains_5g[] = {
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[ETSI3] = {CTL_ETSI, DFS_ETSI_REG, 5, 0, 2, {CHAN_5170_5250_3,
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CHAN_5250_5330_2} },
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- [ETSI4] = {CTL_ETSI, DFS_ETSI_REG, 5, 0, 2, {CHAN_5170_5250_1,
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+ [ETSI4] = {CTL_ETSI, DFS_ETSI_REG, 5, 0, 2, {CHAN_5170_5250_6,
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CHAN_5250_5330_3} },
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[ETSI8] = {CTL_ETSI, DFS_ETSI_REG, 20, 0, 4, {CHAN_5170_5250_3,
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@@ -812,6 +829,11 @@ const struct regdomain regdomains_5g[] = {
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CHAN_5490_5670_1,
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CHAN_5735_5835_3} },
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+ [ETSI11] = {CTL_ETSI, DFS_ETSI_REG, 10, 0, 4, {CHAN_5170_5250_3,
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+ CHAN_5250_5330_2,
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+ CHAN_5490_5710_3,
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+ CHAN_5735_5875_1} },
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+
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[APL1] = {CTL_ETSI, DFS_UNINIT_REG, 2, 0, 1, {CHAN_5735_5835_2} },
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[APL2] = {CTL_ETSI, DFS_UNINIT_REG, 2, 0, 1, {CHAN_5735_5815_1} },
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@@ -828,15 +850,15 @@ const struct regdomain regdomains_5g[] = {
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[APL9] = {CTL_ETSI, DFS_KR_REG, 2, 6, 4, {CHAN_5170_5250_3,
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CHAN_5250_5330_2,
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- CHAN_5490_5630_1,
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- CHAN_5735_5815_1} },
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+ CHAN_5490_5730_2,
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+ CHAN_5735_5835_2} },
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- [APL10] = {CTL_ETSI, DFS_ETSI_REG, 2, 6, 4, {CHAN_5170_5250_3,
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+ [APL10] = {CTL_ETSI, DFS_FCC_REG, 2, 6, 4, {CHAN_5170_5250_3,
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CHAN_5250_5330_2,
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CHAN_5490_5710_1,
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CHAN_5735_5815_1} },
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- [APL12] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 3, {CHAN_5170_5250_1,
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+ [APL12] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 3, {CHAN_5170_5250_2,
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CHAN_5490_5570_1,
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CHAN_5735_5775_1} },
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