samsung-sm8650/android_kernel_samsung_sm8650-modules
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

asoc: lpass-cdc: changes for bolero v2.2

Browse Source 
Implement changes to make the driver compatible with bolero V2.2.

Change-Id: If2797a80f775c685ff2a6912de189b1d9b4906d0
Signed-off-by: Vangala, Amarnath <quic_avangala@quicinc.com>
This commit is contained in:
Vangala, Amarnath
2023-12-28 17:52:45 +05:30
committed by Prasad Kumpatla
parent 641fe28ac7
commit 2792b38785
7 changed files with 631 additions and 369 deletions
Download Patch File Download Diff File Expand all files Collapse all files

52
asoc/codecs/lpass-cdc/lpass-cdc-clk-rsc.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#include <linux/of_platform.h> #include <linux/of_platform.h>
@@ -17,6 +17,7 @@
#define DRV_NAME "lpass-cdc-clk-rsc" #define DRV_NAME "lpass-cdc-clk-rsc"
#define LPASS_CDC_CLK_NAME_LENGTH 30 #define LPASS_CDC_CLK_NAME_LENGTH 30
#define NPL_CLK_OFFSET (TX_NPL_CLK - TX_CORE_CLK)
static char clk_src_name[MAX_CLK][LPASS_CDC_CLK_NAME_LENGTH] = { static char clk_src_name[MAX_CLK][LPASS_CDC_CLK_NAME_LENGTH] = {
"tx_core_clk", "tx_core_clk",
@@ -27,6 +28,10 @@ static char clk_src_name[MAX_CLK][LPASS_CDC_CLK_NAME_LENGTH] = {
"rx_tx_core_clk", "rx_tx_core_clk",
"wsa_tx_core_clk", "wsa_tx_core_clk",
"wsa2_tx_core_clk", "wsa2_tx_core_clk",
"tx_npl_clk",
"rx_npl_clk",
"wsa_npl_clk",
"va_npl_clk",
}; };
struct lpass_cdc_clk_rsc { struct lpass_cdc_clk_rsc {
@@ -113,7 +118,7 @@ int lpass_cdc_rsc_clk_reset(struct device *dev, int clk_id)
return -EINVAL; return -EINVAL;
} }
if (clk_id < 0 || clk_id >= MAX_CLK) { if (clk_id < 0 || clk_id >= MAX_CLK - NPL_CLK_OFFSET) {
pr_err("%s: Invalid clk_id: %d\n", pr_err("%s: Invalid clk_id: %d\n",
__func__, clk_id); __func__, clk_id);
return -EINVAL; return -EINVAL;
@@ -132,6 +137,7 @@ int lpass_cdc_rsc_clk_reset(struct device *dev, int clk_id)
} }
mutex_lock(&priv->rsc_clk_lock); mutex_lock(&priv->rsc_clk_lock);
while (__clk_is_enabled(priv->clk[clk_id])) { while (__clk_is_enabled(priv->clk[clk_id])) {
clk_disable_unprepare(priv->clk[clk_id + NPL_CLK_OFFSET]);
clk_disable_unprepare(priv->clk[clk_id]); clk_disable_unprepare(priv->clk[clk_id]);
count++; count++;
} }
@@ -140,6 +146,7 @@ int lpass_cdc_rsc_clk_reset(struct device *dev, int clk_id)
while (count--) { while (count--) {
clk_prepare_enable(priv->clk[clk_id]); clk_prepare_enable(priv->clk[clk_id]);
clk_prepare_enable(priv->clk[clk_id + NPL_CLK_OFFSET]);
} }
mutex_unlock(&priv->rsc_clk_lock); mutex_unlock(&priv->rsc_clk_lock);
return 0; return 0;
@@ -169,12 +176,18 @@ void lpass_cdc_clk_rsc_enable_all_clocks(struct device *dev, bool enable)
return; return;
} }
mutex_lock(&priv->rsc_clk_lock); mutex_lock(&priv->rsc_clk_lock);
for (i = 0; i < MAX_CLK; i++) { for (i = 0; i < MAX_CLK - NPL_CLK_OFFSET; i++) {
if (enable) { if (enable) {
if (priv->clk[i]) if (priv->clk[i])
clk_prepare_enable(priv->clk[i]); clk_prepare_enable(priv->clk[i]);
if (priv->clk[i + NPL_CLK_OFFSET])
clk_prepare_enable(
priv->clk[i + NPL_CLK_OFFSET]);
} else { } else {
if (priv->clk[i] && __clk_is_enabled(priv->clk[i])) if (priv->clk[i + NPL_CLK_OFFSET])
clk_disable_unprepare(
priv->clk[i + NPL_CLK_OFFSET]);
if (priv->clk[i])
clk_disable_unprepare(priv->clk[i]); clk_disable_unprepare(priv->clk[i]);
} }
} }
@@ -198,6 +211,15 @@ static int lpass_cdc_clk_rsc_mux0_clk_request(struct lpass_cdc_clk_rsc *priv,
__func__, clk_id); __func__, clk_id);
goto done; goto done;
} }
if (priv->clk[clk_id + NPL_CLK_OFFSET]) {
ret = clk_prepare_enable(
priv->clk[clk_id + NPL_CLK_OFFSET]);
if (ret < 0) {
dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
__func__, clk_id + NPL_CLK_OFFSET);
goto err;
}
}
} }
priv->clk_cnt[clk_id]++; priv->clk_cnt[clk_id]++;
} else { } else {
@@ -208,9 +230,16 @@ static int lpass_cdc_clk_rsc_mux0_clk_request(struct lpass_cdc_clk_rsc *priv,
goto done; goto done;
} }
priv->clk_cnt[clk_id]--; priv->clk_cnt[clk_id]--;
if (priv->clk_cnt[clk_id] == 0) if (priv->clk_cnt[clk_id] == 0) {
if (priv->clk[clk_id + NPL_CLK_OFFSET])
clk_disable_unprepare(
priv->clk[clk_id + NPL_CLK_OFFSET]);
clk_disable_unprepare(priv->clk[clk_id]); clk_disable_unprepare(priv->clk[clk_id]);
} }
}
return ret;
err:
clk_disable_unprepare(priv->clk[clk_id]);
done: done:
return ret; return ret;
} }
@@ -246,6 +275,15 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
__func__, clk_id); __func__, clk_id);
goto err_clk; goto err_clk;
} }
if (priv->clk[clk_id + NPL_CLK_OFFSET]) {
ret = clk_prepare_enable(
priv->clk[clk_id + NPL_CLK_OFFSET]);
if (ret < 0) {
dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
__func__, clk_id + NPL_CLK_OFFSET);
goto err_npl_clk;
}
}
/* /*
* Temp SW workaround to address a glitch issue of * Temp SW workaround to address a glitch issue of
* VA GFMux instance responsible for switching from * VA GFMux instance responsible for switching from
@@ -286,6 +324,8 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
muxsel = ioread32(clk_muxsel); muxsel = ioread32(clk_muxsel);
} }
} }
if (priv->clk[clk_id + NPL_CLK_OFFSET])
clk_disable_unprepare(priv->clk[clk_id + NPL_CLK_OFFSET]);
clk_disable_unprepare(priv->clk[clk_id]); clk_disable_unprepare(priv->clk[clk_id]);
if (clk_id != VA_CORE_CLK && !ret) if (clk_id != VA_CORE_CLK && !ret)
lpass_cdc_clk_rsc_mux0_clk_request(priv, lpass_cdc_clk_rsc_mux0_clk_request(priv,
@@ -293,6 +333,8 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
} }
} }
return ret; return ret;
err_npl_clk:
clk_disable_unprepare(priv->clk[clk_id]);
err_clk: err_clk:
if (clk_id != VA_CORE_CLK) if (clk_id != VA_CORE_CLK)

336
asoc/codecs/lpass-cdc/lpass-cdc-registers.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. /* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#ifndef _LPASS_CDC_REGISTERS_H #ifndef _LPASS_CDC_REGISTERS_H
@@ -14,6 +14,7 @@
#define LPASS_CDC_TX_TOP_CSR_TOP_CFG0 (TX_START_OFFSET + 0x0080) #define LPASS_CDC_TX_TOP_CSR_TOP_CFG0 (TX_START_OFFSET + 0x0080)
#define LPASS_CDC_TX_TOP_CSR_ANC_CFG (TX_START_OFFSET + 0x0084) #define LPASS_CDC_TX_TOP_CSR_ANC_CFG (TX_START_OFFSET + 0x0084)
#define LPASS_CDC_TX_TOP_CSR_SWR_CTRL (TX_START_OFFSET + 0x0088) #define LPASS_CDC_TX_TOP_CSR_SWR_CTRL (TX_START_OFFSET + 0x0088)
#define LPASS_CDC_TX_TOP_CSR_FREQ_MCLK (TX_START_OFFSET + 0x0090)
#define LPASS_CDC_TX_TOP_CSR_DEBUG_BUS (TX_START_OFFSET + 0x0094) #define LPASS_CDC_TX_TOP_CSR_DEBUG_BUS (TX_START_OFFSET + 0x0094)
#define LPASS_CDC_TX_TOP_CSR_DEBUG_EN (TX_START_OFFSET + 0x0098) #define LPASS_CDC_TX_TOP_CSR_DEBUG_EN (TX_START_OFFSET + 0x0098)
#define LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL (TX_START_OFFSET + 0x00A4) #define LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL (TX_START_OFFSET + 0x00A4)
@@ -289,6 +290,143 @@
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x0450) #define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x0450)
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x0454) #define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x0454)
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x0458) #define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x0458)
#define LPASS_CDC_RX_IDLE_DETECT_PATH_CTL (RX_START_OFFSET + 0x0780)
#define LPASS_CDC_RX_IDLE_DETECT_CFG0 (RX_START_OFFSET + 0x0784)
#define LPASS_CDC_RX_IDLE_DETECT_CFG1 (RX_START_OFFSET + 0x0788)
#define LPASS_CDC_RX_IDLE_DETECT_CFG2 (RX_START_OFFSET + 0x078C)
#define LPASS_CDC_RX_IDLE_DETECT_CFG3 (RX_START_OFFSET + 0x0790)
#define LPASS_CDC_RX_COMPANDER0_CTL0 (RX_START_OFFSET + 0x0800)
#define LPASS_CDC_RX_COMPANDER0_CTL1 (RX_START_OFFSET + 0x0804)
#define LPASS_CDC_RX_COMPANDER0_CTL2 (RX_START_OFFSET + 0x0808)
#define LPASS_CDC_RX_COMPANDER0_CTL3 (RX_START_OFFSET + 0x080C)
#define LPASS_CDC_RX_COMPANDER0_CTL4 (RX_START_OFFSET + 0x0810)
#define LPASS_CDC_RX_COMPANDER0_CTL5 (RX_START_OFFSET + 0x0814)
#define LPASS_CDC_RX_COMPANDER0_CTL6 (RX_START_OFFSET + 0x0818)
#define LPASS_CDC_RX_COMPANDER0_CTL7 (RX_START_OFFSET + 0x081C)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL \
(RX_START_OFFSET + 0x0A00)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL \
(RX_START_OFFSET + 0x0A04)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL \
(RX_START_OFFSET + 0x0A08)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL \
(RX_START_OFFSET + 0x0A0C)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL \
(RX_START_OFFSET + 0x0A10)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL \
(RX_START_OFFSET + 0x0A14)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL \
(RX_START_OFFSET + 0x0A18)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL \
(RX_START_OFFSET + 0x0A1C)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL \
(RX_START_OFFSET + 0x0A20)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_CTL (RX_START_OFFSET + 0x0A24)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL \
(RX_START_OFFSET + 0x0A28)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL \
(RX_START_OFFSET + 0x0A2C)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL \
(RX_START_OFFSET + 0x0A30)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL \
(RX_START_OFFSET + 0x0A80)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL \
(RX_START_OFFSET + 0x0A84)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL \
(RX_START_OFFSET + 0x0A88)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL \
(RX_START_OFFSET + 0x0A8C)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL \
(RX_START_OFFSET + 0x0A90)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL \
(RX_START_OFFSET + 0x0A94)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL \
(RX_START_OFFSET + 0x0A98)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL \
(RX_START_OFFSET + 0x0A9C)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL \
(RX_START_OFFSET + 0x0AA0)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_CTL (RX_START_OFFSET + 0x0AA4)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL \
(RX_START_OFFSET + 0x0AA8)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL \
(RX_START_OFFSET + 0x0AAC)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL \
(RX_START_OFFSET + 0x0AB0)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0 (RX_START_OFFSET + 0x0B00)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1 (RX_START_OFFSET + 0x0B04)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2 (RX_START_OFFSET + 0x0B08)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3 (RX_START_OFFSET + 0x0B0C)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0 (RX_START_OFFSET + 0x0B10)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1 (RX_START_OFFSET + 0x0B14)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2 (RX_START_OFFSET + 0x0B18)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3 (RX_START_OFFSET + 0x0B1C)
#define LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL \
(RX_START_OFFSET + 0x0B40)
#define LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 \
(RX_START_OFFSET + 0x0B44)
#define LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL \
(RX_START_OFFSET + 0x0B50)
#define LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 \
(RX_START_OFFSET + 0x0B54)
#define LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL \
(RX_START_OFFSET + 0x0C00)
#define LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C04)
#define LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL \
(RX_START_OFFSET + 0x0C40)
#define LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C44)
#define LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL \
(RX_START_OFFSET + 0x0C80)
#define LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C84)
#define LPASS_CDC_RX_EC_ASRC0_CLK_RST_CTL (RX_START_OFFSET + 0x0D00)
#define LPASS_CDC_RX_EC_ASRC0_CTL0 (RX_START_OFFSET + 0x0D04)
#define LPASS_CDC_RX_EC_ASRC0_CTL1 (RX_START_OFFSET + 0x0D08)
#define LPASS_CDC_RX_EC_ASRC0_FIFO_CTL (RX_START_OFFSET + 0x0D0C)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB \
(RX_START_OFFSET + 0x0D10)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB \
(RX_START_OFFSET + 0x0D14)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB \
(RX_START_OFFSET + 0x0D18)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB \
(RX_START_OFFSET + 0x0D1C)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FIFO (RX_START_OFFSET + 0x0D20)
#define LPASS_CDC_RX_EC_ASRC1_CLK_RST_CTL (RX_START_OFFSET + 0x0D40)
#define LPASS_CDC_RX_EC_ASRC1_CTL0 (RX_START_OFFSET + 0x0D44)
#define LPASS_CDC_RX_EC_ASRC1_CTL1 (RX_START_OFFSET + 0x0D48)
#define LPASS_CDC_RX_EC_ASRC1_FIFO_CTL (RX_START_OFFSET + 0x0D4C)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB \
(RX_START_OFFSET + 0x0D50)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB \
(RX_START_OFFSET + 0x0D54)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB \
(RX_START_OFFSET + 0x0D58)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB \
(RX_START_OFFSET + 0x0D5C)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FIFO (RX_START_OFFSET + 0x0D60)
#define LPASS_CDC_RX_EC_ASRC2_CLK_RST_CTL (RX_START_OFFSET + 0x0D80)
#define LPASS_CDC_RX_EC_ASRC2_CTL0 (RX_START_OFFSET + 0x0D84)
#define LPASS_CDC_RX_EC_ASRC2_CTL1 (RX_START_OFFSET + 0x0D88)
#define LPASS_CDC_RX_EC_ASRC2_FIFO_CTL (RX_START_OFFSET + 0x0D8C)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB \
(RX_START_OFFSET + 0x0D90)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB \
(RX_START_OFFSET + 0x0D94)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB \
(RX_START_OFFSET + 0x0D98)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB \
(RX_START_OFFSET + 0x0D9C)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FIFO (RX_START_OFFSET + 0x0DA0)
#define LPASS_CDC_RX_DSD0_PATH_CTL (RX_START_OFFSET + 0x0F00)
#define LPASS_CDC_RX_DSD0_CFG0 (RX_START_OFFSET + 0x0F04)
#define LPASS_CDC_RX_DSD0_CFG1 (RX_START_OFFSET + 0x0F08)
#define LPASS_CDC_RX_DSD0_CFG2 (RX_START_OFFSET + 0x0F0C)
#define LPASS_CDC_RX_DSD1_PATH_CTL (RX_START_OFFSET + 0x0F80)
#define LPASS_CDC_RX_DSD1_CFG0 (RX_START_OFFSET + 0x0F84)
#define LPASS_CDC_RX_DSD1_CFG1 (RX_START_OFFSET + 0x0F88)
#define LPASS_CDC_RX_DSD1_CFG2 (RX_START_OFFSET + 0x0F8C)
#ifdef CONFIG_BOLERO_VER_2P6
#define LPASS_CDC_RX_RX0_RX_FIR_CTL (RX_START_OFFSET + 0x045C) #define LPASS_CDC_RX_RX0_RX_FIR_CTL (RX_START_OFFSET + 0x045C)
#define LPASS_CDC_RX_RX0_RX_FIR_CFG (RX_START_OFFSET + 0x0460) #define LPASS_CDC_RX_RX0_RX_FIR_CFG (RX_START_OFFSET + 0x0460)
#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR (RX_START_OFFSET + 0x0464) #define LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR (RX_START_OFFSET + 0x0464)
@@ -420,19 +558,7 @@
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1 (RX_START_OFFSET + 0x0700) #define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1 (RX_START_OFFSET + 0x0700)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2 (RX_START_OFFSET + 0x0704) #define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2 (RX_START_OFFSET + 0x0704)
#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3 (RX_START_OFFSET + 0x0708) #define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3 (RX_START_OFFSET + 0x0708)
#define LPASS_CDC_RX_IDLE_DETECT_PATH_CTL (RX_START_OFFSET + 0x0780)
#define LPASS_CDC_RX_IDLE_DETECT_CFG0 (RX_START_OFFSET + 0x0784)
#define LPASS_CDC_RX_IDLE_DETECT_CFG1 (RX_START_OFFSET + 0x0788)
#define LPASS_CDC_RX_IDLE_DETECT_CFG2 (RX_START_OFFSET + 0x078C)
#define LPASS_CDC_RX_IDLE_DETECT_CFG3 (RX_START_OFFSET + 0x0790)
#define LPASS_CDC_RX_COMPANDER0_CTL0 (RX_START_OFFSET + 0x0800)
#define LPASS_CDC_RX_COMPANDER0_CTL1 (RX_START_OFFSET + 0x0804)
#define LPASS_CDC_RX_COMPANDER0_CTL2 (RX_START_OFFSET + 0x0808)
#define LPASS_CDC_RX_COMPANDER0_CTL3 (RX_START_OFFSET + 0x080C)
#define LPASS_CDC_RX_COMPANDER0_CTL4 (RX_START_OFFSET + 0x0810)
#define LPASS_CDC_RX_COMPANDER0_CTL5 (RX_START_OFFSET + 0x0814)
#define LPASS_CDC_RX_COMPANDER0_CTL6 (RX_START_OFFSET + 0x0818)
#define LPASS_CDC_RX_COMPANDER0_CTL7 (RX_START_OFFSET + 0x081C)
#define LPASS_CDC_RX_COMPANDER0_CTL8 (RX_START_OFFSET + 0x0820) #define LPASS_CDC_RX_COMPANDER0_CTL8 (RX_START_OFFSET + 0x0820)
#define LPASS_CDC_RX_COMPANDER0_CTL9 (RX_START_OFFSET + 0x0824) #define LPASS_CDC_RX_COMPANDER0_CTL9 (RX_START_OFFSET + 0x0824)
#define LPASS_CDC_RX_COMPANDER0_CTL10 (RX_START_OFFSET + 0x0828) #define LPASS_CDC_RX_COMPANDER0_CTL10 (RX_START_OFFSET + 0x0828)
@@ -465,128 +591,66 @@
#define LPASS_CDC_RX_COMPANDER1_CTL17 (RX_START_OFFSET + 0x08A4) #define LPASS_CDC_RX_COMPANDER1_CTL17 (RX_START_OFFSET + 0x08A4)
#define LPASS_CDC_RX_COMPANDER1_CTL18 (RX_START_OFFSET + 0x08A8) #define LPASS_CDC_RX_COMPANDER1_CTL18 (RX_START_OFFSET + 0x08A8)
#define LPASS_CDC_RX_COMPANDER1_CTL19 (RX_START_OFFSET + 0x08AC) #define LPASS_CDC_RX_COMPANDER1_CTL19 (RX_START_OFFSET + 0x08AC)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL \ #else
(RX_START_OFFSET + 0x0A00) #define LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1 (RX_START_OFFSET + 0x030C)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL \ #define LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2 (RX_START_OFFSET + 0x0310)
(RX_START_OFFSET + 0x0A04) #define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1 (RX_START_OFFSET + 0x0314)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL \ #define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2 (RX_START_OFFSET + 0x0318)
(RX_START_OFFSET + 0x0A08) #define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3 (RX_START_OFFSET + 0x031C)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL \ #define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4 (RX_START_OFFSET + 0x0320)
(RX_START_OFFSET + 0x0A0C) #define LPASS_CDC_RX_BCL_VBAT_DECODE_ST (RX_START_OFFSET + 0x0324)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL \ #define LPASS_CDC_RX_RX1_RX_PATH_CTL (RX_START_OFFSET + 0x0480)
(RX_START_OFFSET + 0x0A10) #define LPASS_CDC_RX_RX1_RX_PATH_CFG0 (RX_START_OFFSET + 0x0484)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL \ #define LPASS_CDC_RX_RX1_RX_PATH_CFG1 (RX_START_OFFSET + 0x0488)
(RX_START_OFFSET + 0x0A14) #define LPASS_CDC_RX_RX1_RX_PATH_CFG2 (RX_START_OFFSET + 0x048C)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL \ #define LPASS_CDC_RX_RX1_RX_PATH_CFG3 (RX_START_OFFSET + 0x0490)
(RX_START_OFFSET + 0x0A18) #define LPASS_CDC_RX_RX1_RX_VOL_CTL (RX_START_OFFSET + 0x0494)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL \ #define LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0498)
(RX_START_OFFSET + 0x0A1C) #define LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x049C)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL \ #define LPASS_CDC_RX_RX1_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x04A0)
(RX_START_OFFSET + 0x0A20) #define LPASS_CDC_RX_RX1_RX_PATH_SEC1 (RX_START_OFFSET + 0x04A4)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_CTL (RX_START_OFFSET + 0x0A24) #define LPASS_CDC_RX_RX1_RX_PATH_SEC2 (RX_START_OFFSET + 0x04A8)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL \ #define LPASS_CDC_RX_RX1_RX_PATH_SEC3 (RX_START_OFFSET + 0x04AC)
(RX_START_OFFSET + 0x0A28) #define LPASS_CDC_RX_RX1_RX_PATH_SEC4 (RX_START_OFFSET + 0x04B0)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL \ #define LPASS_CDC_RX_RX1_RX_PATH_SEC7 (RX_START_OFFSET + 0x04B4)
(RX_START_OFFSET + 0x0A2C) #define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x04B8)
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL \ #define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x04BC)
(RX_START_OFFSET + 0x0A30) #define LPASS_CDC_RX_RX1_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x04C0)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL \ #define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA1 (RX_START_OFFSET + 0x04C4)
(RX_START_OFFSET + 0x0A80) #define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA2 (RX_START_OFFSET + 0x04C8)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL \ #define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA3 (RX_START_OFFSET + 0x04CC)
(RX_START_OFFSET + 0x0A84) #define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x04D0)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL \ #define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x04D4)
(RX_START_OFFSET + 0x0A88) #define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x04D8)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL \ #define LPASS_CDC_RX_RX2_RX_PATH_CTL (RX_START_OFFSET + 0x0500)
(RX_START_OFFSET + 0x0A8C) #define LPASS_CDC_RX_RX2_RX_PATH_CFG0 (RX_START_OFFSET + 0x0504)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL \ #define LPASS_CDC_RX_RX2_RX_PATH_CFG1 (RX_START_OFFSET + 0x0508)
(RX_START_OFFSET + 0x0A90) #define LPASS_CDC_RX_RX2_RX_PATH_CFG2 (RX_START_OFFSET + 0x050C)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL \ #define LPASS_CDC_RX_RX2_RX_PATH_CFG3 (RX_START_OFFSET + 0x0510)
(RX_START_OFFSET + 0x0A94) #define LPASS_CDC_RX_RX2_RX_VOL_CTL (RX_START_OFFSET + 0x0514)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL \ #define LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0518)
(RX_START_OFFSET + 0x0A98) #define LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x051C)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL \ #define LPASS_CDC_RX_RX2_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x0520)
(RX_START_OFFSET + 0x0A9C) #define LPASS_CDC_RX_RX2_RX_PATH_SEC0 (RX_START_OFFSET + 0x0524)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL \ #define LPASS_CDC_RX_RX2_RX_PATH_SEC1 (RX_START_OFFSET + 0x0528)
(RX_START_OFFSET + 0x0AA0) #define LPASS_CDC_RX_RX2_RX_PATH_SEC2 (RX_START_OFFSET + 0x052C)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_CTL (RX_START_OFFSET + 0x0AA4) #define LPASS_CDC_RX_RX2_RX_PATH_SEC3 (RX_START_OFFSET + 0x0530)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL \ #define LPASS_CDC_RX_RX2_RX_PATH_SEC4 (RX_START_OFFSET + 0x0534)
(RX_START_OFFSET + 0x0AA8) #define LPASS_CDC_RX_RX2_RX_PATH_SEC5 (RX_START_OFFSET + 0x0538)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL \ #define LPASS_CDC_RX_RX2_RX_PATH_SEC6 (RX_START_OFFSET + 0x053C)
(RX_START_OFFSET + 0x0AAC) #define LPASS_CDC_RX_RX2_RX_PATH_SEC7 (RX_START_OFFSET + 0x0540)
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL \ #define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x0544)
(RX_START_OFFSET + 0x0AB0) #define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x0548)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0 (RX_START_OFFSET + 0x0B00) #define LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x054C)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1 (RX_START_OFFSET + 0x0B04) #define LPASS_CDC_RX_COMPANDER1_CTL0 (RX_START_OFFSET + 0x0840)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2 (RX_START_OFFSET + 0x0B08) #define LPASS_CDC_RX_COMPANDER1_CTL1 (RX_START_OFFSET + 0x0844)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3 (RX_START_OFFSET + 0x0B0C) #define LPASS_CDC_RX_COMPANDER1_CTL2 (RX_START_OFFSET + 0x0848)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0 (RX_START_OFFSET + 0x0B10) #define LPASS_CDC_RX_COMPANDER1_CTL3 (RX_START_OFFSET + 0x084C)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1 (RX_START_OFFSET + 0x0B14) #define LPASS_CDC_RX_COMPANDER1_CTL4 (RX_START_OFFSET + 0x0850)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2 (RX_START_OFFSET + 0x0B18) #define LPASS_CDC_RX_COMPANDER1_CTL5 (RX_START_OFFSET + 0x0854)
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3 (RX_START_OFFSET + 0x0B1C) #define LPASS_CDC_RX_COMPANDER1_CTL6 (RX_START_OFFSET + 0x0858)
#define LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL \ #define LPASS_CDC_RX_COMPANDER1_CTL7 (RX_START_OFFSET + 0x085C)
(RX_START_OFFSET + 0x0B40) #endif
#define LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 \
(RX_START_OFFSET + 0x0B44)
#define LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL \
(RX_START_OFFSET + 0x0B50)
#define LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 \
(RX_START_OFFSET + 0x0B54)
#define LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL \
(RX_START_OFFSET + 0x0C00)
#define LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C04)
#define LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL \
(RX_START_OFFSET + 0x0C40)
#define LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C44)
#define LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL \
(RX_START_OFFSET + 0x0C80)
#define LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C84)
#define LPASS_CDC_RX_EC_ASRC0_CLK_RST_CTL (RX_START_OFFSET + 0x0D00)
#define LPASS_CDC_RX_EC_ASRC0_CTL0 (RX_START_OFFSET + 0x0D04)
#define LPASS_CDC_RX_EC_ASRC0_CTL1 (RX_START_OFFSET + 0x0D08)
#define LPASS_CDC_RX_EC_ASRC0_FIFO_CTL (RX_START_OFFSET + 0x0D0C)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB \
(RX_START_OFFSET + 0x0D10)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB \
(RX_START_OFFSET + 0x0D14)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB \
(RX_START_OFFSET + 0x0D18)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB \
(RX_START_OFFSET + 0x0D1C)
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FIFO (RX_START_OFFSET + 0x0D20)
#define LPASS_CDC_RX_EC_ASRC1_CLK_RST_CTL (RX_START_OFFSET + 0x0D40)
#define LPASS_CDC_RX_EC_ASRC1_CTL0 (RX_START_OFFSET + 0x0D44)
#define LPASS_CDC_RX_EC_ASRC1_CTL1 (RX_START_OFFSET + 0x0D48)
#define LPASS_CDC_RX_EC_ASRC1_FIFO_CTL (RX_START_OFFSET + 0x0D4C)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB \
(RX_START_OFFSET + 0x0D50)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB \
(RX_START_OFFSET + 0x0D54)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB \
(RX_START_OFFSET + 0x0D58)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB \
(RX_START_OFFSET + 0x0D5C)
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FIFO (RX_START_OFFSET + 0x0D60)
#define LPASS_CDC_RX_EC_ASRC2_CLK_RST_CTL (RX_START_OFFSET + 0x0D80)
#define LPASS_CDC_RX_EC_ASRC2_CTL0 (RX_START_OFFSET + 0x0D84)
#define LPASS_CDC_RX_EC_ASRC2_CTL1 (RX_START_OFFSET + 0x0D88)
#define LPASS_CDC_RX_EC_ASRC2_FIFO_CTL (RX_START_OFFSET + 0x0D8C)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB \
(RX_START_OFFSET + 0x0D90)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB \
(RX_START_OFFSET + 0x0D94)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB \
(RX_START_OFFSET + 0x0D98)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB \
(RX_START_OFFSET + 0x0D9C)
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FIFO (RX_START_OFFSET + 0x0DA0)
#define LPASS_CDC_RX_DSD0_PATH_CTL (RX_START_OFFSET + 0x0F00)
#define LPASS_CDC_RX_DSD0_CFG0 (RX_START_OFFSET + 0x0F04)
#define LPASS_CDC_RX_DSD0_CFG1 (RX_START_OFFSET + 0x0F08)
#define LPASS_CDC_RX_DSD0_CFG2 (RX_START_OFFSET + 0x0F0C)
#define LPASS_CDC_RX_DSD1_PATH_CTL (RX_START_OFFSET + 0x0F80)
#define LPASS_CDC_RX_DSD1_CFG0 (RX_START_OFFSET + 0x0F84)
#define LPASS_CDC_RX_DSD1_CFG1 (RX_START_OFFSET + 0x0F88)
#define LPASS_CDC_RX_DSD1_CFG2 (RX_START_OFFSET + 0x0F8C)
#define RX_MAX_OFFSET (RX_START_OFFSET + 0x0F8C) #define RX_MAX_OFFSET (RX_START_OFFSET + 0x0F8C)
#define LPASS_CDC_RX_MACRO_MAX 0x3E4 /* F8C/4 = 3E3 + 1 */ #define LPASS_CDC_RX_MACRO_MAX 0x3E4 /* F8C/4 = 3E3 + 1 */

257
asoc/codecs/lpass-cdc/lpass-cdc-regmap.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. /* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#include <linux/regmap.h> #include <linux/regmap.h>
@@ -14,18 +14,13 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00}, { LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_TOP_CFG0, 0x00}, { LPASS_CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
{ LPASS_CDC_TX_TOP_CSR_ANC_CFG, 0x00}, { LPASS_CDC_TX_TOP_CSR_ANC_CFG, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x60}, { LPASS_CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
{ LPASS_CDC_TX_TOP_CSR_DEBUG_BUS, 0x00}, { LPASS_CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
{ LPASS_CDC_TX_TOP_CSR_DEBUG_EN, 0x00}, { LPASS_CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
{ LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C}, { LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C},
{ LPASS_CDC_TX_TOP_CSR_I2S_CLK, 0x00}, { LPASS_CDC_TX_TOP_CSR_I2S_CLK, 0x00},
{ LPASS_CDC_TX_TOP_CSR_I2S_RESET, 0x00}, { LPASS_CDC_TX_TOP_CSR_I2S_RESET, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL, 0x0E},
{ LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00}, { LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
{ LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00}, { LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
{ LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00}, { LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
@@ -147,6 +142,23 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_TX7_TX_PATH_SEC4, 0x20}, { LPASS_CDC_TX7_TX_PATH_SEC4, 0x20},
{ LPASS_CDC_TX7_TX_PATH_SEC5, 0x00}, { LPASS_CDC_TX7_TX_PATH_SEC5, 0x00},
{ LPASS_CDC_TX7_TX_PATH_SEC6, 0x00}, { LPASS_CDC_TX7_TX_PATH_SEC6, 0x00},
#ifdef CONFIG_BOLERO_VER_2P6
{ LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x60},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL, 0x0E},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL, 0x0E},
#else
{ LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL, 0x00},
{ LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL, 0x00},
#endif
/* RX Macro */ /* RX Macro */
{ LPASS_CDC_RX_TOP_TOP_CFG0, 0x00}, { LPASS_CDC_RX_TOP_TOP_CFG0, 0x00},
@@ -170,11 +182,9 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11}, { LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11},
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20}, { LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20},
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00}, { LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00},
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x08},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11}, { LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20}, { LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00}, { LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x08},
{ LPASS_CDC_RX_TOP_RX_I2S_CTL, 0x0C}, { LPASS_CDC_RX_TOP_RX_I2S_CTL, 0x0C},
{ LPASS_CDC_RX_TOP_TX_I2S2_CTL, 0x0C}, { LPASS_CDC_RX_TOP_TX_I2S2_CTL, 0x0C},
{ LPASS_CDC_RX_TOP_I2S_CLK, 0x0C}, { LPASS_CDC_RX_TOP_I2S_CLK, 0x0C},
@@ -266,7 +276,6 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_RX0_RX_PATH_CFG0, 0x00}, { LPASS_CDC_RX_RX0_RX_PATH_CFG0, 0x00},
{ LPASS_CDC_RX_RX0_RX_PATH_CFG1, 0x64}, { LPASS_CDC_RX_RX0_RX_PATH_CFG1, 0x64},
{ LPASS_CDC_RX_RX0_RX_PATH_CFG2, 0x8F}, { LPASS_CDC_RX_RX0_RX_PATH_CFG2, 0x8F},
{ LPASS_CDC_RX_RX0_RX_PATH_CFG3, 0x03},
{ LPASS_CDC_RX_RX0_RX_VOL_CTL, 0x00}, { LPASS_CDC_RX_RX0_RX_VOL_CTL, 0x00},
{ LPASS_CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04}, { LPASS_CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04},
{ LPASS_CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E}, { LPASS_CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E},
@@ -285,22 +294,10 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55}, { LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55},
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55}, { LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55},
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55}, { LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55},
{ LPASS_CDC_RX_RX0_RX_FIR_CTL, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_CFG, 0x64},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7, 0x00},
{ LPASS_CDC_RX_RX1_RX_PATH_CTL, 0x04}, { LPASS_CDC_RX_RX1_RX_PATH_CTL, 0x04},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG0, 0x00}, { LPASS_CDC_RX_RX1_RX_PATH_CFG0, 0x00},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG1, 0x64}, { LPASS_CDC_RX_RX1_RX_PATH_CFG1, 0x64},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG2, 0x8F}, { LPASS_CDC_RX_RX1_RX_PATH_CFG2, 0x8F},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG3, 0x03},
{ LPASS_CDC_RX_RX1_RX_VOL_CTL, 0x00}, { LPASS_CDC_RX_RX1_RX_VOL_CTL, 0x00},
{ LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04}, { LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04},
{ LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E}, { LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E},
@@ -319,22 +316,10 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55}, { LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55},
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55}, { LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55},
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55}, { LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55},
{ LPASS_CDC_RX_RX1_RX_FIR_CTL, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_CFG, 0x64},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_CTL, 0x04}, { LPASS_CDC_RX_RX2_RX_PATH_CTL, 0x04},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG0, 0x00}, { LPASS_CDC_RX_RX2_RX_PATH_CFG0, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG1, 0x64}, { LPASS_CDC_RX_RX2_RX_PATH_CFG1, 0x64},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG2, 0x8F}, { LPASS_CDC_RX_RX2_RX_PATH_CFG2, 0x8F},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x03},
{ LPASS_CDC_RX_RX2_RX_VOL_CTL, 0x00}, { LPASS_CDC_RX_RX2_RX_VOL_CTL, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04}, { LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04},
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E}, { LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E},
@@ -350,61 +335,6 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08}, { LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08},
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00}, { LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00}, { LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1, 0x85},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2, 0xDC},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3, 0x85},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4, 0xDC},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5, 0x85},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6, 0xDC},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7, 0x32},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG, 0x10},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3, 0x04},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1, 0xE0},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3, 0x40},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1, 0x2A},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2, 0x18},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3, 0x18},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4, 0x03},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4, 0x64},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN, 0x0C},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2, 0x77},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5, 0x4B},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1, 0x04},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2, 0x08},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3, 0x0C},
{ LPASS_CDC_RX_IDLE_DETECT_PATH_CTL, 0x00}, { LPASS_CDC_RX_IDLE_DETECT_PATH_CTL, 0x00},
{ LPASS_CDC_RX_IDLE_DETECT_CFG0, 0x07}, { LPASS_CDC_RX_IDLE_DETECT_CFG0, 0x07},
{ LPASS_CDC_RX_IDLE_DETECT_CFG1, 0x3C}, { LPASS_CDC_RX_IDLE_DETECT_CFG1, 0x3C},
@@ -418,18 +348,6 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_COMPANDER0_CTL5, 0x00}, { LPASS_CDC_RX_COMPANDER0_CTL5, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL6, 0x01}, { LPASS_CDC_RX_COMPANDER0_CTL6, 0x01},
{ LPASS_CDC_RX_COMPANDER0_CTL7, 0x28}, { LPASS_CDC_RX_COMPANDER0_CTL7, 0x28},
{ LPASS_CDC_RX_COMPANDER0_CTL8, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL9, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL10, 0x06},
{ LPASS_CDC_RX_COMPANDER0_CTL11, 0x12},
{ LPASS_CDC_RX_COMPANDER0_CTL12, 0x1E},
{ LPASS_CDC_RX_COMPANDER0_CTL13, 0x2A},
{ LPASS_CDC_RX_COMPANDER0_CTL14, 0x36},
{ LPASS_CDC_RX_COMPANDER0_CTL15, 0x3C},
{ LPASS_CDC_RX_COMPANDER0_CTL16, 0xC4},
{ LPASS_CDC_RX_COMPANDER0_CTL17, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL18, 0x0C},
{ LPASS_CDC_RX_COMPANDER0_CTL19, 0x16},
{ LPASS_CDC_RX_COMPANDER1_CTL0, 0x60}, { LPASS_CDC_RX_COMPANDER1_CTL0, 0x60},
{ LPASS_CDC_RX_COMPANDER1_CTL1, 0xDB}, { LPASS_CDC_RX_COMPANDER1_CTL1, 0xDB},
{ LPASS_CDC_RX_COMPANDER1_CTL2, 0xFF}, { LPASS_CDC_RX_COMPANDER1_CTL2, 0xFF},
@@ -438,18 +356,6 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_COMPANDER1_CTL5, 0x00}, { LPASS_CDC_RX_COMPANDER1_CTL5, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL6, 0x01}, { LPASS_CDC_RX_COMPANDER1_CTL6, 0x01},
{ LPASS_CDC_RX_COMPANDER1_CTL7, 0x28}, { LPASS_CDC_RX_COMPANDER1_CTL7, 0x28},
{ LPASS_CDC_RX_COMPANDER1_CTL8, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL9, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL10, 0x06},
{ LPASS_CDC_RX_COMPANDER1_CTL11, 0x12},
{ LPASS_CDC_RX_COMPANDER1_CTL12, 0x1E},
{ LPASS_CDC_RX_COMPANDER1_CTL13, 0x2A},
{ LPASS_CDC_RX_COMPANDER1_CTL14, 0x36},
{ LPASS_CDC_RX_COMPANDER1_CTL15, 0x3C},
{ LPASS_CDC_RX_COMPANDER1_CTL16, 0xC4},
{ LPASS_CDC_RX_COMPANDER1_CTL17, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL18, 0x0C},
{ LPASS_CDC_RX_COMPANDER1_CTL19, 0x16},
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00}, { LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00},
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00}, { LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00},
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00}, { LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00},
@@ -529,6 +435,127 @@ static const struct reg_default lpass_cdc_defaults[] = {
{ LPASS_CDC_RX_DSD1_CFG0, 0x00}, { LPASS_CDC_RX_DSD1_CFG0, 0x00},
{ LPASS_CDC_RX_DSD1_CFG1, 0x62}, { LPASS_CDC_RX_DSD1_CFG1, 0x62},
{ LPASS_CDC_RX_DSD1_CFG2, 0x96}, { LPASS_CDC_RX_DSD1_CFG2, 0x96},
#ifdef CONFIG_BOLERO_VER_2P6
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x08},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x08},
{ LPASS_CDC_RX_RX0_RX_PATH_CFG3, 0x03},
{ LPASS_CDC_RX_RX0_RX_FIR_CTL, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_CFG, 0x64},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6, 0x00},
{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7, 0x00},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG3, 0x03},
{ LPASS_CDC_RX_RX1_RX_FIR_CTL, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_CFG, 0x64},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6, 0x00},
{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x03},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1, 0x85},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2, 0xDC},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3, 0x85},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4, 0xDC},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5, 0x85},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6, 0xDC},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7, 0x32},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4, 0x00},
{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG, 0x10},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3, 0x04},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1, 0xE0},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3, 0x40},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1, 0x2A},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2, 0x18},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3, 0x18},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4, 0x03},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4, 0x64},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN, 0x0C},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2, 0x77},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5, 0x4B},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7, 0x01},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9, 0x00},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1, 0x04},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2, 0x08},
{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3, 0x0C},
{ LPASS_CDC_RX_COMPANDER0_CTL8, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL9, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL10, 0x06},
{ LPASS_CDC_RX_COMPANDER0_CTL11, 0x12},
{ LPASS_CDC_RX_COMPANDER0_CTL12, 0x1E},
{ LPASS_CDC_RX_COMPANDER0_CTL13, 0x2A},
{ LPASS_CDC_RX_COMPANDER0_CTL14, 0x36},
{ LPASS_CDC_RX_COMPANDER0_CTL15, 0x3C},
{ LPASS_CDC_RX_COMPANDER0_CTL16, 0xC4},
{ LPASS_CDC_RX_COMPANDER0_CTL17, 0x00},
{ LPASS_CDC_RX_COMPANDER0_CTL18, 0x0C},
{ LPASS_CDC_RX_COMPANDER0_CTL19, 0x16},
{ LPASS_CDC_RX_COMPANDER1_CTL8, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL9, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL10, 0x06},
{ LPASS_CDC_RX_COMPANDER1_CTL11, 0x12},
{ LPASS_CDC_RX_COMPANDER1_CTL12, 0x1E},
{ LPASS_CDC_RX_COMPANDER1_CTL13, 0x2A},
{ LPASS_CDC_RX_COMPANDER1_CTL14, 0x36},
{ LPASS_CDC_RX_COMPANDER1_CTL15, 0x3C},
{ LPASS_CDC_RX_COMPANDER1_CTL16, 0xC4},
{ LPASS_CDC_RX_COMPANDER1_CTL17, 0x00},
{ LPASS_CDC_RX_COMPANDER1_CTL18, 0x0C},
{ LPASS_CDC_RX_COMPANDER1_CTL19, 0x16},
#else
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00},
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00},
{ LPASS_CDC_RX_BCL_VBAT_DECODE_ST, 0x00},
{ LPASS_CDC_RX_RX0_RX_PATH_CFG3, 0x00},
{ LPASS_CDC_RX_RX1_RX_PATH_CFG3, 0x00},
{ LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x00},
#endif
/* WSA Macro */ /* WSA Macro */
{ LPASS_CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, { LPASS_CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
@@ -1331,6 +1358,7 @@ static bool lpass_cdc_is_volatile_register(struct device *dev,
case LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL: case LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL:
case LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL: case LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL:
case LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL: case LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL:
#ifdef CONFIG_BOLERO_VER_2P6
case LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR: case LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR:
case LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0: case LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0:
case LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1: case LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1:
@@ -1353,6 +1381,7 @@ static bool lpass_cdc_is_volatile_register(struct device *dev,
case LPASS_CDC_RX_RX1_RX_FIR_CTL: case LPASS_CDC_RX_RX1_RX_FIR_CTL:
case LPASS_CDC_RX_RX0_RX_PATH_CTL: case LPASS_CDC_RX_RX0_RX_PATH_CTL:
case LPASS_CDC_RX_RX1_RX_PATH_CTL: case LPASS_CDC_RX_RX1_RX_PATH_CTL:
#endif
return true; return true;
} }
return false; return false;

131
asoc/codecs/lpass-cdc/lpass-cdc-rx-macro.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. /* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#include <linux/module.h> #include <linux/module.h>
@@ -55,13 +55,14 @@
#define LPASS_CDC_RX_MACRO_INTERP_MUX_NUM_INPUTS 3 #define LPASS_CDC_RX_MACRO_INTERP_MUX_NUM_INPUTS 3
#define LPASS_CDC_RX_MACRO_SIDETONE_IIR_COEFF_MAX 5 #define LPASS_CDC_RX_MACRO_SIDETONE_IIR_COEFF_MAX 5
#ifdef CONFIG_BOLERO_VER_2P6
#define LPASS_CDC_RX_MACRO_FIR_COEFF_MAX 100 #define LPASS_CDC_RX_MACRO_FIR_COEFF_MAX 100
#define LPASS_CDC_RX_MACRO_FIR_COEFF_ARRAY_MAX \ #define LPASS_CDC_RX_MACRO_FIR_COEFF_ARRAY_MAX \
(LPASS_CDC_RX_MACRO_FIR_COEFF_MAX + 1) (LPASS_CDC_RX_MACRO_FIR_COEFF_MAX + 1)
/* first value represent number of coefficients in each 100 integer group */ /* first value represent number of coefficients in each 100 integer group */
#define LPASS_CDC_RX_MACRO_FIR_FILTER_BYTES \ #define LPASS_CDC_RX_MACRO_FIR_FILTER_BYTES \
(sizeof(u32) * LPASS_CDC_RX_MACRO_FIR_COEFF_ARRAY_MAX) (sizeof(u32) * LPASS_CDC_RX_MACRO_FIR_COEFF_ARRAY_MAX)
#endif
#define STRING(name) #name #define STRING(name) #name
#define LPASS_CDC_RX_MACRO_DAPM_ENUM(name, reg, offset, text) \ #define LPASS_CDC_RX_MACRO_DAPM_ENUM(name, reg, offset, text) \
@@ -184,12 +185,14 @@ enum {
RX_MODE_MAX RX_MODE_MAX
}; };
#ifdef CONFIG_BOLERO_VER_2P6
static struct lpass_cdc_comp_setting comp_setting_table[RX_MODE_MAX] = static struct lpass_cdc_comp_setting comp_setting_table[RX_MODE_MAX] =
{ {
{12, -60, 12}, {12, -60, 12},
{0, -60, 12}, {0, -60, 12},
{12, -36, 12}, {12, -36, 12},
}; };
#endif
struct lpass_cdc_rx_macro_reg_mask_val { struct lpass_cdc_rx_macro_reg_mask_val {
u16 reg; u16 reg;
@@ -368,6 +371,7 @@ struct lpass_cdc_rx_macro_iir_filter_ctl {
} \ } \
} }
#ifdef CONFIG_BOLERO_VER_2P6
/* Codec supports 2 FIR filters Path */ /* Codec supports 2 FIR filters Path */
enum { enum {
RX0_PATH = 0, RX0_PATH = 0,
@@ -399,6 +403,7 @@ struct lpass_cdc_rx_macro_fir_filter_ctl {
.bytes_ext = {.max = LPASS_CDC_RX_MACRO_FIR_FILTER_BYTES, }, \ .bytes_ext = {.max = LPASS_CDC_RX_MACRO_FIR_FILTER_BYTES, }, \
} \ } \
} }
#endif
struct lpass_cdc_rx_macro_idle_detect_config { struct lpass_cdc_rx_macro_idle_detect_config {
u8 hph_idle_thr; u8 hph_idle_thr;
@@ -416,6 +421,12 @@ static struct interp_sample_rate sr_val_tbl[] = {
{176400, 0xB}, {352800, 0xC}, {176400, 0xB}, {352800, 0xC},
}; };
struct lpass_cdc_rx_macro_bcl_pmic_params {
u8 id;
u8 sid;
u8 ppid;
};
static int lpass_cdc_rx_macro_core_vote(void *handle, bool enable); static int lpass_cdc_rx_macro_core_vote(void *handle, bool enable);
static int lpass_cdc_rx_macro_hw_params(struct snd_pcm_substream *substream, static int lpass_cdc_rx_macro_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_pcm_hw_params *params,
@@ -496,11 +507,16 @@ struct lpass_cdc_rx_macro_priv {
bool reset_swr; bool reset_swr;
int clsh_users; int clsh_users;
int rx_mclk_cnt; int rx_mclk_cnt;
#ifdef CONFIG_BOLERO_VER_2P6
u8 fir_total_coeff_num[FIR_PATH_MAX]; u8 fir_total_coeff_num[FIR_PATH_MAX];
bool is_fir_coeff_written[FIR_PATH_MAX][GRP_MAX];
u32 fir_coeff_array[FIR_PATH_MAX][GRP_MAX]
[LPASS_CDC_RX_MACRO_FIR_COEFF_MAX];
u32 num_fir_coeff[FIR_PATH_MAX][GRP_MAX];
#endif
bool is_native_on; bool is_native_on;
bool is_ear_mode_on; bool is_ear_mode_on;
bool is_fir_filter_on; bool is_fir_filter_on;
bool is_fir_coeff_written[FIR_PATH_MAX][GRP_MAX];
bool is_fir_capable; bool is_fir_capable;
bool dev_up; bool dev_up;
bool pre_dev_up; bool pre_dev_up;
@@ -522,15 +538,13 @@ struct lpass_cdc_rx_macro_priv {
u8 sidetone_coeff_array[IIR_MAX][BAND_MAX] u8 sidetone_coeff_array[IIR_MAX][BAND_MAX]
[LPASS_CDC_RX_MACRO_SIDETONE_IIR_COEFF_MAX * 4]; [LPASS_CDC_RX_MACRO_SIDETONE_IIR_COEFF_MAX * 4];
/* NOT designed to always reflect the actual hardware value */ /* NOT designed to always reflect the actual hardware value */
u32 fir_coeff_array[FIR_PATH_MAX][GRP_MAX]
[LPASS_CDC_RX_MACRO_FIR_COEFF_MAX];
u32 num_fir_coeff[FIR_PATH_MAX][GRP_MAX];
struct platform_device *pdev_child_devices struct platform_device *pdev_child_devices
[LPASS_CDC_RX_MACRO_CHILD_DEVICES_MAX]; [LPASS_CDC_RX_MACRO_CHILD_DEVICES_MAX];
int child_count; int child_count;
int is_softclip_on; int is_softclip_on;
int is_aux_hpf_on; int is_aux_hpf_on;
int softclip_clk_users; int softclip_clk_users;
struct lpass_cdc_rx_macro_bcl_pmic_params bcl_pmic_params;
u16 clk_id; u16 clk_id;
u16 default_clk_id; u16 default_clk_id;
struct clk *hifi_fir_clk; struct clk *hifi_fir_clk;
@@ -608,9 +622,11 @@ static const char * const lpass_cdc_rx_macro_vbat_bcl_gsm_mode_text[] = {"OFF",
static const struct soc_enum lpass_cdc_rx_macro_vbat_bcl_gsm_mode_enum = static const struct soc_enum lpass_cdc_rx_macro_vbat_bcl_gsm_mode_enum =
SOC_ENUM_SINGLE_EXT(2, lpass_cdc_rx_macro_vbat_bcl_gsm_mode_text); SOC_ENUM_SINGLE_EXT(2, lpass_cdc_rx_macro_vbat_bcl_gsm_mode_text);
#ifdef CONFIG_BOLERO_VER_2P6
static const char *const lpass_cdc_rx_macro_fir_filter_text[] = {"OFF", "ON"}; static const char *const lpass_cdc_rx_macro_fir_filter_text[] = {"OFF", "ON"};
static const struct soc_enum lpass_cdc_rx_macro_fir_filter_enum = static const struct soc_enum lpass_cdc_rx_macro_fir_filter_enum =
SOC_ENUM_SINGLE_EXT(2, lpass_cdc_rx_macro_fir_filter_text); SOC_ENUM_SINGLE_EXT(2, lpass_cdc_rx_macro_fir_filter_text);
#endif
static const struct snd_kcontrol_new rx_int2_1_vbat_mix_switch[] = { static const struct snd_kcontrol_new rx_int2_1_vbat_mix_switch[] = {
SOC_DAPM_SINGLE("RX AUX VBAT Enable", SND_SOC_NOPM, 0, 1, 0) SOC_DAPM_SINGLE("RX AUX VBAT Enable", SND_SOC_NOPM, 0, 1, 0)
@@ -1862,9 +1878,12 @@ static int lpass_cdc_rx_macro_config_compander(struct snd_soc_component *compone
int interp_n, int event) int interp_n, int event)
{ {
int comp = 0; int comp = 0;
u16 comp_ctl0_reg = 0, comp_ctl8_reg = 0, rx_path_cfg0_reg = 0; u16 comp_ctl0_reg = 0, rx_path_cfg0_reg = 0;
u16 comp_coeff_lsb_reg = 0, comp_coeff_msb_reg = 0; u16 comp_coeff_lsb_reg = 0, comp_coeff_msb_reg = 0;
u16 mode = rx_priv->hph_pwr_mode; u16 mode = rx_priv->hph_pwr_mode;
#ifdef CONFIG_BOLERO_VER_2P6
u16 comp_ctl8_reg = 0;
#endif
/* AUX does not have compander */ /* AUX does not have compander */
if (interp_n == INTERP_AUX) if (interp_n == INTERP_AUX)
@@ -1889,8 +1908,10 @@ static int lpass_cdc_rx_macro_config_compander(struct snd_soc_component *compone
} }
comp_ctl0_reg = LPASS_CDC_RX_COMPANDER0_CTL0 + comp_ctl0_reg = LPASS_CDC_RX_COMPANDER0_CTL0 +
(comp * LPASS_CDC_RX_MACRO_COMP_OFFSET); (comp * LPASS_CDC_RX_MACRO_COMP_OFFSET);
#ifdef CONFIG_BOLERO_VER_2P6
comp_ctl8_reg = LPASS_CDC_RX_COMPANDER0_CTL8 + comp_ctl8_reg = LPASS_CDC_RX_COMPANDER0_CTL8 +
(comp * LPASS_CDC_RX_MACRO_COMP_OFFSET); (comp * LPASS_CDC_RX_MACRO_COMP_OFFSET);
#endif
rx_path_cfg0_reg = LPASS_CDC_RX_RX0_RX_PATH_CFG0 + rx_path_cfg0_reg = LPASS_CDC_RX_RX0_RX_PATH_CFG0 +
(comp * LPASS_CDC_RX_MACRO_RX_PATH_OFFSET); (comp * LPASS_CDC_RX_MACRO_RX_PATH_OFFSET);
if (SND_SOC_DAPM_EVENT_ON(event)) { if (SND_SOC_DAPM_EVENT_ON(event)) {
@@ -1898,11 +1919,11 @@ static int lpass_cdc_rx_macro_config_compander(struct snd_soc_component *compone
comp_coeff_lsb_reg, comp_coeff_msb_reg, comp_coeff_lsb_reg, comp_coeff_msb_reg,
comp_coeff_table[rx_priv->hph_pwr_mode], comp_coeff_table[rx_priv->hph_pwr_mode],
COMP_MAX_COEFF); COMP_MAX_COEFF);
#ifdef CONFIG_BOLERO_VER_2P6
lpass_cdc_update_compander_setting(component, lpass_cdc_update_compander_setting(component,
comp_ctl8_reg, comp_ctl8_reg,
&comp_setting_table[mode]); &comp_setting_table[mode]);
#endif
/* Enable Compander Clock */ /* Enable Compander Clock */
snd_soc_component_update_bits(component, comp_ctl0_reg, snd_soc_component_update_bits(component, comp_ctl0_reg,
0x01, 0x01); 0x01, 0x01);
@@ -2157,6 +2178,7 @@ static int lpass_cdc_rx_macro_hph_idle_detect_put(struct snd_kcontrol *kcontrol,
return 0; return 0;
} }
#ifdef CONFIG_BOLERO_VER_2P6
static int lpass_cdc_rx_macro_get_pcm_path(struct snd_kcontrol *kcontrol, static int lpass_cdc_rx_macro_get_pcm_path(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol) struct snd_ctl_elem_value *ucontrol)
{ {
@@ -2186,6 +2208,7 @@ static int lpass_cdc_rx_macro_put_pcm_path(struct snd_kcontrol *kcontrol,
rx_priv->is_pcm_enabled = ucontrol->value.integer.value[0]; rx_priv->is_pcm_enabled = ucontrol->value.integer.value[0];
return 0; return 0;
} }
#endif
static int lpass_cdc_rx_macro_get_compander(struct snd_kcontrol *kcontrol, static int lpass_cdc_rx_macro_get_compander(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol) struct snd_ctl_elem_value *ucontrol)
@@ -2578,6 +2601,7 @@ static int lpass_cdc_rx_macro_enable_vbat(struct snd_soc_dapm_widget *w,
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD9,
0xFF, 0x00); 0xFF, 0x00);
#ifdef CONFIG_BOLERO_VER_2P6
/* Enable CB decode block clock */ /* Enable CB decode block clock */
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1, 0x01, 0x01); LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1, 0x01, 0x01);
@@ -2587,15 +2611,18 @@ static int lpass_cdc_rx_macro_enable_vbat(struct snd_soc_dapm_widget *w,
/* Request for BCL data */ /* Request for BCL data */
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3, 0x01, 0x01); LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3, 0x01, 0x01);
#endif
break; break;
case SND_SOC_DAPM_POST_PMD: case SND_SOC_DAPM_POST_PMD:
#ifdef CONFIG_BOLERO_VER_2P6
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3, 0x01, 0x00); LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3, 0x01, 0x00);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2, 0x01, 0x00); LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2, 0x01, 0x00);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1, 0x01, 0x00); LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1, 0x01, 0x00);
#endif
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
LPASS_CDC_RX_RX2_RX_PATH_CFG1, LPASS_CDC_RX_RX2_RX_PATH_CFG1,
0x80, 0x00); 0x80, 0x00);
@@ -3039,6 +3066,7 @@ static int lpass_cdc_rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol,
return 0; return 0;
} }
static int lpass_cdc_rx_macro_iir_band_audio_mixer_get(struct snd_kcontrol *kcontrol, static int lpass_cdc_rx_macro_iir_band_audio_mixer_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol) struct snd_ctl_elem_value *ucontrol)
{ {
@@ -3210,6 +3238,7 @@ static int lpass_cdc_rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w,
return 0; return 0;
} }
#ifdef CONFIG_BOLERO_VER_2P6
static int lpass_cdc_rx_macro_fir_filter_enable_get(struct snd_kcontrol *kcontrol, static int lpass_cdc_rx_macro_fir_filter_enable_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol) struct snd_ctl_elem_value *ucontrol)
{ {
@@ -3709,6 +3738,7 @@ static int lpass_cdc_rx_macro_fir_coeff_num_put(struct snd_kcontrol *kcontrol,
return ret; return ret;
} }
#endif
static const struct snd_kcontrol_new lpass_cdc_rx_macro_snd_controls[] = { static const struct snd_kcontrol_new lpass_cdc_rx_macro_snd_controls[] = {
SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume",
@@ -3735,6 +3765,7 @@ static const struct snd_kcontrol_new lpass_cdc_rx_macro_snd_controls[] = {
SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, LPASS_CDC_RX_MACRO_COMP2, 1, 0, SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, LPASS_CDC_RX_MACRO_COMP2, 1, 0,
lpass_cdc_rx_macro_get_compander, lpass_cdc_rx_macro_set_compander), lpass_cdc_rx_macro_get_compander, lpass_cdc_rx_macro_set_compander),
#ifdef CONFIG_BOLERO_VER_2P6
SOC_SINGLE_EXT("RX_HPH PCM", SND_SOC_NOPM, 0, 1, 0, SOC_SINGLE_EXT("RX_HPH PCM", SND_SOC_NOPM, 0, 1, 0,
lpass_cdc_rx_macro_get_pcm_path, lpass_cdc_rx_macro_put_pcm_path), lpass_cdc_rx_macro_get_pcm_path, lpass_cdc_rx_macro_put_pcm_path),
@@ -3745,6 +3776,9 @@ static const struct snd_kcontrol_new lpass_cdc_rx_macro_snd_controls[] = {
SOC_SINGLE_EXT("RX1 FIR Coeff Num", SND_SOC_NOPM, RX1_PATH, SOC_SINGLE_EXT("RX1 FIR Coeff Num", SND_SOC_NOPM, RX1_PATH,
(LPASS_CDC_RX_MACRO_FIR_COEFF_MAX * GRP_MAX), 0, (LPASS_CDC_RX_MACRO_FIR_COEFF_MAX * GRP_MAX), 0,
lpass_cdc_rx_macro_fir_coeff_num_get, lpass_cdc_rx_macro_fir_coeff_num_put), lpass_cdc_rx_macro_fir_coeff_num_get, lpass_cdc_rx_macro_fir_coeff_num_put),
SOC_ENUM_EXT("RX_FIR Filter", lpass_cdc_rx_macro_fir_filter_enum,
lpass_cdc_rx_macro_fir_filter_enable_get, lpass_cdc_rx_macro_fir_filter_enable_put),
#endif
SOC_ENUM_EXT("HPH Idle Detect", hph_idle_detect_enum, SOC_ENUM_EXT("HPH Idle Detect", hph_idle_detect_enum,
lpass_cdc_rx_macro_hph_idle_detect_get, lpass_cdc_rx_macro_hph_idle_detect_put), lpass_cdc_rx_macro_hph_idle_detect_get, lpass_cdc_rx_macro_hph_idle_detect_put),
@@ -3752,8 +3786,6 @@ static const struct snd_kcontrol_new lpass_cdc_rx_macro_snd_controls[] = {
SOC_ENUM_EXT("RX_EAR Mode", lpass_cdc_rx_macro_ear_mode_enum, SOC_ENUM_EXT("RX_EAR Mode", lpass_cdc_rx_macro_ear_mode_enum,
lpass_cdc_rx_macro_get_ear_mode, lpass_cdc_rx_macro_put_ear_mode), lpass_cdc_rx_macro_get_ear_mode, lpass_cdc_rx_macro_put_ear_mode),
SOC_ENUM_EXT("RX_FIR Filter", lpass_cdc_rx_macro_fir_filter_enum,
lpass_cdc_rx_macro_fir_filter_enable_get, lpass_cdc_rx_macro_fir_filter_enable_put),
SOC_ENUM_EXT("RX_HPH HD2 Mode", lpass_cdc_rx_macro_hph_hd2_mode_enum, SOC_ENUM_EXT("RX_HPH HD2 Mode", lpass_cdc_rx_macro_hph_hd2_mode_enum,
lpass_cdc_rx_macro_get_hph_hd2_mode, lpass_cdc_rx_macro_put_hph_hd2_mode), lpass_cdc_rx_macro_get_hph_hd2_mode, lpass_cdc_rx_macro_put_hph_hd2_mode),
@@ -3838,10 +3870,12 @@ static const struct snd_kcontrol_new lpass_cdc_rx_macro_snd_controls[] = {
LPASS_CDC_RX_MACRO_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4), LPASS_CDC_RX_MACRO_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
LPASS_CDC_RX_MACRO_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5), LPASS_CDC_RX_MACRO_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
#ifdef CONFIG_BOLERO_VER_2P6
LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX0 FIR Coeff Group0", RX0_PATH, GRP0), LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX0 FIR Coeff Group0", RX0_PATH, GRP0),
LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX0 FIR Coeff Group1", RX0_PATH, GRP1), LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX0 FIR Coeff Group1", RX0_PATH, GRP1),
LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX1 FIR Coeff Group0", RX1_PATH, GRP0), LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX1 FIR Coeff Group0", RX1_PATH, GRP0),
LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX1 FIR Coeff Group1", RX1_PATH, GRP1), LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX1 FIR Coeff Group1", RX1_PATH, GRP1),
#endif
}; };
static int lpass_cdc_rx_macro_enable_echo(struct snd_soc_dapm_widget *w, static int lpass_cdc_rx_macro_enable_echo(struct snd_soc_dapm_widget *w,
@@ -4475,6 +4509,7 @@ exit:
return ret; return ret;
} }
#ifdef CONFIG_BOLERO_VER_2P6
/** /**
* lpass_cdc_rx_set_fir_capability - Set RX HIFI FIR Filter capability * lpass_cdc_rx_set_fir_capability - Set RX HIFI FIR Filter capability
* *
@@ -4501,6 +4536,7 @@ int lpass_cdc_rx_set_fir_capability(struct snd_soc_component *component, bool ca
return 0; return 0;
} }
EXPORT_SYMBOL(lpass_cdc_rx_set_fir_capability); EXPORT_SYMBOL(lpass_cdc_rx_set_fir_capability);
#endif
static const struct lpass_cdc_rx_macro_reg_mask_val static const struct lpass_cdc_rx_macro_reg_mask_val
lpass_cdc_rx_macro_reg_init[] = { lpass_cdc_rx_macro_reg_init[] = {
@@ -4512,6 +4548,55 @@ static const struct lpass_cdc_rx_macro_reg_mask_val
{LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x03, 0x02}, {LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x03, 0x02},
}; };
#ifdef CONFIG_BOLERO_VER_2P1
static void lpass_cdc_rx_macro_init_bcl_pmic_reg(struct snd_soc_component *component)
{
struct device *rx_dev = NULL;
struct lpass_cdc_rx_macro_priv *rx_priv = NULL;
if (!component) {
pr_err("%s: NULL component pointer!\n", __func__);
return;
}
if (!lpass_cdc_rx_macro_get_data(component, &rx_dev, &rx_priv, __func__))
return;
switch (rx_priv->bcl_pmic_params.id) {
case 0:
/* Enable ID0 to listen to respective PMIC group interrupts */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0x02, 0x02);
/* Update MC_SID0 */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0x0F,
rx_priv->bcl_pmic_params.sid);
/* Update MC_PPID0 */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2, 0xFF,
rx_priv->bcl_pmic_params.ppid);
break;
case 1:
/* Enable ID1 to listen to respective PMIC group interrupts */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0x01, 0x01);
/* Update MC_SID1 */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3, 0x0F,
rx_priv->bcl_pmic_params.sid);
/* Update MC_PPID1 */
snd_soc_component_update_bits(component,
LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0xFF,
rx_priv->bcl_pmic_params.ppid);
break;
default:
dev_err(rx_dev, "%s: PMIC ID is invalid %d\n",
__func__, rx_priv->bcl_pmic_params.id);
break;
}
}
#endif
static int lpass_cdc_rx_macro_init(struct snd_soc_component *component) static int lpass_cdc_rx_macro_init(struct snd_soc_component *component)
{ {
struct snd_soc_dapm_context *dapm = struct snd_soc_dapm_context *dapm =
@@ -4583,6 +4668,9 @@ static int lpass_cdc_rx_macro_init(struct snd_soc_component *component)
lpass_cdc_rx_macro_reg_init[i].val); lpass_cdc_rx_macro_reg_init[i].val);
rx_priv->component = component; rx_priv->component = component;
#ifdef CONFIG_BOLERO_VER_2P1
lpass_cdc_rx_macro_init_bcl_pmic_reg(component);
#endif
return 0; return 0;
} }
@@ -4725,8 +4813,13 @@ static int lpass_cdc_rx_macro_probe(struct platform_device *pdev)
u32 rx_base_addr = 0, muxsel = 0; u32 rx_base_addr = 0, muxsel = 0;
char __iomem *rx_io_base = NULL, *muxsel_io = NULL; char __iomem *rx_io_base = NULL, *muxsel_io = NULL;
int ret = 0; int ret = 0;
#ifdef CONFIG_BOLERO_VER_2P1
u8 bcl_pmic_params[3];
#endif
u32 default_clk_id = 0; u32 default_clk_id = 0;
#ifdef CONFIG_BOLERO_VER_2P6
struct clk *hifi_fir_clk = NULL; struct clk *hifi_fir_clk = NULL;
#endif
u32 is_used_rx_swr_gpio = 1; u32 is_used_rx_swr_gpio = 1;
const char *is_used_rx_swr_gpio_dt = "qcom,is-used-swr-gpio"; const char *is_used_rx_swr_gpio_dt = "qcom,is-used-swr-gpio";
@@ -4816,11 +4909,26 @@ static int lpass_cdc_rx_macro_probe(struct platform_device *pdev)
rx_priv->swr_plat_data.core_vote = lpass_cdc_rx_macro_core_vote; rx_priv->swr_plat_data.core_vote = lpass_cdc_rx_macro_core_vote;
rx_priv->swr_plat_data.handle_irq = NULL; rx_priv->swr_plat_data.handle_irq = NULL;
#ifdef CONFIG_BOLERO_VER_2P1
ret = of_property_read_u8_array(pdev->dev.of_node,
"qcom,rx-bcl-pmic-params", bcl_pmic_params,
sizeof(bcl_pmic_params));
if (ret) {
dev_dbg(&pdev->dev, "%s: could not find %s entry in dt\n",
__func__, "qcom,rx-bcl-pmic-params");
} else {
rx_priv->bcl_pmic_params.id = bcl_pmic_params[0];
rx_priv->bcl_pmic_params.sid = bcl_pmic_params[1];
rx_priv->bcl_pmic_params.ppid = bcl_pmic_params[2];
}
#endif
rx_priv->clk_id = default_clk_id; rx_priv->clk_id = default_clk_id;
rx_priv->default_clk_id = default_clk_id; rx_priv->default_clk_id = default_clk_id;
ops.clk_id_req = rx_priv->clk_id; ops.clk_id_req = rx_priv->clk_id;
ops.default_clk_id = default_clk_id; ops.default_clk_id = default_clk_id;
#ifdef CONFIG_BOLERO_VER_2P6
hifi_fir_clk = devm_clk_get(&pdev->dev, "rx_mclk2_2x_clk"); hifi_fir_clk = devm_clk_get(&pdev->dev, "rx_mclk2_2x_clk");
if (IS_ERR(hifi_fir_clk)) { if (IS_ERR(hifi_fir_clk)) {
ret = PTR_ERR(hifi_fir_clk); ret = PTR_ERR(hifi_fir_clk);
@@ -4829,6 +4937,7 @@ static int lpass_cdc_rx_macro_probe(struct platform_device *pdev)
hifi_fir_clk = NULL; hifi_fir_clk = NULL;
} }
rx_priv->hifi_fir_clk = hifi_fir_clk; rx_priv->hifi_fir_clk = hifi_fir_clk;
#endif
rx_priv->is_aux_hpf_on = 1; rx_priv->is_aux_hpf_on = 1;

215
asoc/codecs/lpass-cdc/lpass-cdc-tables.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#include <linux/types.h> #include <linux/types.h>
@@ -15,6 +15,7 @@ u8 lpass_cdc_tx_reg_access[LPASS_CDC_TX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TOP_CFG0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_ANC_CFG)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_ANC_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_CTRL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_FREQ_MCLK)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_BUS)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_EN)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
@@ -286,17 +287,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG1)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG1)] = RD_WR_REG,
@@ -320,17 +310,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG1)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG1)] = RD_WR_REG,
@@ -351,61 +330,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_PATH_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG1)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG1)] = RD_WR_REG,
@@ -419,18 +343,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL5)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL6)] = RD_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL6)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL7)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL10)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL11)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL12)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL13)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL14)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL15)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL16)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL17)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL18)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL19)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL1)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL2)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL2)] = RD_WR_REG,
@@ -439,18 +351,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL5)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL6)] = RD_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL6)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL7)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL10)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL11)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL12)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL13)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL14)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL15)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL16)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL17)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL18)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL19)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL)] = RD_WR_REG,
@@ -532,6 +432,117 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
[LPASS_CDC_REG(LPASS_CDC_RX_DSD1_CFG0)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_DSD1_CFG0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_DSD1_CFG1)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_DSD1_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_DSD1_CFG2)] = RD_WR_REG, [LPASS_CDC_REG(LPASS_CDC_RX_DSD1_CFG2)] = RD_WR_REG,
#ifdef CONFIG_BOLERO_VER_2P6
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON)] = WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL)] = RD_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL10)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL11)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL12)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL13)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL14)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL15)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL16)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL17)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL18)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL19)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL8)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL9)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL10)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL11)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL12)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL13)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL14)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL15)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL16)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL17)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL18)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL19)] = RD_WR_REG,
#else
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4)] = RD_WR_REG,
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_ST)] = RD_REG,
#endif
}; };
u8 lpass_cdc_va_reg_access[LPASS_CDC_VA_MACRO_MAX] = { u8 lpass_cdc_va_reg_access[LPASS_CDC_VA_MACRO_MAX] = {

2
asoc/pineapple.c
View File

@@ -2032,10 +2032,12 @@ static int msm_rx_tx_codec_init(struct snd_soc_pcm_runtime *rtd)
wcd939x_info_create_codec_entry(pdata->codec_root, component); wcd939x_info_create_codec_entry(pdata->codec_root, component);
codec_variant = wcd939x_get_codec_variant(component); codec_variant = wcd939x_get_codec_variant(component);
dev_dbg(component->dev, "%s: variant %d\n", __func__, codec_variant); dev_dbg(component->dev, "%s: variant %d\n", __func__, codec_variant);
#ifdef CONFIG_BOLERO_VER_2P6
if (codec_variant == WCD9395) if (codec_variant == WCD9395)
ret = lpass_cdc_rx_set_fir_capability(lpass_cdc_component, true); ret = lpass_cdc_rx_set_fir_capability(lpass_cdc_component, true);
else else
ret = lpass_cdc_rx_set_fir_capability(lpass_cdc_component, false); ret = lpass_cdc_rx_set_fir_capability(lpass_cdc_component, false);
#endif
} }
if (ret < 0) { if (ret < 0) {

7
include/bindings/qcom,lpass-cdc-clk-rsc.h
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#ifndef __LPASS_CDC_CLK_RSC_H #ifndef __LPASS_CDC_CLK_RSC_H
@@ -15,6 +16,10 @@
#define RX_TX_CORE_CLK 5 #define RX_TX_CORE_CLK 5
#define WSA_TX_CORE_CLK 6 #define WSA_TX_CORE_CLK 6
#define WSA2_TX_CORE_CLK 7 #define WSA2_TX_CORE_CLK 7
#define MAX_CLK 8 #define TX_NPL_CLK 8
#define RX_NPL_CLK 9
#define WSA_NPL_CLK 10
#define VA_NPL_CLK 11
#define MAX_CLK 12
#endif /* __LPASS_CDC_CLK_RSC_H */ #endif /* __LPASS_CDC_CLK_RSC_H */