msm: camera: isp: Add support for pixel path in IFE Lite Top

This change adds required functionality, register information and
fixes for pixel path in IFE Lite.

CRs-Fixed: 2846451
Change-Id: I10c9f193547a2f9d112a7d00750997e71b11c7fb
Signed-off-by: Anand Ravi <[email protected]>

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c

@@ -845,6 +845,7 @@ static int cam_ife_csid_ver2_ipp_bottom_half(
 	uint32_t                                   irq_status_ipp;
 	uint32_t                                   err_mask;
 	char                                       tag[15];
+	int                                        irq_idx;
 
 	if (!handler_priv || !evt_payload_priv) {
 		CAM_ERR(CAM_ISP, "Invalid params");
@@ -853,8 +854,14 @@ static int cam_ife_csid_ver2_ipp_bottom_half(
 
 	payload = evt_payload_priv;
 	csid_hw = handler_priv;
+	csid_reg = csid_hw->core_info->csid_reg;
 
-	irq_status_ipp = payload->irq_reg_val[CAM_IFE_CSID_IRQ_REG_IPP];
+	irq_idx = cam_ife_csid_get_rt_irq_idx(
+			CAM_IFE_CSID_IRQ_REG_IPP,
+			csid_reg->cmn_reg->num_pix,
+			csid_reg->cmn_reg->num_ppp,
+			csid_reg->cmn_reg->num_rdis);
+	irq_status_ipp = payload->irq_reg_val[irq_idx];
 
 	snprintf(tag, sizeof(tag), "CSID:%d IPP", csid_hw->hw_intf->hw_idx);
 
@@ -889,9 +896,6 @@ static int cam_ife_csid_ver2_ipp_bottom_half(
 				CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info);
 	}
 
-	csid_reg = (struct cam_ife_csid_ver2_reg_info *)
-			csid_hw->core_info->csid_reg;
-
 	err_mask = csid_reg->ipp_reg->fatal_err_mask |
 			csid_reg->ipp_reg->non_fatal_err_mask;
 

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite68x.h

@@ -50,6 +50,15 @@ static struct cam_vfe_top_ver4_reg_offset_common vfe68x_top_common_reg = {
 	.top_debug_4              = 0x0000106C,
 };
 
+static struct cam_vfe_ver4_path_reg_data vfe68x_ipp_reg_data =
+{
+	.sof_irq_mask                    = 0x1,
+	.eof_irq_mask                    = 0x2,
+	.error_irq_mask                  = 0x3,
+	.enable_diagnostic_hw            = 0x1,
+	.top_debug_cfg_en                = 0x1,
+};
+
 static struct cam_vfe_ver4_path_reg_data vfe68x_rdi_reg_data[4] = {
 
 	{
@@ -109,8 +118,13 @@ static struct cam_vfe_top_ver4_hw_info vfe68x_top_hw_info = {
 	.rdi_hw_info[1] = &vfe68x_rdi_hw_info[1],
 	.rdi_hw_info[2] = &vfe68x_rdi_hw_info[2],
 	.rdi_hw_info[3] = &vfe68x_rdi_hw_info[3],
-	.num_mux = 4,
+	.vfe_full_hw_info = {
+		.common_reg     = &vfe68x_top_common_reg,
+		.reg_data       = &vfe68x_ipp_reg_data,
+	},
+	.num_mux = 5,
 	.mux_type = {
+		CAM_VFE_CAMIF_VER_4_0,
 		CAM_VFE_RDI_VER_1_0,
 		CAM_VFE_RDI_VER_1_0,
 		CAM_VFE_RDI_VER_1_0,

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c

@@ -59,6 +59,11 @@ enum cam_vfe_bus_ver3_packer_format {
 	PACKER_FMT_VER3_PLAIN_32,
 	PACKER_FMT_VER3_PLAIN_64,
 	PACKER_FMT_VER3_TP_10,
+	PACKER_FMT_VER3_MIPI10,
+	PACKER_FMT_VER3_MIPI12,
+	PACKER_FMT_VER3_MIPI14,
+	PACKER_FMT_VER3_MIPI20,
+	PACKER_FMT_VER3_PLAIN32_20BPP,
 	PACKER_FMT_VER3_MAX,
 };
 
@@ -467,6 +472,16 @@ static const struct cam_vfe_bus_error_info vfe_lite_error_list[] = {
 		.bitmask = 0x08,
 		.vfe_output = CAM_VFE_BUS_VER3_VFE_OUT_RDI3,
 		.error_description = "Lite RDI 3"
+	},
+	{
+		.bitmask = 0x10,
+		.vfe_output = CAM_VFE_BUS_VER3_VFE_OUT_PREPROCESS_RAW,
+		.error_description = "Lite Pixel Path Preprocess Raw"
+	},
+	{
+		.bitmask = 0x20,
+		.vfe_output = CAM_VFE_BUS_VER3_VFE_OUT_STATS_BG,
+		.error_description = "Lite Pixel Path Stats"
 	}
 };
 
@@ -784,18 +799,22 @@ static enum cam_vfe_bus_ver3_packer_format
 {
 	switch (out_fmt) {
 	case CAM_FORMAT_MIPI_RAW_6:
-	case CAM_FORMAT_MIPI_RAW_8:
-	case CAM_FORMAT_MIPI_RAW_10:
-	case CAM_FORMAT_MIPI_RAW_12:
-	case CAM_FORMAT_MIPI_RAW_14:
 	case CAM_FORMAT_MIPI_RAW_16:
-	case CAM_FORMAT_MIPI_RAW_20:
 	case CAM_FORMAT_PLAIN16_8:
 	case CAM_FORMAT_PLAIN128:
 	case CAM_FORMAT_PD8:
 		return PACKER_FMT_VER3_PLAIN_128;
+	case CAM_FORMAT_MIPI_RAW_8:
 	case CAM_FORMAT_PLAIN8:
 		return PACKER_FMT_VER3_PLAIN_8;
+	case CAM_FORMAT_MIPI_RAW_10:
+		return PACKER_FMT_VER3_MIPI10;
+	case CAM_FORMAT_MIPI_RAW_12:
+		return PACKER_FMT_VER3_MIPI12;
+	case CAM_FORMAT_MIPI_RAW_14:
+		return PACKER_FMT_VER3_MIPI14;
+	case CAM_FORMAT_MIPI_RAW_20:
+		return PACKER_FMT_VER3_MIPI20;
 	case CAM_FORMAT_NV21:
 		if ((wm_index == 1) || (wm_index == 3) || (wm_index == 5))
 			return PACKER_FMT_VER3_PLAIN_8_LSB_MSB_10_ODD_EVEN;
@@ -815,6 +834,8 @@ static enum cam_vfe_bus_ver3_packer_format
 	case CAM_FORMAT_PLAIN32:
 	case CAM_FORMAT_ARGB:
 		return PACKER_FMT_VER3_PLAIN_32;
+	case CAM_FORMAT_PLAIN32_20:
+		return PACKER_FMT_VER3_PLAIN32_20BPP;
 	case CAM_FORMAT_PLAIN64:
 	case CAM_FORMAT_ARGB_16:
 	case CAM_FORMAT_PD10:
@@ -1091,8 +1112,8 @@ static int cam_vfe_bus_ver3_acquire_wm(
 
 	if ((vfe_out_res_id >= CAM_VFE_BUS_VER3_VFE_OUT_RDI0) &&
 		(vfe_out_res_id <= CAM_VFE_BUS_VER3_VFE_OUT_RDI3)) {
-
-		rsrc_data->pack_fmt = 0x0;
+		/* Force RDI to use PLAIN128 */
+		rsrc_data->pack_fmt = PACKER_FMT_VER3_PLAIN_128;
 		switch (rsrc_data->format) {
 		case CAM_FORMAT_MIPI_RAW_6:
 		case CAM_FORMAT_MIPI_RAW_8:
@@ -1302,6 +1323,7 @@ static int cam_vfe_bus_ver3_acquire_wm(
 		case CAM_FORMAT_PLAIN16_8:
 		case CAM_FORMAT_PLAIN16_10:
 		case CAM_FORMAT_PLAIN16_12:
+		case CAM_FORMAT_PLAIN16_14:
 			rsrc_data->width = 0;
 			rsrc_data->height = 0;
 			rsrc_data->stride = 1;
@@ -1444,7 +1466,7 @@ static int cam_vfe_bus_ver3_start_wm(struct cam_isp_resource_node *wm_res)
 		(uint32_t) rsrc_data->hw_regs->cfg, rsrc_data->en_cfg,
 		rsrc_data->width, rsrc_data->height);
 	CAM_DBG(CAM_ISP, "WM:%d pk_fmt:%d stride:%d burst len:%d",
-		rsrc_data->index, rsrc_data->pack_fmt & PACKER_FMT_VER3_MAX,
+		rsrc_data->index, rsrc_data->pack_fmt,
 		rsrc_data->stride, 0xF);
 
 	wm_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING;

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c

@@ -30,7 +30,6 @@ struct cam_vfe_mux_ver4_data {
 	void __iomem                                *mem_base;
 	struct cam_hw_intf                          *hw_intf;
 	struct cam_vfe_top_ver4_reg_offset_common   *common_reg;
-	struct cam_hw_soc_info                      *soc_info;
 	struct cam_vfe_top_common_cfg                cam_common_cfg;
 	struct cam_vfe_ver4_path_reg_data      *reg_data;
 
@@ -62,7 +61,7 @@ struct cam_vfe_mux_ver4_data {
 	uint32_t                           is_dual;
 	bool                               is_fe_enabled;
 	bool                               is_offline;
-
+	bool                               is_lite;
 	bool                               is_pixel_path;
 	bool                               sfe_binned_epoch_cfg;
 
@@ -946,7 +945,6 @@ static int cam_vfe_resource_start(
 	int                             rc = 0;
 	uint32_t                        err_irq_mask[CAM_IFE_IRQ_REGISTERS_MAX];
 	uint32_t                        irq_mask[CAM_IFE_IRQ_REGISTERS_MAX];
-	struct cam_vfe_soc_private     *soc_private;
 
 	if (!vfe_res) {
 		CAM_ERR(CAM_ISP, "Error, Invalid input arguments");
@@ -964,21 +962,13 @@ static int cam_vfe_resource_start(
 
 	rsrc_data = (struct cam_vfe_mux_ver4_data *)vfe_res->res_priv;
 
-	soc_private = rsrc_data->soc_info->soc_private;
-
-	if (!soc_private) {
-		CAM_ERR(CAM_ISP, "Error, soc_private NULL");
-		return -ENODEV;
-	}
-
 	/* config debug status registers */
 	cam_io_w_mb(rsrc_data->reg_data->top_debug_cfg_en, rsrc_data->mem_base +
 		rsrc_data->common_reg->top_debug_cfg);
 
-	if (soc_private->is_ife_lite | !rsrc_data->is_pixel_path)
+	if (rsrc_data->is_lite || !rsrc_data->is_pixel_path)
 		goto skip_core_cfg;
 
-
 	val = cam_io_r_mb(rsrc_data->mem_base +
 		rsrc_data->common_reg->core_cfg_0);
 
@@ -1009,7 +999,6 @@ static int cam_vfe_resource_start(
 	cam_io_w_mb(val, rsrc_data->mem_base +
 		rsrc_data->common_reg->core_cfg_0);
 
-
 	/* pixel fmt */
 	val = cam_io_r_mb(rsrc_data->mem_base +
 		rsrc_data->common_reg->core_cfg_1);
@@ -1050,8 +1039,12 @@ skip_core_cfg:
 			rsrc_data->common_reg->diag_config);
 	}
 
-	if ((rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) &&
-		rsrc_data->is_dual)
+	/* Skip subscribing to timing irqs in these scenarios:
+	 *     1. Resource is dual IFE slave
+	 *     2. Resource is not primary RDI
+	 */
+	if (((rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) && rsrc_data->is_dual) ||
+		(!rsrc_data->is_pixel_path && !vfe_res->rdi_only_ctx))
 		goto subscribe_err;
 
 	irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] =
@@ -1140,8 +1133,8 @@ static int cam_vfe_resource_stop(
 
 	vfe_priv = (struct cam_vfe_mux_ver4_data *)vfe_res->res_priv;
 
-	if (!vfe_priv->is_pixel_path)
-		goto unsub_irq;
+	if (vfe_priv->is_lite || !vfe_priv->is_pixel_path)
+		goto skip_core_decfg;
 
 	if ((vfe_priv->dsp_mode >= CAM_ISP_DSP_MODE_ONE_WAY) &&
 		(vfe_priv->dsp_mode <= CAM_ISP_DSP_MODE_ROUND)) {
@@ -1152,6 +1145,7 @@ static int cam_vfe_resource_stop(
 			vfe_priv->common_reg->core_cfg_0);
 	}
 
+skip_core_decfg:
 	if (vfe_res->res_state == CAM_ISP_RESOURCE_STATE_STREAMING)
 		vfe_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED;
 
@@ -1163,7 +1157,6 @@ static int cam_vfe_resource_stop(
 			vfe_priv->common_reg->diag_config);
 	}
 
-unsub_irq:
 	if (vfe_priv->irq_handle) {
 		cam_irq_controller_unsubscribe_irq(
 			vfe_priv->vfe_irq_controller, vfe_priv->irq_handle);
@@ -1196,6 +1189,7 @@ int cam_vfe_res_init(
 {
 	struct cam_vfe_mux_ver4_data           *vfe_priv = NULL;
 	struct cam_vfe_ver4_path_hw_info       *hw_info = vfe_hw_info;
+	struct cam_vfe_soc_private    *soc_priv = soc_info->soc_private;
 	int i;
 
 	vfe_priv = kzalloc(sizeof(struct cam_vfe_mux_ver4_data),
@@ -1208,7 +1202,7 @@ int cam_vfe_res_init(
 	vfe_priv->common_reg  = hw_info->common_reg;
 	vfe_priv->reg_data    = hw_info->reg_data;
 	vfe_priv->hw_intf     = hw_intf;
-	vfe_priv->soc_info    = soc_info;
+	vfe_priv->is_lite     = soc_priv->is_ife_lite;
 	vfe_priv->vfe_irq_controller = vfe_irq_controller;
 	vfe_priv->is_pixel_path = (vfe_res->res_id == CAM_ISP_HW_VFE_IN_CAMIF);