fw-api: Add missing header for qca8074V2

Add HW missing header for qca8074V2.

Change-Id: Ic0af0355f7eb8720dcb7276944604f94a0276f3a

hw/qca8074/v2/phyrx_other_receive_info_su_evm_details.h

@@ -0,0 +1,900 @@
+/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_H_
+#define _PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	number_of_symbols[15:0], nss_count[23:16], pilot_count[31:24]
+//	1	pilot_0_evm[31:0]
+//	2	pilot_1_evm[31:0]
+//	3	pilot_2_evm[31:0]
+//	4	pilot_3_evm[31:0]
+//	5	pilot_4_evm[31:0]
+//	6	pilot_5_evm[31:0]
+//	7	pilot_6_evm[31:0]
+//	8	pilot_7_evm[31:0]
+//	9	pilot_8_evm[31:0]
+//	10	pilot_9_evm[31:0]
+//	11	pilot_10_evm[31:0]
+//	12	pilot_11_evm[31:0]
+//	13	pilot_12_evm[31:0]
+//	14	pilot_13_evm[31:0]
+//	15	pilot_14_evm[31:0]
+//	16	pilot_15_evm[31:0]
+//	17	pilot_16_evm[31:0]
+//	18	pilot_17_evm[31:0]
+//	19	pilot_18_evm[31:0]
+//	20	pilot_19_evm[31:0]
+//	21	pilot_20_evm[31:0]
+//	22	pilot_21_evm[31:0]
+//	23	pilot_22_evm[31:0]
+//	24	pilot_23_evm[31:0]
+//	25	pilot_24_evm[31:0]
+//	26	pilot_25_evm[31:0]
+//	27	pilot_26_evm[31:0]
+//	28	pilot_27_evm[31:0]
+//	29	pilot_28_evm[31:0]
+//	30	pilot_29_evm[31:0]
+//	31	pilot_30_evm[31:0]
+//	32	pilot_31_evm[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS 33
+
+struct phyrx_other_receive_info_su_evm_details {
+             uint32_t number_of_symbols               : 16, //[15:0]
+                      nss_count                       :  8, //[23:16]
+                      pilot_count                     :  8; //[31:24]
+             uint32_t pilot_0_evm                     : 32; //[31:0]
+             uint32_t pilot_1_evm                     : 32; //[31:0]
+             uint32_t pilot_2_evm                     : 32; //[31:0]
+             uint32_t pilot_3_evm                     : 32; //[31:0]
+             uint32_t pilot_4_evm                     : 32; //[31:0]
+             uint32_t pilot_5_evm                     : 32; //[31:0]
+             uint32_t pilot_6_evm                     : 32; //[31:0]
+             uint32_t pilot_7_evm                     : 32; //[31:0]
+             uint32_t pilot_8_evm                     : 32; //[31:0]
+             uint32_t pilot_9_evm                     : 32; //[31:0]
+             uint32_t pilot_10_evm                    : 32; //[31:0]
+             uint32_t pilot_11_evm                    : 32; //[31:0]
+             uint32_t pilot_12_evm                    : 32; //[31:0]
+             uint32_t pilot_13_evm                    : 32; //[31:0]
+             uint32_t pilot_14_evm                    : 32; //[31:0]
+             uint32_t pilot_15_evm                    : 32; //[31:0]
+             uint32_t pilot_16_evm                    : 32; //[31:0]
+             uint32_t pilot_17_evm                    : 32; //[31:0]
+             uint32_t pilot_18_evm                    : 32; //[31:0]
+             uint32_t pilot_19_evm                    : 32; //[31:0]
+             uint32_t pilot_20_evm                    : 32; //[31:0]
+             uint32_t pilot_21_evm                    : 32; //[31:0]
+             uint32_t pilot_22_evm                    : 32; //[31:0]
+             uint32_t pilot_23_evm                    : 32; //[31:0]
+             uint32_t pilot_24_evm                    : 32; //[31:0]
+             uint32_t pilot_25_evm                    : 32; //[31:0]
+             uint32_t pilot_26_evm                    : 32; //[31:0]
+             uint32_t pilot_27_evm                    : 32; //[31:0]
+             uint32_t pilot_28_evm                    : 32; //[31:0]
+             uint32_t pilot_29_evm                    : 32; //[31:0]
+             uint32_t pilot_30_evm                    : 32; //[31:0]
+             uint32_t pilot_31_evm                    : 32; //[31:0]
+};
+
+/*
+
+number_of_symbols
+			
+			The number of symbols over which this EVM measurement
+			was done
+			
+			<legal all>
+
+nss_count
+			
+			The number of Spatial Streams in this SU reception.
+			
+			<legal 1-8>
+
+pilot_count
+			
+			The number of pilots captured per Spatial Stream in this
+			log
+			
+			<legal 1-32>
+
+pilot_0_evm
+			
+			
+			
+			
+			Example mapping of Nss and pilots to the evm fields:
+			
+			With NSS_count = 2, Pilot_count = 3
+			
+			Pilot_0_evm => NSS 0, Pilot 0
+			
+			Pilot_1_evm => NSS 1, Pilot 0
+			
+			Pilot_2_evm => NSS 0, Pilot 1
+			
+			Pilot_3_evm => NSS 1, Pilot 1
+			
+			Pilot_4_evm => NSS 0, Pilot 2
+			
+			Pilot_5_evm => NSS 1, Pilot 2
+			
+			
+			
+			<legal all>
+
+pilot_1_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_2_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_3_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_4_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_5_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_6_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_7_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_8_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_9_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_10_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_11_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_12_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_13_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_14_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_15_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_16_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_17_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_18_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_19_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_20_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_21_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_22_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_23_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_24_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_25_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_26_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_27_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_28_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_29_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_30_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+
+pilot_31_evm
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS
+			
+			The number of symbols over which this EVM measurement
+			was done
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS_OFFSET 0x00000000
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS_MASK 0x0000ffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NSS_COUNT
+			
+			The number of Spatial Streams in this SU reception.
+			
+			<legal 1-8>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NSS_COUNT_OFFSET   0x00000000
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NSS_COUNT_LSB      16
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NSS_COUNT_MASK     0x00ff0000
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_PILOT_COUNT
+			
+			The number of pilots captured per Spatial Stream in this
+			log
+			
+			<legal 1-32>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_PILOT_COUNT_OFFSET 0x00000000
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_PILOT_COUNT_LSB    24
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_PILOT_COUNT_MASK   0xff000000
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_1_PILOT_0_EVM
+			
+			
+			
+			
+			Example mapping of Nss and pilots to the evm fields:
+			
+			With NSS_count = 2, Pilot_count = 3
+			
+			Pilot_0_evm => NSS 0, Pilot 0
+			
+			Pilot_1_evm => NSS 1, Pilot 0
+			
+			Pilot_2_evm => NSS 0, Pilot 1
+			
+			Pilot_3_evm => NSS 1, Pilot 1
+			
+			Pilot_4_evm => NSS 0, Pilot 2
+			
+			Pilot_5_evm => NSS 1, Pilot 2
+			
+			
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_1_PILOT_0_EVM_OFFSET 0x00000004
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_1_PILOT_0_EVM_LSB    0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_1_PILOT_0_EVM_MASK   0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_2_PILOT_1_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_2_PILOT_1_EVM_OFFSET 0x00000008
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_2_PILOT_1_EVM_LSB    0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_2_PILOT_1_EVM_MASK   0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_3_PILOT_2_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_3_PILOT_2_EVM_OFFSET 0x0000000c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_3_PILOT_2_EVM_LSB    0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_3_PILOT_2_EVM_MASK   0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_4_PILOT_3_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_4_PILOT_3_EVM_OFFSET 0x00000010
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_4_PILOT_3_EVM_LSB    0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_4_PILOT_3_EVM_MASK   0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_5_PILOT_4_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_5_PILOT_4_EVM_OFFSET 0x00000014
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_5_PILOT_4_EVM_LSB    0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_5_PILOT_4_EVM_MASK   0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_6_PILOT_5_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_6_PILOT_5_EVM_OFFSET 0x00000018
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_6_PILOT_5_EVM_LSB    0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_6_PILOT_5_EVM_MASK   0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_7_PILOT_6_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_7_PILOT_6_EVM_OFFSET 0x0000001c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_7_PILOT_6_EVM_LSB    0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_7_PILOT_6_EVM_MASK   0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_8_PILOT_7_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_8_PILOT_7_EVM_OFFSET 0x00000020
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_8_PILOT_7_EVM_LSB    0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_8_PILOT_7_EVM_MASK   0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_9_PILOT_8_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_9_PILOT_8_EVM_OFFSET 0x00000024
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_9_PILOT_8_EVM_LSB    0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_9_PILOT_8_EVM_MASK   0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_10_PILOT_9_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_10_PILOT_9_EVM_OFFSET 0x00000028
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_10_PILOT_9_EVM_LSB   0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_10_PILOT_9_EVM_MASK  0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_11_PILOT_10_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_11_PILOT_10_EVM_OFFSET 0x0000002c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_11_PILOT_10_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_11_PILOT_10_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_12_PILOT_11_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_12_PILOT_11_EVM_OFFSET 0x00000030
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_12_PILOT_11_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_12_PILOT_11_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_13_PILOT_12_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_13_PILOT_12_EVM_OFFSET 0x00000034
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_13_PILOT_12_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_13_PILOT_12_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_14_PILOT_13_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_14_PILOT_13_EVM_OFFSET 0x00000038
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_14_PILOT_13_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_14_PILOT_13_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_15_PILOT_14_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_15_PILOT_14_EVM_OFFSET 0x0000003c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_15_PILOT_14_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_15_PILOT_14_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_16_PILOT_15_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_16_PILOT_15_EVM_OFFSET 0x00000040
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_16_PILOT_15_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_16_PILOT_15_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_17_PILOT_16_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_17_PILOT_16_EVM_OFFSET 0x00000044
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_17_PILOT_16_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_17_PILOT_16_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_18_PILOT_17_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_18_PILOT_17_EVM_OFFSET 0x00000048
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_18_PILOT_17_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_18_PILOT_17_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_19_PILOT_18_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_19_PILOT_18_EVM_OFFSET 0x0000004c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_19_PILOT_18_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_19_PILOT_18_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_20_PILOT_19_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_20_PILOT_19_EVM_OFFSET 0x00000050
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_20_PILOT_19_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_20_PILOT_19_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_21_PILOT_20_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_21_PILOT_20_EVM_OFFSET 0x00000054
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_21_PILOT_20_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_21_PILOT_20_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_22_PILOT_21_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_22_PILOT_21_EVM_OFFSET 0x00000058
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_22_PILOT_21_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_22_PILOT_21_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_23_PILOT_22_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_23_PILOT_22_EVM_OFFSET 0x0000005c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_23_PILOT_22_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_23_PILOT_22_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_24_PILOT_23_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_24_PILOT_23_EVM_OFFSET 0x00000060
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_24_PILOT_23_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_24_PILOT_23_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_25_PILOT_24_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_25_PILOT_24_EVM_OFFSET 0x00000064
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_25_PILOT_24_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_25_PILOT_24_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_26_PILOT_25_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_26_PILOT_25_EVM_OFFSET 0x00000068
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_26_PILOT_25_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_26_PILOT_25_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_27_PILOT_26_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_27_PILOT_26_EVM_OFFSET 0x0000006c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_27_PILOT_26_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_27_PILOT_26_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_28_PILOT_27_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_28_PILOT_27_EVM_OFFSET 0x00000070
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_28_PILOT_27_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_28_PILOT_27_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_29_PILOT_28_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_29_PILOT_28_EVM_OFFSET 0x00000074
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_29_PILOT_28_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_29_PILOT_28_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_30_PILOT_29_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_30_PILOT_29_EVM_OFFSET 0x00000078
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_30_PILOT_29_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_30_PILOT_29_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_31_PILOT_30_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_31_PILOT_30_EVM_OFFSET 0x0000007c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_31_PILOT_30_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_31_PILOT_30_EVM_MASK 0xffffffff
+
+/* Description		PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_32_PILOT_31_EVM
+			
+			
+			
+			
+			See Pilot_0_evm descriptions details for mapping info
+			
+			<legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_32_PILOT_31_EVM_OFFSET 0x00000080
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_32_PILOT_31_EVM_LSB  0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_32_PILOT_31_EVM_MASK 0xffffffff
+
+
+#endif // _PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_H_

hw/qca8074/v2/phyrx_pkt_end_info.h

@@ -0,0 +1,1901 @@
+/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _PHYRX_PKT_END_INFO_H_
+#define _PHYRX_PKT_END_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_location_info.h"
+#include "rx_timing_offset_info.h"
+#include "receive_rssi_info.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	phy_internal_nap[0], location_info_valid[1], timing_info_valid[2], rssi_info_valid[3], rx_frame_correction_needed[4], frameless_frame_received[5], reserved_0a[11:6], dl_ofdma_info_valid[12], dl_ofdma_ru_start_index[19:13], dl_ofdma_ru_width[26:20], reserved_0b[31:27]
+//	1	phy_timestamp_1_lower_32[31:0]
+//	2	phy_timestamp_1_upper_32[31:0]
+//	3	phy_timestamp_2_lower_32[31:0]
+//	4	phy_timestamp_2_upper_32[31:0]
+//	5-13	struct rx_location_info rx_location_info_details;
+//	14	struct rx_timing_offset_info rx_timing_offset_info_details;
+//	15-30	struct receive_rssi_info post_rssi_info_details;
+//	31	phy_sw_status_31_0[31:0]
+//	32	phy_sw_status_63_32[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33
+
+struct phyrx_pkt_end_info {
+             uint32_t phy_internal_nap                :  1, //[0]
+                      location_info_valid             :  1, //[1]
+                      timing_info_valid               :  1, //[2]
+                      rssi_info_valid                 :  1, //[3]
+                      rx_frame_correction_needed      :  1, //[4]
+                      frameless_frame_received        :  1, //[5]
+                      reserved_0a                     :  6, //[11:6]
+                      dl_ofdma_info_valid             :  1, //[12]
+                      dl_ofdma_ru_start_index         :  7, //[19:13]
+                      dl_ofdma_ru_width               :  7, //[26:20]
+                      reserved_0b                     :  5; //[31:27]
+             uint32_t phy_timestamp_1_lower_32        : 32; //[31:0]
+             uint32_t phy_timestamp_1_upper_32        : 32; //[31:0]
+             uint32_t phy_timestamp_2_lower_32        : 32; //[31:0]
+             uint32_t phy_timestamp_2_upper_32        : 32; //[31:0]
+    struct            rx_location_info                       rx_location_info_details;
+    struct            rx_timing_offset_info                       rx_timing_offset_info_details;
+    struct            receive_rssi_info                       post_rssi_info_details;
+             uint32_t phy_sw_status_31_0              : 32; //[31:0]
+             uint32_t phy_sw_status_63_32             : 32; //[31:0]
+};
+
+/*
+
+phy_internal_nap
+			
+			When set, PHY RX entered an internal NAP state, as PHY
+			determined that this reception was not destined to this
+			device
+
+location_info_valid
+			
+			Indicates that the RX_LOCATION_INFO structure later on
+			in the TLV contains valid info
+
+timing_info_valid
+			
+			Indicates that the RX_TIMING_OFFSET_INFO structure later
+			on in the TLV contains valid info
+
+rssi_info_valid
+			
+			Indicates that the RECEIVE_RSSI_INFO structure later on
+			in the TLV contains valid info
+
+rx_frame_correction_needed
+			
+			When clear, no action is needed in the MAC.
+			
+			
+			
+			When set, the falling edge of the rx_frame happened 4us
+			too late. MAC will need to compensate for this delay in
+			order to maintain proper SIFS timing and/or not to get
+			de-slotted.
+			
+			
+			
+			PHY uses this for very short 11a frames. 
+			
+			
+			
+			When set, PHY will have passed this TLV to the MAC up to
+			8 us into the 'real SIFS' time, and thus within 4us from the
+			falling edge of the rx_frame.
+			
+			
+			
+			<legal all>
+
+frameless_frame_received
+			
+			When set, PHY has received the 'frameless frame' . Can
+			be used in the 'MU-RTS -CTS exchange where CTS reception can
+			be problematic.
+			
+			<legal all>
+
+reserved_0a
+			
+			<legal 0>
+
+dl_ofdma_info_valid
+			
+			When set, the following DL_ofdma_... fields are valid.
+			
+			It provides the MAC insight into which RU was allocated
+			to this device. 
+			
+			<legal all>
+
+dl_ofdma_ru_start_index
+			
+			RU index number to which User is assigned
+			
+			RU numbering is over the entire BW, starting from 0 and
+			in increasing frequency order and not primary-secondary
+			order
+			
+			<legal 0-73>
+
+dl_ofdma_ru_width
+			
+			The size of the RU for this user.
+			
+			In units of 1 (26 tone) RU
+			
+			<legal 1-74>
+
+reserved_0b
+			
+			<legal 0>
+
+phy_timestamp_1_lower_32
+			
+			TODO PHY: cleanup descriptionThe PHY timestamp in the
+			AMPI of the first rising edge of rx_clear_pri after
+			TX_PHY_DESC. .  This field should set to 0 by the PHY and
+			should be updated by the AMPI before being forwarded to the
+			rest of the MAC. This field indicates the lower 32 bits of
+			the timestamp
+
+phy_timestamp_1_upper_32
+			
+			TODO PHY: cleanup description 
+			
+			The PHY timestamp in the AMPI of the first rising edge
+			of rx_clear_pri after TX_PHY_DESC.  This field should set to
+			0 by the PHY and should be updated by the AMPI before being
+			forwarded to the rest of the MAC. This field indicates the
+			upper 32 bits of the timestamp
+
+phy_timestamp_2_lower_32
+			
+			TODO PHY: cleanup description 
+			
+			The PHY timestamp in the AMPI of the rising edge of
+			rx_clear_pri after RX_RSSI_LEGACY.  This field should set to
+			0 by the PHY and should be updated by the AMPI before being
+			forwarded to the rest of the MAC. This field indicates the
+			lower 32 bits of the timestamp
+
+phy_timestamp_2_upper_32
+			
+			TODO PHY: cleanup description 
+			
+			The PHY timestamp in the AMPI of the rising edge of
+			rx_clear_pri after RX_RSSI_LEGACY.  This field should set to
+			0 by the PHY and should be updated by the AMPI before being
+			forwarded to the rest of the MAC. This field indicates the
+			upper 32 bits of the timestamp
+
+struct rx_location_info rx_location_info_details
+			
+			Overview of location related info 
+
+struct rx_timing_offset_info rx_timing_offset_info_details
+			
+			Overview of timing offset related info
+
+struct receive_rssi_info post_rssi_info_details
+			
+			Overview of the post-RSSI values. 
+
+phy_sw_status_31_0
+			
+			Some PHY micro code status that can be put in here.
+			Details of definition within SW specification
+			
+			This field can be used for debugging, FW - SW message
+			exchange, etc.
+			
+			It could for example be a pointer to a DDR memory
+			location where PHY FW put some debug info.
+			
+			<legal all>
+
+phy_sw_status_63_32
+			
+			Some PHY micro code status that can be put in here.
+			Details of definition within SW specification
+			
+			This field can be used for debugging, FW - SW message
+			exchange, etc.
+			
+			It could for example be a pointer to a DDR memory
+			location where PHY FW put some debug info.
+			
+			<legal all>
+*/
+
+
+/* Description		PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP
+			
+			When set, PHY RX entered an internal NAP state, as PHY
+			determined that this reception was not destined to this
+			device
+*/
+#define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_OFFSET                 0x00000000
+#define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_LSB                    0
+#define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_MASK                   0x00000001
+
+/* Description		PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID
+			
+			Indicates that the RX_LOCATION_INFO structure later on
+			in the TLV contains valid info
+*/
+#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET              0x00000000
+#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB                 1
+#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK                0x00000002
+
+/* Description		PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID
+			
+			Indicates that the RX_TIMING_OFFSET_INFO structure later
+			on in the TLV contains valid info
+*/
+#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET                0x00000000
+#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB                   2
+#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK                  0x00000004
+
+/* Description		PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID
+			
+			Indicates that the RECEIVE_RSSI_INFO structure later on
+			in the TLV contains valid info
+*/
+#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET                  0x00000000
+#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB                     3
+#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK                    0x00000008
+
+/* Description		PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED
+			
+			When clear, no action is needed in the MAC.
+			
+			
+			
+			When set, the falling edge of the rx_frame happened 4us
+			too late. MAC will need to compensate for this delay in
+			order to maintain proper SIFS timing and/or not to get
+			de-slotted.
+			
+			
+			
+			PHY uses this for very short 11a frames. 
+			
+			
+			
+			When set, PHY will have passed this TLV to the MAC up to
+			8 us into the 'real SIFS' time, and thus within 4us from the
+			falling edge of the rx_frame.
+			
+			
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET       0x00000000
+#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB          4
+#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK         0x00000010
+
+/* Description		PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED
+			
+			When set, PHY has received the 'frameless frame' . Can
+			be used in the 'MU-RTS -CTS exchange where CTS reception can
+			be problematic.
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET         0x00000000
+#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB            5
+#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK           0x00000020
+
+/* Description		PHYRX_PKT_END_INFO_0_RESERVED_0A
+			
+			<legal 0>
+*/
+#define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET                      0x00000000
+#define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB                         6
+#define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK                        0x00000fc0
+
+/* Description		PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID
+			
+			When set, the following DL_ofdma_... fields are valid.
+			
+			It provides the MAC insight into which RU was allocated
+			to this device. 
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_OFFSET              0x00000000
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_LSB                 12
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_MASK                0x00001000
+
+/* Description		PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX
+			
+			RU index number to which User is assigned
+			
+			RU numbering is over the entire BW, starting from 0 and
+			in increasing frequency order and not primary-secondary
+			order
+			
+			<legal 0-73>
+*/
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_OFFSET          0x00000000
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_LSB             13
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_MASK            0x000fe000
+
+/* Description		PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH
+			
+			The size of the RU for this user.
+			
+			In units of 1 (26 tone) RU
+			
+			<legal 1-74>
+*/
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_OFFSET                0x00000000
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_LSB                   20
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_MASK                  0x07f00000
+
+/* Description		PHYRX_PKT_END_INFO_0_RESERVED_0B
+			
+			<legal 0>
+*/
+#define PHYRX_PKT_END_INFO_0_RESERVED_0B_OFFSET                      0x00000000
+#define PHYRX_PKT_END_INFO_0_RESERVED_0B_LSB                         27
+#define PHYRX_PKT_END_INFO_0_RESERVED_0B_MASK                        0xf8000000
+
+/* Description		PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32
+			
+			TODO PHY: cleanup descriptionThe PHY timestamp in the
+			AMPI of the first rising edge of rx_clear_pri after
+			TX_PHY_DESC. .  This field should set to 0 by the PHY and
+			should be updated by the AMPI before being forwarded to the
+			rest of the MAC. This field indicates the lower 32 bits of
+			the timestamp
+*/
+#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET         0x00000004
+#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB            0
+#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK           0xffffffff
+
+/* Description		PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32
+			
+			TODO PHY: cleanup description 
+			
+			The PHY timestamp in the AMPI of the first rising edge
+			of rx_clear_pri after TX_PHY_DESC.  This field should set to
+			0 by the PHY and should be updated by the AMPI before being
+			forwarded to the rest of the MAC. This field indicates the
+			upper 32 bits of the timestamp
+*/
+#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET         0x00000008
+#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB            0
+#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK           0xffffffff
+
+/* Description		PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32
+			
+			TODO PHY: cleanup description 
+			
+			The PHY timestamp in the AMPI of the rising edge of
+			rx_clear_pri after RX_RSSI_LEGACY.  This field should set to
+			0 by the PHY and should be updated by the AMPI before being
+			forwarded to the rest of the MAC. This field indicates the
+			lower 32 bits of the timestamp
+*/
+#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET         0x0000000c
+#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB            0
+#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK           0xffffffff
+
+/* Description		PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32
+			
+			TODO PHY: cleanup description 
+			
+			The PHY timestamp in the AMPI of the rising edge of
+			rx_clear_pri after RX_RSSI_LEGACY.  This field should set to
+			0 by the PHY and should be updated by the AMPI before being
+			forwarded to the rest of the MAC. This field indicates the
+			upper 32 bits of the timestamp
+*/
+#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET         0x00000010
+#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB            0
+#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK           0xffffffff
+
+ /* EXTERNAL REFERENCE : struct rx_location_info rx_location_info_details */ 
+
+
+/* Description		PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY
+			
+			For 20/40/80, this field shows the RTT first arrival
+			correction value computed from L-LTF on the first selected
+			Rx chain
+			
+			
+			
+			For 80+80, this field shows the RTT first arrival
+			correction value computed from L-LTF on pri80 on the
+			selected pri80 Rx chain
+			
+			
+			
+			16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+			6.4us, and 4 bits fraction to cover pri80 and 32x FAC
+			interpolation
+			
+			
+			
+			clock unit is 320MHz
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff
+
+/* Description		PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80
+			
+			For 20/40/80, this field shows the RTT first arrival
+			correction value computed from L-LTF on the second selected
+			Rx chain
+			
+			
+			
+			For 80+80, this field shows the RTT first arrival
+			correction value computed from L-LTF on ext80 on the
+			selected ext80 Rx chain
+			
+			
+			
+			16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+			6.4us, and 4 bits fraction to cover ext80 and 32x FAC
+			interpolation
+			
+			
+			
+			clock unit is 320MHz
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000
+
+/* Description		PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT
+			
+			For 20/40/80, this field shows the RTT first arrival
+			correction value computed from (V)HT/HE-LTF on the first
+			selected Rx chain
+			
+			
+			
+			For 80+80, this field shows the RTT first arrival
+			correction value computed from (V)HT/HE-LTF on pri80 on the
+			selected pri80 Rx chain
+			
+			
+			
+			16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+			6.4us, and 4 bits fraction to cover pri80 and 32x FAC
+			interpolation
+			
+			
+			
+			clock unit is 320MHz
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff
+
+/* Description		PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80
+			
+			For 20/40/80, this field shows the RTT first arrival
+			correction value computed from (V)HT/HE-LTF on the second
+			selected Rx chain
+			
+			
+			
+			For 80+80, this field shows the RTT first arrival
+			correction value computed from (V)HT/HE-LTF on ext80 on the
+			selected ext80 Rx chain
+			
+			
+			
+			16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+			6.4us, and 4 bits fraction to cover ext80 and 32x FAC
+			interpolation
+			
+			
+			
+			clock unit is 320MHz
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000
+
+/* Description		PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS
+			
+			Status of rtt_fac_legacy
+			
+			
+			
+			<enum 0 location_fac_legacy_status_not_valid>
+			
+			<enum 1 location_fac_legacy_status_valid>
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001
+
+/* Description		PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS
+			
+			Status of rtt_fac_legacy_ext80
+			
+			
+			
+			<enum 0 location_fac_legacy_ext80_status_not_valid>
+			
+			<enum 1 location_fac_legacy_ext80_status_valid>
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002
+
+/* Description		PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS
+			
+			Status of rtt_fac_vht
+			
+			
+			
+			<enum 0 location_fac_vht_status_not_valid>
+			
+			<enum 1 location_fac_vht_status_valid>
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004
+
+/* Description		PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS
+			
+			Status of rtt_fac_vht_ext80
+			
+			
+			
+			<enum 0 location_fac_vht_ext80_status_not_valid>
+			
+			<enum 1 location_fac_vht_ext80_status_valid>
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008
+
+/* Description		PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS
+			
+			To support fine SIFS adjustment, need to provide FAC
+			value @ integer number of 320 MHz clock cycles to MAC.  It
+			is from L-LTF if it is a Legacy packet and from (V)HT/HE-LTF
+			if it is a (V)HT/HE packet
+			
+			
+			
+			12 bits, signed, no fractional part
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0
+
+/* Description		PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS
+			
+			Status of rtt_fac_sifs
+			
+			0: not valid
+			
+			1: valid and from L-LTF
+			
+			2: valid and from (V)HT/HE-LTF
+			
+			3: reserved
+			
+			<legal 0-2>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000
+
+/* Description		PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS
+			
+			Status of channel frequency response dump
+			
+			
+			
+			<enum 0 location_CFR_dump_not_valid>
+			
+			<enum 1 location_CFR_dump_valid>
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000
+
+/* Description		PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS
+			
+			Status of channel impulse response dump
+			
+			
+			
+			<enum 0 location_CIR_dump_not_valid>
+			
+			<enum 1 location_CIR_dump_valid>
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000
+
+/* Description		PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE
+			
+			Channel dump size.  It shows how many tones in CFR in
+			one chain, for example, it will show 52 for Legacy20 and 484
+			for VHT160
+			
+			
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000
+
+/* Description		PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE
+			
+			Indicator showing if HW IFFT mode or SW IFFT mode
+			
+			
+			
+			<enum 0 location_sw_ifft_mode>
+			
+			<enum 1 location_hw_ifft_mode>
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000
+
+/* Description		PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS
+			
+			Indicate if BTCF is used to capture the timestamps
+			
+			
+			
+			<enum 0 location_not_BTCF_based_ts>
+			
+			<enum 1 location_BTCF_based_ts>
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001
+
+/* Description		PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE
+			
+			Indicate preamble type
+			
+			
+			
+			<enum 0 location_preamble_type_legacy>
+			
+			<enum 1 location_preamble_type_ht>
+			
+			<enum 2 location_preamble_type_vht>
+			
+			<enum 3 location_preamble_type_he_su_4xltf>
+			
+			<enum 4 location_preamble_type_he_su_2xltf>
+			
+			<enum 5 location_preamble_type_he_su_1xltf>
+			
+			<enum 6
+			location_preamble_type_he_trigger_based_ul_4xltf>
+			
+			<enum 7
+			location_preamble_type_he_trigger_based_ul_2xltf>
+			
+			<enum 8
+			location_preamble_type_he_trigger_based_ul_1xltf>
+			
+			<enum 9 location_preamble_type_he_mu_4xltf>
+			
+			<enum 10 location_preamble_type_he_mu_2xltf>
+			
+			<enum 11 location_preamble_type_he_mu_1xltf>
+			
+			<enum 12
+			location_preamble_type_he_extended_range_su_4xltf>
+			
+			<enum 13
+			location_preamble_type_he_extended_range_su_2xltf>
+			
+			<enum 14
+			location_preamble_type_he_extended_range_su_1xltf>
+			
+			<legal 0-14>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e
+
+/* Description		PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG
+			
+			Indicate the bandwidth of L-LTF
+			
+			
+			
+			<enum 0 location_pkt_bw_20MHz>
+			
+			<enum 1 location_pkt_bw_40MHz>
+			
+			<enum 2 location_pkt_bw_80MHz>
+			
+			<enum 3 location_pkt_bw_160MHz>
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0
+
+/* Description		PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT
+			
+			Indicate the bandwidth of (V)HT/HE-LTF
+			
+			
+			
+			<enum 0 location_pkt_bw_20MHz>
+			
+			<enum 1 location_pkt_bw_40MHz>
+			
+			<enum 2 location_pkt_bw_80MHz>
+			
+			<enum 3 location_pkt_bw_160MHz>
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300
+
+/* Description		PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE
+			
+			Indicate GI (guard interval) type
+			
+			
+			
+			<enum 0     gi_0_8_us > HE related GI. Can also be used
+			for HE
+			
+			<enum 1     gi_0_4_us > HE related GI. Can also be used
+			for HE
+			
+			<enum 2     gi_1_6_us > HE related GI
+			
+			<enum 3     gi_3_2_us > HE related GI
+			
+			<legal 0 - 3>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00
+
+/* Description		PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE
+			
+			Bits 0~4 indicate MCS rate, if Legacy, 
+			
+			0: 48 Mbps,
+			
+			1: 24 Mbps,
+			
+			2: 12 Mbps,
+			
+			3: 6 Mbps,
+			
+			4: 54 Mbps,
+			
+			5: 36 Mbps,
+			
+			6: 18 Mbps,
+			
+			7: 9 Mbps,
+			
+			
+			
+			if HT, 0-7: MCS0-MCS7, 
+			
+			if VHT, 0-9: MCS0-MCS9, 
+			
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000
+
+/* Description		PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN
+			
+			For 20/40/80, this field shows the first selected Rx
+			chain that is used in HW IFFT mode
+			
+			
+			
+			For 80+80, this field shows the selected pri80 Rx chain
+			that is used in HW IFFT mode
+			
+			
+			
+			<enum 0 location_strongest_chain_is_0>
+			
+			<enum 1 location_strongest_chain_is_1>
+			
+			<enum 2 location_strongest_chain_is_2>
+			
+			<enum 3 location_strongest_chain_is_3>
+			
+			<enum 4 location_strongest_chain_is_4>
+			
+			<enum 5 location_strongest_chain_is_5>
+			
+			<enum 6 location_strongest_chain_is_6>
+			
+			<enum 7 location_strongest_chain_is_7>
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000
+
+/* Description		PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80
+			
+			For 20/40/80, this field shows the second selected Rx
+			chain that is used in HW IFFT mode
+			
+			
+			
+			For 80+80, this field shows the selected ext80 Rx chain
+			that is used in HW IFFT mode
+			
+			
+			
+			<enum 0 location_strongest_chain_is_0>
+			
+			<enum 1 location_strongest_chain_is_1>
+			
+			<enum 2 location_strongest_chain_is_2>
+			
+			<enum 3 location_strongest_chain_is_3>
+			
+			<enum 4 location_strongest_chain_is_4>
+			
+			<enum 5 location_strongest_chain_is_5>
+			
+			<enum 6 location_strongest_chain_is_6>
+			
+			<enum 7 location_strongest_chain_is_7>
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000
+
+/* Description		PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK
+			
+			Rx chain mask, each bit is a Rx chain
+			
+			0: the Rx chain is not used
+			
+			1: the Rx chain is used
+			
+			Support up to 8 Rx chains
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000
+
+/* Description		PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3
+			
+			<legal 0>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000
+
+/* Description		PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS
+			
+			RX packet start timestamp
+			
+			
+			
+			It reports the time the first L-STF ADC sample arrived
+			at RX antenna
+			
+			
+			
+			clock unit is 480MHz
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024
+#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0
+#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff
+
+/* Description		PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS
+			
+			RX packet end timestamp
+			
+			
+			
+			It reports the time the last symbol's last ADC sample
+			arrived at RX antenna
+			
+			
+			
+			clock unit is 480MHz
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028
+#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0
+#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff
+
+/* Description		PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START
+			
+			The phase of the SFO of the first symbol's first FFT
+			input sample
+			
+			
+			
+			12 bits, signed 6.6. 6 bits integer to cover -66.7ns to
+			66.7ns, and 6 bits fraction to provide a resolution of
+			0.03ns
+			
+			
+			
+			clock unit is 480MHz
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff
+
+/* Description		PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END
+			
+			The phase of the SFO of the last symbol's last FFT input
+			sample
+			
+			
+			
+			12 bits, signed 6.6. 6 bits integer to cover -66.7ns to
+			66.7ns, and 6 bits fraction to provide a resolution of
+			0.03ns
+			
+			
+			
+			clock unit is 480MHz
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000
+
+/* Description		PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8
+			
+			The high 8 bits of the 40 bits pointer pointed to the
+			external RTT channel information buffer
+			
+			
+			
+			8 bits
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32
+			
+			The low 32 bits of the 40 bits pointer pointed to the
+			external RTT channel information buffer
+			
+			
+			
+			32 bits
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030
+#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
+#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff
+
+/* Description		PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT
+			
+			CFO measurement. Needed for passive locationing
+			
+			
+			
+			14 bits, signed 1.13. 13 bits fraction to provide a
+			resolution of 153 Hz
+			
+			
+			
+			In units of cycles/800 ns
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff
+
+/* Description		PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD
+			
+			Channel delay spread measurement. Needed for selecting
+			GI length
+			
+			
+			
+			8 bits, unsigned. At 25 ns step. Can represent up to
+			6375 ns
+			
+			
+			
+			In units of cycles @ 40 MHz
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000
+
+/* Description		PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL
+			
+			Indicate which timing backoff value is used
+			
+			
+			
+			<enum 0 timing_backoff_low_rssi>
+			
+			<enum 1 timing_backoff_mid_rssi>
+			
+			<enum 2 timing_backoff_high_rssi>
+			
+			<enum 3 reserved>
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000
+
+/* Description		PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8
+			
+			<legal 0>
+*/
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000
+
+/* Description		PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID
+			
+			<enum 0 rx_location_info_is_not_valid>
+			
+			<enum 1 rx_location_info_is_valid>
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000
+
+ /* EXTERNAL REFERENCE : struct rx_timing_offset_info rx_timing_offset_info_details */ 
+
+
+/* Description		PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET
+			
+			Cumulative reference frequency error at end of RX
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
+
+/* Description		PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED
+			
+			<legal 0>
+*/
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000
+
+ /* EXTERNAL REFERENCE : struct receive_rssi_info post_rssi_info_details */ 
+
+
+/* Description		PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0
+			
+			RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0
+			
+			RSSI of RX PPDU on chain 0 of extension 20 MHz
+			bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0
+			
+			RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0
+			
+			RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0
+			
+			RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0
+			
+			RSSI of RX PPDU on chain 0 of extension 80, low-high 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0
+			
+			RSSI of RX PPDU on chain 0 of extension 80, high-low 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0
+			
+			RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1
+			
+			RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1
+			
+			RSSI of RX PPDU on chain 1 of extension 20 MHz
+			bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1
+			
+			RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1
+			
+			RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1
+			
+			RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1
+			
+			RSSI of RX PPDU on chain 1 of extension 80, low-high 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1
+			
+			RSSI of RX PPDU on chain 1 of extension 80, high-low 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1
+			
+			RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2
+			
+			RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2
+			
+			RSSI of RX PPDU on chain 2 of extension 20 MHz
+			bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2
+			
+			RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2
+			
+			RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2
+			
+			RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2
+			
+			RSSI of RX PPDU on chain 2 of extension 80, low-high 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2
+			
+			RSSI of RX PPDU on chain 2 of extension 80, high-low 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2
+			
+			RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3
+			
+			RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3
+			
+			RSSI of RX PPDU on chain 3 of extension 20 MHz
+			bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3
+			
+			RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3
+			
+			RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3
+			
+			RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3
+			
+			RSSI of RX PPDU on chain 3 of extension 80, low-high 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3
+			
+			RSSI of RX PPDU on chain 3 of extension 80, high-low 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3
+			
+			RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4
+			
+			RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4
+			
+			RSSI of RX PPDU on chain 4 of extension 20 MHz
+			bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4
+			
+			RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4
+			
+			RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4
+			
+			RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4
+			
+			RSSI of RX PPDU on chain 4 of extension 80, low-high 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4
+			
+			RSSI of RX PPDU on chain 4 of extension 80, high-low 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4
+			
+			RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5
+			
+			RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5
+			
+			RSSI of RX PPDU on chain 5 of extension 20 MHz
+			bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5
+			
+			RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5
+			
+			RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5
+			
+			RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5
+			
+			RSSI of RX PPDU on chain 5 of extension 80, low-high 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5
+			
+			RSSI of RX PPDU on chain 5 of extension 80, high-low 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5
+			
+			RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6
+			
+			RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6
+			
+			RSSI of RX PPDU on chain 6 of extension 20 MHz
+			bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6
+			
+			RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6
+			
+			RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6
+			
+			RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6
+			
+			RSSI of RX PPDU on chain 6 of extension 80, low-high 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6
+			
+			RSSI of RX PPDU on chain 6 of extension 80, high-low 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6
+			
+			RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7
+			
+			RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7
+			
+			RSSI of RX PPDU on chain 7 of extension 20 MHz
+			bandwidth. 
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7
+			
+			RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7
+			
+			RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7
+			
+			RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+/* Description		PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7
+			
+			RSSI of RX PPDU on chain 7 of extension 80, low-high 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+/* Description		PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7
+			
+			RSSI of RX PPDU on chain 7 of extension 80, high-low 20
+			MHz bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+/* Description		PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7
+			
+			RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz
+			bandwidth.  
+			
+			Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+/* Description		PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0
+			
+			Some PHY micro code status that can be put in here.
+			Details of definition within SW specification
+			
+			This field can be used for debugging, FW - SW message
+			exchange, etc.
+			
+			It could for example be a pointer to a DDR memory
+			location where PHY FW put some debug info.
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET              0x0000007c
+#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB                 0
+#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK                0xffffffff
+
+/* Description		PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32
+			
+			Some PHY micro code status that can be put in here.
+			Details of definition within SW specification
+			
+			This field can be used for debugging, FW - SW message
+			exchange, etc.
+			
+			It could for example be a pointer to a DDR memory
+			location where PHY FW put some debug info.
+			
+			<legal all>
+*/
+#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET             0x00000080
+#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB                0
+#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK               0xffffffff
+
+
+#endif // _PHYRX_PKT_END_INFO_H_

hw/qca8074/v2/reo_entrance_ring.h

@@ -0,0 +1,1181 @@
+/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_ENTRANCE_RING_H_
+#define _REO_ENTRANCE_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_mpdu_details.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-3	struct rx_mpdu_details reo_level_mpdu_frame_info;
+//	4	rx_reo_queue_desc_addr_31_0[31:0]
+//	5	rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28]
+//	6	rxdma_push_reason[1:0], rxdma_error_code[6:2], mpdu_fragment_number[10:7], reserved_6a[31:11]
+//	7	reserved_7a[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
+
+struct reo_entrance_ring {
+    struct            rx_mpdu_details                       reo_level_mpdu_frame_info;
+             uint32_t rx_reo_queue_desc_addr_31_0     : 32; //[31:0]
+             uint32_t rx_reo_queue_desc_addr_39_32    :  8, //[7:0]
+                      rounded_mpdu_byte_count         : 14, //[21:8]
+                      reo_destination_indication      :  5, //[26:22]
+                      frameless_bar                   :  1, //[27]
+                      reserved_5a                     :  4; //[31:28]
+             uint32_t rxdma_push_reason               :  2, //[1:0]
+                      rxdma_error_code                :  5, //[6:2]
+                      mpdu_fragment_number            :  4, //[10:7]
+                      reserved_6a                     : 21; //[31:11]
+             uint32_t reserved_7a                     : 20, //[19:0]
+                      ring_id                         :  8, //[27:20]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct rx_mpdu_details reo_level_mpdu_frame_info
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Details related to the MPDU being pushed into the REO
+
+rx_reo_queue_desc_addr_31_0
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor. 
+			
+			<legal all>
+
+rx_reo_queue_desc_addr_39_32
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor. 
+			
+			<legal all>
+
+rounded_mpdu_byte_count
+			
+			An approximation of the number of bytes received in this
+			MPDU. 
+			
+			Used to keeps stats on the amount of data flowing
+			through a queue.
+			
+			<legal all>
+
+reo_destination_indication
+			
+			RXDMA copy the MPDU's first MSDU's destination
+			indication field here. This is used for REO to be able to
+			re-route the packet to a different SW destination ring if
+			the packet is detected as error in REO.
+			
+			
+			
+			The ID of the REO exit ring where the MSDU frame shall
+			push after (MPDU level) reordering has finished.
+			
+			
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_7> REO remaps this
+			
+			<enum 8 reo_destination_8> REO remaps this <enum 9
+			reo_destination_9> REO remaps this <enum 10
+			reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			<legal all>
+
+frameless_bar
+			
+			When set, this REO entrance ring struct contains BAR
+			info from a multi TID BAR frame. The original multi TID BAR
+			frame itself contained all the REO info for the first TID,
+			but all the subsequent TID info and their linkage to the REO
+			descriptors is passed down as 'frameless' BAR info.
+			
+			
+			
+			The only fields valid in this descriptor when this bit
+			is set are:
+			
+			Rx_reo_queue_desc_addr_31_0
+			
+			RX_reo_queue_desc_addr_39_32
+			
+			
+			
+			And within the
+			
+			Reo_level_mpdu_frame_info:    
+			
+			   Within Rx_mpdu_desc_info_details:
+			
+			Mpdu_Sequence_number
+			
+			BAR_frame
+			
+			Peer_meta_data
+			
+			All other fields shall be set to 0
+			
+			
+			
+			<legal all>
+
+reserved_5a
+			
+			<legal 0>
+
+rxdma_push_reason
+			
+			Indicates why rxdma pushed the frame to this ring
+			
+			
+			
+			This field is ignored by REO. 
+			
+			
+			
+			<enum 0 rxdma_error_detected> RXDMA detected an error an
+			pushed this frame to this queue
+			
+			<enum 1 rxdma_routing_instruction> RXDMA pushed the
+			frame to this queue per received routing instructions. No
+			error within RXDMA was detected
+			
+			<enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
+			result the MSDU link descriptor might not have the
+			last_msdu_in_mpdu_flag set, but instead WBM might just see a
+			NULL pointer in the MSDU link descriptor. This is to be
+			considered a normal condition for this scenario.
+			
+			
+			
+			<legal 0 - 2>
+
+rxdma_error_code
+			
+			Field only valid when 'rxdma_push_reason' set to
+			'rxdma_error_detected'.
+			
+			
+			
+			This field is ignored by REO.
+			
+			
+			
+			<enum 0 rxdma_overflow_err>MPDU frame is not complete
+			due to a FIFO overflow error in RXPCU.
+			
+			<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
+			due to receiving incomplete MPDU from the PHY
+			
+			
+			<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
+			error or CRYPTO received an encrypted frame, but did not get
+			a valid corresponding key id in the peer entry.
+			
+			<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
+			error
+			
+			<enum 5 rxdma_unecrypted_err>CRYPTO reported an
+			unencrypted frame error when encrypted was expected
+			
+			<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
+			length error
+			
+			<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
+			number of MSDUs allowed in an MPDU got exceeded
+			
+			<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
+			error
+			
+			<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
+			parsing error
+			
+			<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
+			during SA search
+			
+			<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
+			during DA search
+			
+			<enum 12 rxdma_flow_timeout_err>RX OLE reported a
+			timeout during flow search
+			
+			<enum 13 Rxdma_flush_request>RXDMA received a flush
+			request
+
+mpdu_fragment_number
+			
+			Field only valid when Reo_level_mpdu_frame_info.
+			
+			Rx_mpdu_desc_info_details.
+			
+			Fragment_flag  is set.
+			
+			
+			
+			The fragment number from the 802.11 header.
+			
+			
+			
+			Note that the sequence number is embedded in field:
+			Reo_level_mpdu_frame_info.
+			
+			Rx_mpdu_desc_info_details.
+			
+			Mpdu_Sequence_number
+			
+			
+			
+			<legal all>
+
+reserved_6a
+			
+			<legal 0>
+
+reserved_7a
+			
+			<legal 0>
+
+ring_id
+			
+			Consumer: SW/REO/DEBUG
+			
+			Producer: SRNG (of RXDMA)
+			
+			
+			
+			For debugging. 
+			
+			This field is filled in by the SRNG module.
+			
+			It help to identify the ring that is being looked <legal
+			all>
+
+looping_count
+			
+			Consumer: SW/REO/DEBUG
+			
+			Producer: SRNG (of RXDMA)
+			
+			
+			
+			For debugging. 
+			
+			This field is filled in by the SRNG module.
+			
+			
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_details reo_level_mpdu_frame_info */ 
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */ 
+
+
+/* Description		REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+			
+			Address (lower 32 bits) of the MSDU buffer OR
+			MSDU_EXTENSION descriptor OR Link Descriptor
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description		REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+			
+			Address (upper 8 bits) of the MSDU buffer OR
+			MSDU_EXTENSION descriptor OR Link Descriptor
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description		REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+			
+			Consumer: WBM
+			
+			Producer: SW/FW
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			
+			
+			Indicates to which buffer manager the buffer OR
+			MSDU_EXTENSION descriptor OR link descriptor that is being
+			pointed to shall be returned after the frame has been
+			processed. It is used by WBM for routing purposes.
+			
+			
+			
+			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+			to the WMB buffer idle list
+			
+			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+			returned to the WMB idle link descriptor idle list
+			
+			<enum 2 FW_BM> This buffer shall be returned to the FW
+			
+			<enum 3 SW0_BM> This buffer shall be returned to the SW,
+			ring 0
+			
+			<enum 4 SW1_BM> This buffer shall be returned to the SW,
+			ring 1
+			
+			<enum 5 SW2_BM> This buffer shall be returned to the SW,
+			ring 2
+			
+			<enum 6 SW3_BM> This buffer shall be returned to the SW,
+			ring 3
+			
+			<enum 7 SW4_BM> This buffer shall be returned to the SW,
+			ring 3
+			
+			
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description		REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+			
+			Cookie field exclusively used by SW. 
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			
+			
+			HW ignores the contents, accept that it passes the
+			programmed value on to other descriptors together with the
+			physical address 
+			
+			
+			
+			Field can be used by SW to for example associate the
+			buffers physical address with the virtual address
+			
+			The bit definitions as used by SW are within SW HLD
+			specification
+			
+			
+			
+			NOTE:
+			
+			The three most significant bits can have a special
+			meaning in case this struct is embedded in a TX_MPDU_DETAILS
+			STRUCT, and field transmit_bw_restriction is set
+			
+			
+			
+			In case of NON punctured transmission:
+			
+			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+			
+			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+			
+			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+			
+			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+			
+			
+			
+			In case of punctured transmission:
+			
+			Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+			
+			Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+			
+			Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+			
+			Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+			
+			Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+			
+			Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+			
+			Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+			
+			Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+			
+			
+			
+			Note: a punctured transmission is indicated by the
+			presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+			TLV
+			
+			
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ 
+
+
+/* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			The number of MSDUs within the MPDU 
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+/* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			The field can have two different meanings based on the
+			setting of field 'BAR_frame':
+			
+			
+			
+			'BAR_frame' is NOT set:
+			
+			The MPDU sequence number of the received frame.
+			
+			
+			
+			'BAR_frame' is set.
+			
+			The MPDU Start sequence number from the BAR frame
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
+
+/* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			When set, this MPDU is a fragment and REO should forward
+			this fragment MPDU to the REO destination ring without any
+			reorder checks, pn checks or bitmap update. This implies
+			that REO is forwarding the pointer to the MSDU link
+			descriptor. The destination ring is coming from a
+			programmable register setting in REO
+			
+			
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
+
+/* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			The retry bit setting from the MPDU header of the
+			received frame
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
+
+/* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			When set, the MPDU was received as part of an A-MPDU.
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000
+
+/* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			When set, the received frame is a BAR frame. After
+			processing, this frame shall be pushed to SW or deleted.
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000
+
+/* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			Copied here by RXDMA from RX_MPDU_END
+			
+			When not set, REO will Not perform a PN sequence number
+			check
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
+
+/* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID
+			
+			When set, OLE found a valid SA entry for all MSDUs in
+			this MPDU
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
+
+/* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
+			
+			When set, at least 1 MSDU within the MPDU has an
+			unsuccessful MAC source address search due to the expiration
+			of the search timer.
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
+
+/* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID
+			
+			When set, OLE found a valid DA entry for all MSDUs in
+			this MPDU
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
+
+/* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC
+			
+			Field Only valid if da_is_valid is set
+			
+			
+			
+			When set, at least one of the DA addresses is a
+			Multicast or Broadcast address.
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000
+
+/* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
+			
+			When set, at least 1 MSDU within the MPDU has an
+			unsuccessful MAC destination address search due to the
+			expiration of the search timer.
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
+
+/* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU
+			
+			Field only valid when first_msdu_in_mpdu_flag is set.
+			
+			
+			
+			When set, the contents in the MSDU buffer contains a
+			'RAW' MPDU. This 'RAW' MPDU might be spread out over
+			multiple MSDU buffers.
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
+
+/* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG
+			
+			The More Fragment bit setting from the MPDU header of
+			the received frame
+			
+			
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
+
+/* Description		REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA
+			
+			Meta data that SW has programmed in the Peer table entry
+			of the transmitting STA.
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+/* Description		REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor. 
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET       0x00000010
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB          0
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK         0xffffffff
+
+/* Description		REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor. 
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET      0x00000014
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB         0
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK        0x000000ff
+
+/* Description		REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT
+			
+			An approximation of the number of bytes received in this
+			MPDU. 
+			
+			Used to keeps stats on the amount of data flowing
+			through a queue.
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET           0x00000014
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB              8
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK             0x003fff00
+
+/* Description		REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION
+			
+			RXDMA copy the MPDU's first MSDU's destination
+			indication field here. This is used for REO to be able to
+			re-route the packet to a different SW destination ring if
+			the packet is detected as error in REO.
+			
+			
+			
+			The ID of the REO exit ring where the MSDU frame shall
+			push after (MPDU level) reordering has finished.
+			
+			
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_7> REO remaps this
+			
+			<enum 8 reo_destination_8> REO remaps this <enum 9
+			reo_destination_9> REO remaps this <enum 10
+			reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET        0x00000014
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB           22
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK          0x07c00000
+
+/* Description		REO_ENTRANCE_RING_5_FRAMELESS_BAR
+			
+			When set, this REO entrance ring struct contains BAR
+			info from a multi TID BAR frame. The original multi TID BAR
+			frame itself contained all the REO info for the first TID,
+			but all the subsequent TID info and their linkage to the REO
+			descriptors is passed down as 'frameless' BAR info.
+			
+			
+			
+			The only fields valid in this descriptor when this bit
+			is set are:
+			
+			Rx_reo_queue_desc_addr_31_0
+			
+			RX_reo_queue_desc_addr_39_32
+			
+			
+			
+			And within the
+			
+			Reo_level_mpdu_frame_info:    
+			
+			   Within Rx_mpdu_desc_info_details:
+			
+			Mpdu_Sequence_number
+			
+			BAR_frame
+			
+			Peer_meta_data
+			
+			All other fields shall be set to 0
+			
+			
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET                     0x00000014
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB                        27
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK                       0x08000000
+
+/* Description		REO_ENTRANCE_RING_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET                       0x00000014
+#define REO_ENTRANCE_RING_5_RESERVED_5A_LSB                          28
+#define REO_ENTRANCE_RING_5_RESERVED_5A_MASK                         0xf0000000
+
+/* Description		REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON
+			
+			Indicates why rxdma pushed the frame to this ring
+			
+			
+			
+			This field is ignored by REO. 
+			
+			
+			
+			<enum 0 rxdma_error_detected> RXDMA detected an error an
+			pushed this frame to this queue
+			
+			<enum 1 rxdma_routing_instruction> RXDMA pushed the
+			frame to this queue per received routing instructions. No
+			error within RXDMA was detected
+			
+			<enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
+			result the MSDU link descriptor might not have the
+			last_msdu_in_mpdu_flag set, but instead WBM might just see a
+			NULL pointer in the MSDU link descriptor. This is to be
+			considered a normal condition for this scenario.
+			
+			
+			
+			<legal 0 - 2>
+*/
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET                 0x00000018
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB                    0
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK                   0x00000003
+
+/* Description		REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE
+			
+			Field only valid when 'rxdma_push_reason' set to
+			'rxdma_error_detected'.
+			
+			
+			
+			This field is ignored by REO.
+			
+			
+			
+			<enum 0 rxdma_overflow_err>MPDU frame is not complete
+			due to a FIFO overflow error in RXPCU.
+			
+			<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
+			due to receiving incomplete MPDU from the PHY
+			
+			
+			<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
+			error or CRYPTO received an encrypted frame, but did not get
+			a valid corresponding key id in the peer entry.
+			
+			<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
+			error
+			
+			<enum 5 rxdma_unecrypted_err>CRYPTO reported an
+			unencrypted frame error when encrypted was expected
+			
+			<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
+			length error
+			
+			<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
+			number of MSDUs allowed in an MPDU got exceeded
+			
+			<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
+			error
+			
+			<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
+			parsing error
+			
+			<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
+			during SA search
+			
+			<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
+			during DA search
+			
+			<enum 12 rxdma_flow_timeout_err>RX OLE reported a
+			timeout during flow search
+			
+			<enum 13 Rxdma_flush_request>RXDMA received a flush
+			request
+*/
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET                  0x00000018
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB                     2
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK                    0x0000007c
+
+/* Description		REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER
+			
+			Field only valid when Reo_level_mpdu_frame_info.
+			
+			Rx_mpdu_desc_info_details.
+			
+			Fragment_flag  is set.
+			
+			
+			
+			The fragment number from the 802.11 header.
+			
+			
+			
+			Note that the sequence number is embedded in field:
+			Reo_level_mpdu_frame_info.
+			
+			Rx_mpdu_desc_info_details.
+			
+			Mpdu_Sequence_number
+			
+			
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET              0x00000018
+#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB                 7
+#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK                0x00000780
+
+/* Description		REO_ENTRANCE_RING_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET                       0x00000018
+#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB                          11
+#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK                         0xfffff800
+
+/* Description		REO_ENTRANCE_RING_7_RESERVED_7A
+			
+			<legal 0>
+*/
+#define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET                       0x0000001c
+#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB                          0
+#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK                         0x000fffff
+
+/* Description		REO_ENTRANCE_RING_7_RING_ID
+			
+			Consumer: SW/REO/DEBUG
+			
+			Producer: SRNG (of RXDMA)
+			
+			
+			
+			For debugging. 
+			
+			This field is filled in by the SRNG module.
+			
+			It help to identify the ring that is being looked <legal
+			all>
+*/
+#define REO_ENTRANCE_RING_7_RING_ID_OFFSET                           0x0000001c
+#define REO_ENTRANCE_RING_7_RING_ID_LSB                              20
+#define REO_ENTRANCE_RING_7_RING_ID_MASK                             0x0ff00000
+
+/* Description		REO_ENTRANCE_RING_7_LOOPING_COUNT
+			
+			Consumer: SW/REO/DEBUG
+			
+			Producer: SRNG (of RXDMA)
+			
+			
+			
+			For debugging. 
+			
+			This field is filled in by the SRNG module.
+			
+			
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET                     0x0000001c
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB                        28
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK                       0xf0000000
+
+
+#endif // _REO_ENTRANCE_RING_H_

hw/qca8074/v2/wcss_version.h

@@ -0,0 +1,16 @@
+/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#define WCSS_VERSION 1057