fw-api: CL 6631391 - update fw common interface files

Change-Id: Ib5c584481a410c3c98c7b634af00c4bb384eb2ec
HTT: add rx offset specs to RX_RING_SELECTION_CFG msg def
CRs-Fixed: 2262693

fw/htt.h

@@ -175,9 +175,10 @@
  * 3.58 Add optional MSDU ack RSSI array to end of HTT_T2H TX_COMPL_IND msg
  * 3.59 Add HTT_RXDMA_HOST_BUF_RING2 def
  * 3.60 Add HTT_T2H_MSG_TYPE_PEER_STATS_IND def
+ * 3.61 Add rx offset fields to HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG msg
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 60
+#define HTT_CURRENT_VERSION_MINOR 61
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -4728,9 +4729,9 @@ enum htt_srng_ring_id {
  *
  *    The message would appear as follows:
  *
- *    |31       26|25|24|23            16|15             8|7             0|
+ *    |31    27|26|25|24|23            16|15             8|7             0|
  *    |-----------------+----------------+----------------+---------------|
- *    |   rsvd1   |PS|SS|     ring_id    |     pdev_id    |    msg_type   |
+ *    |  rsvd1 |OV|PS|SS|     ring_id    |     pdev_id    |    msg_type   |
  *    |-------------------------------------------------------------------|
  *    |              rsvd2               |           ring_buffer_size     |
  *    |-------------------------------------------------------------------|
@@ -4744,9 +4745,18 @@ enum htt_srng_ring_id {
  *    |-------------------------------------------------------------------|
  *    |                         tlv_filter_in_flags                       |
  *    |-------------------------------------------------------------------|
+ *    |         rx_header_offset         |       rx_packet_offset         |
+ *    |-------------------------------------------------------------------|
+ *    |       rx_mpdu_start_offset       |      rx_mpdu_end_offset        |
+ *    |-------------------------------------------------------------------|
+ *    |       rx_msdu_start_offset       |      rx_msdu_end_offset        |
+ *    |-------------------------------------------------------------------|
+ *    |              rsvd3               |      rx_attention_offset       |
+ *    |-------------------------------------------------------------------|
  * Where:
  *     PS = pkt_swap
  *     SS = status_swap
+ *     OV = rx_offsets_valid
  * The message is interpreted as follows:
  * dword0 - b'0:7   - msg_type: This will be set to
  *                    HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
@@ -4755,9 +4765,15 @@ enum htt_srng_ring_id {
  *                    1/2/3 mac id (for rings at LMAC level)
  *          b'16:23 - ring_id : Identify the ring to configure.
  *                    More details can be got from enum htt_srng_ring_id
- *          b'24    - status_swap: 1 is to swap status TLV
- *          b'25    - pkt_swap:  1 is to swap packet TLV
- *          b'26:31 - rsvd1:  reserved for future use
+ *          b'24    - status_swap (SS): 1 is to swap status TLV - refer to
+ *                    BUF_RING_CFG_0 defs within HW .h files,
+ *                    e.g. wmac_top_reg_seq_hwioreg.h
+ *          b'25    - pkt_swap (PS):  1 is to swap packet TLV - refer to
+ *                    BUF_RING_CFG_0 defs within HW .h files,
+ *                    e.g. wmac_top_reg_seq_hwioreg.h
+ *          b'26    - rx_offset_valid (OV): flag to indicate rx offsets
+ *                    configuration fields are valid
+ *          b'27:31 - rsvd1:  reserved for future use
  * dword1 - b'0:16  - ring_buffer_size: size of bufferes referenced by rx ring,
  *                    in byte units.
  *                    Valid only for HW_TO_SW_RING and SW_TO_HW_RING
@@ -4786,14 +4802,51 @@ enum htt_srng_ring_id {
  * dword6 - b'0:31 -  tlv_filter_in_flags:
  *                    Filter in Attention/MPDU/PPDU/Header/User tlvs
  *                    Refer to CFG_TLV_FILTER_IN_FLAG defs
+ * dword7 - b'0:15 -  rx_packet_offset: rx_packet_offset in byte units
+ *                    Valid only for HW_TO_SW_RING and SW_TO_HW_RING
+ *                    A value of 0 will be considered as ignore this config.
+ *                    Refer to BUF_RING_CFG_1 defs within HW .h files,
+ *                    e.g. wmac_top_reg_seq_hwioreg.h
+ *        - b'16:31 - rx_header_offset: rx_header_offset in byte units
+ *                    Valid only for HW_TO_SW_RING and SW_TO_HW_RING
+ *                    A value of 0 will be considered as ignore this config.
+ *                    Refer to BUF_RING_CFG_1 defs within HW .h files,
+ *                    e.g. wmac_top_reg_seq_hwioreg.h
+ * dword8 - b'0:15 -  rx_mpdu_end_offset: rx_mpdu_end_offset in byte units
+ *                    Valid only for HW_TO_SW_RING and SW_TO_HW_RING
+ *                    A value of 0 will be considered as ignore this config.
+ *                    Refer to BUF_RING_CFG_2 defs within HW .h files,
+ *                    e.g. wmac_top_reg_seq_hwioreg.h
+ *        - b'16:31 - rx_mpdu_start_offset: rx_mpdu_start_offset in byte units
+ *                    Valid only for HW_TO_SW_RING and SW_TO_HW_RING
+ *                    A value of 0 will be considered as ignore this config.
+ *                    Refer to BUF_RING_CFG_2 defs within HW .h files,
+ *                    e.g. wmac_top_reg_seq_hwioreg.h
+ * dword9 - b'0:15 -  rx_msdu_end_offset: rx_msdu_end_offset in byte units
+ *                    Valid only for HW_TO_SW_RING and SW_TO_HW_RING
+ *                    A value of 0 will be considered as ignore this config.
+ *                    Refer to BUF_RING_CFG_3 defs within HW .h files,
+ *                    e.g. wmac_top_reg_seq_hwioreg.h
+ *        - b'16:31 - rx_msdu_start_offset: rx_msdu_start_offset in byte units
+ *                    Valid only for HW_TO_SW_RING and SW_TO_HW_RING
+ *                    A value of 0 will be considered as ignore this config.
+ *                    Refer to BUF_RING_CFG_3 defs within HW .h files,
+ *                    e.g. wmac_top_reg_seq_hwioreg.h
+ * dword10 - b'0:15 - rx_attention_offset: rx_attention_offset in byte units
+ *                    Valid only for HW_TO_SW_RING and SW_TO_HW_RING
+ *                    A value of 0 will be considered as ignore this config.
+ *                    Refer to BUF_RING_CFG_4 defs within HW .h files,
+ *                    e.g. wmac_top_reg_seq_hwioreg.h
+ *        - b'16-31 - rsvd3 for future use
  */
 PREPACK struct htt_rx_ring_selection_cfg_t {
-    A_UINT32 msg_type:    8,
-             pdev_id:     8,
-             ring_id:     8,
-             status_swap: 1,
-             pkt_swap:    1,
-             rsvd1:       6;
+    A_UINT32 msg_type:          8,
+             pdev_id:           8,
+             ring_id:           8,
+             status_swap:       1,
+             pkt_swap:          1,
+             rx_offsets_valid:  1,
+             rsvd1:             5;
     A_UINT32 ring_buffer_size: 16,
              rsvd2:            16;
     A_UINT32 packet_type_enable_flags_0;
@@ -4801,6 +4854,14 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
     A_UINT32 packet_type_enable_flags_2;
     A_UINT32 packet_type_enable_flags_3;
     A_UINT32 tlv_filter_in_flags;
+    A_UINT32 rx_packet_offset:     16,
+             rx_header_offset:     16;
+    A_UINT32 rx_mpdu_end_offset:   16,
+             rx_mpdu_start_offset: 16;
+    A_UINT32 rx_msdu_end_offset:   16,
+             rx_msdu_start_offset: 16;
+    A_UINT32 rx_attn_offset:       16,
+             rsvd3:                16;
 } POSTPACK;
 
 #define HTT_RX_RING_SELECTION_CFG_SZ    (sizeof(struct htt_rx_ring_selection_cfg_t))
@@ -4849,6 +4910,17 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
                 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S)); \
             } while (0)
 
+#define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_M           0x04000000
+#define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S           26
+#define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S)); \
+            } while (0)
+
 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M           0x0000ffff
 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S           0
 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_GET(_var) \
@@ -4915,6 +4987,83 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
                 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S)); \
             } while (0)
 
+#define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_M         0x0000ffff
+#define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S         0
+#define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_M         0xffff0000
+#define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S         16
+#define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_M         0x0000ffff
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S         0
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_M         0xffff0000
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S         16
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_M         0x0000ffff
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S         0
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_M         0xffff0000
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S         16
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_M         0x0000ffff
+#define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S         0
+#define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S)); \
+            } while (0)
+
 /*
  * Subtype based MGMT frames enable bits.
  * FP: Filter_Pass, MD: Monitor_Direct MO: Monitor_Other