qcacmn: Add hal_reo_status_get_header_generic API
Implement hal_reo_status_get_header_generic based on the chipset as the macro to retrieve reo_status value is chipset dependent. Change-Id: I43bd624bec37fb051f33b4828fcf7cd3e4b2a61e CRs-Fixed: 2522133
Šī revīzija ir iekļauta:

revīziju iesūtīja
nshrivas

vecāks
84d5092701
revīzija
25d7dbc589
@@ -605,6 +605,103 @@ static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v1(void *hw_desc_addr)
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return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID);
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}
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/**
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* hal_reo_status_get_header_8074v1 - Process reo desc info
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* @d - Pointer to reo descriptior
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* @b - tlv type info
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* @h1 - Pointer to hal_reo_status_header where info to be stored
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*
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* Return - none.
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*
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*/
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static void hal_reo_status_get_header_8074v1(uint32_t *d, int b, void *h1)
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{
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uint32_t val1 = 0;
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struct hal_reo_status_header *h =
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(struct hal_reo_status_header *)h1;
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switch (b) {
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case HAL_REO_QUEUE_STATS_STATUS_TLV:
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val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
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UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
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break;
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case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
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val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0,
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UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
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break;
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case HAL_REO_FLUSH_CACHE_STATUS_TLV:
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val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0,
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UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
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break;
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case HAL_REO_UNBLK_CACHE_STATUS_TLV:
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val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0,
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UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
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break;
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case HAL_REO_TIMOUT_LIST_STATUS_TLV:
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val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0,
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UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
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break;
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case HAL_REO_DESC_THRES_STATUS_TLV:
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val1 =
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d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0,
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UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
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break;
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case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
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val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0,
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UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
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break;
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default:
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qdf_nofl_err("ERROR: Unknown tlv\n");
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break;
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}
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h->cmd_num =
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HAL_GET_FIELD(
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UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER,
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val1);
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h->exec_time =
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HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
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CMD_EXECUTION_TIME, val1);
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h->status =
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HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
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REO_CMD_EXECUTION_STATUS, val1);
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switch (b) {
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case HAL_REO_QUEUE_STATS_STATUS_TLV:
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val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1,
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UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
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break;
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case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
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val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1,
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UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
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break;
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case HAL_REO_FLUSH_CACHE_STATUS_TLV:
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val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1,
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UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
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break;
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case HAL_REO_UNBLK_CACHE_STATUS_TLV:
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val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1,
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UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
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break;
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case HAL_REO_TIMOUT_LIST_STATUS_TLV:
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val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1,
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UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
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break;
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case HAL_REO_DESC_THRES_STATUS_TLV:
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val1 =
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d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1,
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UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
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break;
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case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
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val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1,
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UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
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break;
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default:
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qdf_nofl_err("ERROR: Unknown tlv\n");
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break;
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}
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h->tstamp =
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HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
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}
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struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
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/* init and setup */
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@@ -639,7 +736,7 @@ struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
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hal_rx_msdu_end_da_idx_get_8074,
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hal_rx_msdu_desc_info_get_ptr_generic,
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hal_rx_link_desc_msdu0_ptr_generic,
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hal_reo_status_get_header_generic,
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hal_reo_status_get_header_8074v1,
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hal_rx_status_get_tlv_info_generic,
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hal_rx_wbm_err_info_get_generic,
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hal_rx_dump_mpdu_start_tlv_generic,
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