disp: msm: dsi: Mask overflow error for Broadcast command
Currently, for Dual DSI Broadcast command, Overflow error is masked only for master controller. This changes add support to mask overflow error for slave controller as well. Change-Id: Ida73c4166e996fcf2c8c936d0c76d0a89a220d89 Signed-off-by: Harigovindan P <harigovi@codeaurora.org> Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org> Signed-off-by: Steve Cohen <cohens@codeaurora.org>
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committed by
Steve Cohen

parent
d8ffbf3d39
commit
25b6a3e7d1
@@ -1361,9 +1361,7 @@ static void dsi_kickoff_msg_tx(struct dsi_ctrl *dsi_ctrl,
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if (!(flags & DSI_CTRL_CMD_DEFER_TRIGGER)) {
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dsi_ctrl_wait_for_video_done(dsi_ctrl);
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if (dsi_hw_ops.mask_error_intr)
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dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw,
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BIT(DSI_FIFO_OVERFLOW), true);
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dsi_ctrl_mask_overflow(dsi_ctrl, true);
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atomic_set(&dsi_ctrl->dma_irq_trig, 0);
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dsi_ctrl_enable_status_interrupt(dsi_ctrl,
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@@ -1407,9 +1405,8 @@ static void dsi_kickoff_msg_tx(struct dsi_ctrl *dsi_ctrl,
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dsi_ctrl_dma_cmd_wait_for_done(&dsi_ctrl->dma_cmd_wait);
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}
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if (dsi_hw_ops.mask_error_intr && !dsi_ctrl->esd_check_underway)
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dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw,
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BIT(DSI_FIFO_OVERFLOW), false);
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dsi_ctrl_mask_overflow(dsi_ctrl, false);
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dsi_hw_ops.reset_cmd_fifo(&dsi_ctrl->hw);
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/*
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@@ -3316,6 +3313,28 @@ error:
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return rc;
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}
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/**
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* dsi_ctrl_mask_overflow() - API to mask/unmask overflow error.
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* @dsi_ctrl: DSI controller handle.
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* @enable: variable to control masking/unmasking.
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*/
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void dsi_ctrl_mask_overflow(struct dsi_ctrl *dsi_ctrl, bool enable)
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{
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struct dsi_ctrl_hw_ops dsi_hw_ops;
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dsi_hw_ops = dsi_ctrl->hw.ops;
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if (enable) {
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if (dsi_hw_ops.mask_error_intr)
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dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw,
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BIT(DSI_FIFO_OVERFLOW), true);
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} else {
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if (dsi_hw_ops.mask_error_intr && !dsi_ctrl->esd_check_underway)
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dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw,
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BIT(DSI_FIFO_OVERFLOW), false);
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}
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}
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/**
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* dsi_ctrl_cmd_tx_trigger() - Trigger a deferred command.
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* @dsi_ctrl: DSI controller handle.
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@@ -3358,9 +3377,6 @@ int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags)
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if ((flags & DSI_CTRL_CMD_BROADCAST) &&
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(flags & DSI_CTRL_CMD_BROADCAST_MASTER)) {
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dsi_ctrl_wait_for_video_done(dsi_ctrl);
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if (dsi_hw_ops.mask_error_intr)
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dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw,
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BIT(DSI_FIFO_OVERFLOW), true);
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atomic_set(&dsi_ctrl->dma_irq_trig, 0);
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dsi_ctrl_enable_status_interrupt(dsi_ctrl,
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DSI_SINT_CMD_MODE_DMA_DONE, NULL);
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@@ -3388,11 +3404,6 @@ int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags)
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dsi_ctrl_dma_cmd_wait_for_done(&dsi_ctrl->dma_cmd_wait);
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}
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if (dsi_hw_ops.mask_error_intr &&
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!dsi_ctrl->esd_check_underway)
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dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw,
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BIT(DSI_FIFO_OVERFLOW), false);
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if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
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if (dsi_ctrl->version < DSI_CTRL_VERSION_2_4)
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dsi_hw_ops.soft_reset(&dsi_ctrl->hw);
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