disp: msm: sde: add helper function to setup encoder and sspp

This change creates a helper function for sde_encoder_virt_enable
which is responsible for setting up physical encoders. Similarly, it
creates a helper function for sde_hw_sspp_setup_format which is
responsible for writing to the static control register based on ubwc
version.

Change-Id: I106f1f2524398daf7285a931971099735ee8dd4f
Signed-off-by: Samantha Tran <[email protected]>

msm/sde/sde_encoder.c

@@ -2733,6 +2733,65 @@ void sde_encoder_virt_restore(struct drm_encoder *drm_enc)
 	_sde_encoder_virt_enable_helper(drm_enc);
 }
 
+static void sde_encoder_populate_encoder_phys(struct drm_encoder *drm_enc,
+		struct sde_encoder_virt *sde_enc, struct msm_display_mode *msm_mode)
+{
+	struct msm_compression_info *comp_info = &sde_enc->mode_info.comp_info;
+	struct msm_display_info *disp_info = &sde_enc->disp_info;
+	int i;
+
+	for (i = 0; i < sde_enc->num_phys_encs; i++) {
+		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+		if (!phys)
+			continue;
+
+		phys->comp_type = comp_info->comp_type;
+		phys->comp_ratio = comp_info->comp_ratio;
+		phys->frame_trigger_mode = sde_enc->frame_trigger_mode;
+		phys->poms_align_vsync = disp_info->poms_align_vsync;
+		if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC) {
+			phys->dsc_extra_pclk_cycle_cnt =
+				comp_info->dsc_info.pclk_per_line;
+			phys->dsc_extra_disp_width =
+				comp_info->dsc_info.extra_width;
+			phys->dce_bytes_per_line =
+				comp_info->dsc_info.bytes_per_pkt *
+				comp_info->dsc_info.pkt_per_line;
+		} else if (phys->comp_type == MSM_DISPLAY_COMPRESSION_VDC) {
+			phys->dce_bytes_per_line =
+				comp_info->vdc_info.bytes_per_pkt *
+				comp_info->vdc_info.pkt_per_line;
+		}
+
+		if (phys != sde_enc->cur_master) {
+			/**
+			 * on DMS request, the encoder will be enabled
+			 * already. Invoke restore to reconfigure the
+			 * new mode.
+			 */
+			if ((msm_is_mode_seamless_dms(msm_mode) ||
+				msm_is_mode_seamless_dyn_clk(msm_mode)) &&
+					phys->ops.restore)
+				phys->ops.restore(phys);
+			else if (phys->ops.enable)
+				phys->ops.enable(phys);
+		}
+
+		if (sde_enc->misr_enable  && phys->ops.setup_misr &&
+		(sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE)))
+			phys->ops.setup_misr(phys, true,
+						sde_enc->misr_frame_count);
+	}
+
+	if ((msm_is_mode_seamless_dms(msm_mode) ||
+			msm_is_mode_seamless_dyn_clk(msm_mode)) &&
+			sde_enc->cur_master->ops.restore)
+		sde_enc->cur_master->ops.restore(sde_enc->cur_master);
+	else if (sde_enc->cur_master->ops.enable)
+		sde_enc->cur_master->ops.enable(sde_enc->cur_master);
+}
+
 static void sde_encoder_off_work(struct kthread_work *work)
 {
 	struct sde_encoder_virt *sde_enc = container_of(work,
@@ -2755,17 +2814,14 @@ static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
 	struct sde_encoder_virt *sde_enc = NULL;
 	int i, ret = 0;
 	struct sde_connector_state *c_state;
-	struct msm_compression_info *comp_info = NULL;
 	struct drm_display_mode *cur_mode = NULL;
 	struct msm_display_mode *msm_mode;
-	struct msm_display_info *disp_info;
 
 	if (!drm_enc || !drm_enc->crtc) {
 		SDE_ERROR("invalid encoder\n");
 		return;
 	}
 	sde_enc = to_sde_encoder_virt(drm_enc);
-	disp_info = &sde_enc->disp_info;
 
 	if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
 		SDE_ERROR("power resource is not enabled\n");
@@ -2775,7 +2831,6 @@ static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
 	if (!sde_enc->crtc)
 		sde_enc->crtc = drm_enc->crtc;
 
-	comp_info = &sde_enc->mode_info.comp_info;
 	cur_mode = &sde_enc->base.crtc->state->adjusted_mode;
 
 	SDE_DEBUG_ENC(sde_enc, "\n");
@@ -2823,56 +2878,7 @@ static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
 	memset(&sde_enc->cur_master->intf_cfg_v1, 0,
 			sizeof(sde_enc->cur_master->intf_cfg_v1));
 
-	for (i = 0; i < sde_enc->num_phys_encs; i++) {
-		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
-
-		if (!phys)
-			continue;
-
-		phys->comp_type = comp_info->comp_type;
-		phys->comp_ratio = comp_info->comp_ratio;
-		phys->frame_trigger_mode = sde_enc->frame_trigger_mode;
-		phys->poms_align_vsync = disp_info->poms_align_vsync;
-		if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC) {
-			phys->dsc_extra_pclk_cycle_cnt =
-				comp_info->dsc_info.pclk_per_line;
-			phys->dsc_extra_disp_width =
-				comp_info->dsc_info.extra_width;
-			phys->dce_bytes_per_line =
-				comp_info->dsc_info.bytes_per_pkt *
-				comp_info->dsc_info.pkt_per_line;
-		} else if (phys->comp_type == MSM_DISPLAY_COMPRESSION_VDC) {
-			phys->dce_bytes_per_line =
-				comp_info->vdc_info.bytes_per_pkt *
-				comp_info->vdc_info.pkt_per_line;
-		}
-
-		if (phys != sde_enc->cur_master) {
-			/**
-			 * on DMS request, the encoder will be enabled
-			 * already. Invoke restore to reconfigure the
-			 * new mode.
-			 */
-			if ((msm_is_mode_seamless_dms(msm_mode) ||
-				msm_is_mode_seamless_dyn_clk(msm_mode)) &&
-					phys->ops.restore)
-				phys->ops.restore(phys);
-			else if (phys->ops.enable)
-				phys->ops.enable(phys);
-		}
-
-		if (sde_enc->misr_enable  && phys->ops.setup_misr &&
-		(sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE)))
-			phys->ops.setup_misr(phys, true,
-						sde_enc->misr_frame_count);
-	}
-
-	if ((msm_is_mode_seamless_dms(msm_mode) ||
-			msm_is_mode_seamless_dyn_clk(msm_mode)) &&
-			sde_enc->cur_master->ops.restore)
-		sde_enc->cur_master->ops.restore(sde_enc->cur_master);
-	else if (sde_enc->cur_master->ops.enable)
-		sde_enc->cur_master->ops.enable(sde_enc->cur_master);
+	sde_encoder_populate_encoder_phys(drm_enc, sde_enc, msm_mode);
 
 	_sde_encoder_virt_enable_helper(drm_enc);
 }

msm/sde/sde_hw_sspp.c

@@ -295,6 +295,36 @@ static void sde_hw_sspp_set_src_split_order(struct sde_hw_pipe *ctx,
 	SDE_REG_WRITE(c, op_mode_off + idx, opmode);
 }
 
+static void sde_hw_sspp_setup_ubwc(struct sde_hw_pipe *ctx, struct sde_hw_blk_reg_map *c,
+		const struct sde_format *fmt, bool const_alpha_en, bool const_color_en)
+{
+	u32 alpha_en_mask = 0, color_en_mask = 0;
+
+	SDE_REG_WRITE(c, SSPP_FETCH_CONFIG,
+		SDE_FETCH_CONFIG_RESET_VALUE |
+		ctx->mdp->highest_bank_bit << 18);
+
+	if (IS_UBWC_40_SUPPORTED(ctx->catalog->ubwc_version)) {
+		SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+			SDE_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
+	} else if (IS_UBWC_30_SUPPORTED(ctx->catalog->ubwc_version)) {
+		color_en_mask = const_color_en ? BIT(30) : 0;
+		SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+			color_en_mask | (ctx->mdp->ubwc_swizzle) |
+			(ctx->mdp->highest_bank_bit << 4));
+	} else if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_version)) {
+		alpha_en_mask = const_alpha_en ? BIT(31) : 0;
+		SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+			alpha_en_mask | (ctx->mdp->ubwc_swizzle) |
+			(ctx->mdp->highest_bank_bit << 4));
+	} else if (IS_UBWC_10_SUPPORTED(ctx->catalog->ubwc_version)) {
+		alpha_en_mask = const_alpha_en ? BIT(31) : 0;
+		SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+			alpha_en_mask | (ctx->mdp->ubwc_swizzle & 0x1) |
+			BIT(8) | (ctx->mdp->highest_bank_bit << 4));
+	}
+}
+
 /**
  * Setup source pixel format, flip,
  */
@@ -306,7 +336,6 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx,
 	struct sde_hw_blk_reg_map *c;
 	u32 chroma_samp, unpack, src_format;
 	u32 opmode = 0;
-	u32 alpha_en_mask = 0, color_en_mask = 0;
 	u32 op_mode_off, unpack_pat_off, format_off;
 	u32 idx;
 	bool const_color_en = true;
@@ -377,28 +406,8 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx,
 		if (SDE_FORMAT_IS_UBWC(fmt))
 			opmode |= MDSS_MDP_OP_BWC_EN;
 		src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
-		SDE_REG_WRITE(c, SSPP_FETCH_CONFIG,
-			SDE_FETCH_CONFIG_RESET_VALUE |
-			ctx->mdp->highest_bank_bit << 18);
-		if (IS_UBWC_40_SUPPORTED(ctx->catalog->ubwc_version)) {
-			SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
-				SDE_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
-		} else if (IS_UBWC_10_SUPPORTED(ctx->catalog->ubwc_version)) {
-			alpha_en_mask = const_alpha_en ? BIT(31) : 0;
-			SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
-				alpha_en_mask | (ctx->mdp->ubwc_swizzle & 0x1) |
-				BIT(8) | (ctx->mdp->highest_bank_bit << 4));
-		} else if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_version)) {
-			alpha_en_mask = const_alpha_en ? BIT(31) : 0;
-			SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
-				alpha_en_mask | (ctx->mdp->ubwc_swizzle) |
-				(ctx->mdp->highest_bank_bit << 4));
-		} else if (IS_UBWC_30_SUPPORTED(ctx->catalog->ubwc_version)) {
-			color_en_mask = const_color_en ? BIT(30) : 0;
-			SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
-				color_en_mask | (ctx->mdp->ubwc_swizzle) |
-				(ctx->mdp->highest_bank_bit << 4));
-		}
+
+		sde_hw_sspp_setup_ubwc(ctx, c, fmt, const_alpha_en, const_color_en);
 	}
 
 	opmode |= MDSS_MDP_OP_PE_OVERRIDE;