qcacmn: Add HAL layer changes for full monitor mode
Add HAL layer changes for full monitor mode. Define HAL API and Data structures to read sw_monitor_ring descriptor. CRs-Fixed: 2630982 Change-Id: I015fa106d9da74222bef092d50e96fc70a117a4a
This commit is contained in:
@@ -66,30 +66,6 @@
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*/
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*/
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#define MAPPED_REF_OFF 0xFE0
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#define MAPPED_REF_OFF 0xFE0
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/**
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* hal_ring_desc - opaque handle for DP ring descriptor
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*/
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struct hal_ring_desc;
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typedef struct hal_ring_desc *hal_ring_desc_t;
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/**
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* hal_link_desc - opaque handle for DP link descriptor
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*/
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struct hal_link_desc;
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typedef struct hal_link_desc *hal_link_desc_t;
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/**
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* hal_rxdma_desc - opaque handle for DP rxdma dst ring descriptor
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*/
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struct hal_rxdma_desc;
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typedef struct hal_rxdma_desc *hal_rxdma_desc_t;
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/**
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* hal_buff_addrinfo - opaque handle for DP buffer address info
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*/
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struct hal_buff_addrinfo;
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typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t;
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#ifdef ENABLE_VERBOSE_DEBUG
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#ifdef ENABLE_VERBOSE_DEBUG
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static inline void
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static inline void
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hal_set_verbose_debug(bool flag)
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hal_set_verbose_debug(bool flag)
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@@ -2036,4 +2012,21 @@ static inline void hal_srng_inc_flush_cnt(hal_ring_handle_t hal_ring_hdl)
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srng->flush_count++;
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srng->flush_count++;
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}
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}
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/**
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* hal_rx_sw_mon_desc_info_get () - Get SW monitor desc info
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*
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* @hal: Core HAL soc handle
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* @ring_desc: Mon dest ring descriptor
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* @desc_info: Desc info to be populated
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*
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* Return void
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*/
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static inline void
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hal_rx_sw_mon_desc_info_get(struct hal_soc *hal,
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hal_ring_desc_t ring_desc,
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hal_rx_mon_desc_info_t desc_info)
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{
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return hal->ops->hal_rx_sw_mon_desc_info_get(ring_desc, desc_info);
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}
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#endif /* _HAL_APIH_ */
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#endif /* _HAL_APIH_ */
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@@ -155,6 +155,31 @@
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/* Max pilot count */
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/* Max pilot count */
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#define HAL_RX_MAX_SU_EVM_COUNT 32
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#define HAL_RX_MAX_SU_EVM_COUNT 32
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/**
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* struct hal_rx_mon_desc_info () - HAL Rx Monitor descriptor info
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*
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* @ppdu_id: PHY ppdu id
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* @status_buf_count: number of status buffer count
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* @rxdma_push_reason: rxdma push reason
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* @rxdma_error_code: rxdma error code
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* @msdu_cnt: msdu count
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* @end_of_ppdu: end of ppdu
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* @link_desc: msdu link descriptor address
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* @status_buf: for a PPDU, status buffers can span acrosss
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* multiple buffers, status_buf points to first
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* status buffer address of PPDU
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*/
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struct hal_rx_mon_desc_info {
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uint16_t ppdu_id;
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uint8_t status_buf_count;
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uint8_t rxdma_push_reason;
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uint8_t rxdma_error_code;
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uint8_t msdu_count;
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uint8_t end_of_ppdu;
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struct hal_buf_info link_desc;
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struct hal_buf_info status_buf;
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};
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/*
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/*
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* Struct hal_rx_su_evm_info - SU evm info
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* Struct hal_rx_su_evm_info - SU evm info
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* @number_of_symbols: number of symbols
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* @number_of_symbols: number of symbols
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@@ -68,6 +68,36 @@ extern bool is_hal_verbose_debug_enabled;
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struct hal_soc_handle;
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struct hal_soc_handle;
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typedef struct hal_soc_handle *hal_soc_handle_t;
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typedef struct hal_soc_handle *hal_soc_handle_t;
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/**
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* hal_ring_desc - opaque handle for DP ring descriptor
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*/
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struct hal_ring_desc;
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typedef struct hal_ring_desc *hal_ring_desc_t;
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/**
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* hal_link_desc - opaque handle for DP link descriptor
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*/
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struct hal_link_desc;
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typedef struct hal_link_desc *hal_link_desc_t;
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/**
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* hal_rxdma_desc - opaque handle for DP rxdma dst ring descriptor
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*/
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struct hal_rxdma_desc;
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typedef struct hal_rxdma_desc *hal_rxdma_desc_t;
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/**
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* hal_buff_addrinfo - opaque handle for DP buffer address info
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*/
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struct hal_buff_addrinfo;
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typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t;
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/**
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* hal_rx_mon_desc_info - opaque handle for sw monitor ring desc info
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*/
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struct hal_rx_mon_desc_info;
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typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t;
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/* TBD: This should be movded to shared HW header file */
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/* TBD: This should be movded to shared HW header file */
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enum hal_srng_ring_id {
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enum hal_srng_ring_id {
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/* UMAC rings */
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/* UMAC rings */
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@@ -558,6 +588,8 @@ struct hal_hw_txrx_ops {
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uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf);
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uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf);
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bool (*hal_rx_get_fisa_timeout)(uint8_t *buf);
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bool (*hal_rx_get_fisa_timeout)(uint8_t *buf);
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uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr);
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uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr);
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void (*hal_rx_sw_mon_desc_info_get)(hal_ring_desc_t rxdma_dst_ring_desc,
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hal_rx_mon_desc_info_t mon_desc_info);
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};
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};
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/**
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/**
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@@ -1087,6 +1087,8 @@ struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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};
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};
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struct hal_hw_srng_config hw_srng_table_6390[] = {
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struct hal_hw_srng_config hw_srng_table_6390[] = {
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@@ -1510,6 +1510,8 @@ struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
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hal_rx_get_flow_agg_continuation_6490,
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hal_rx_get_flow_agg_continuation_6490,
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hal_rx_get_flow_agg_count_6490,
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hal_rx_get_flow_agg_count_6490,
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hal_rx_get_fisa_timeout_6490,
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hal_rx_get_fisa_timeout_6490,
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NULL,
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NULL,
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};
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};
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struct hal_hw_srng_config hw_srng_table_6490[] = {
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struct hal_hw_srng_config hw_srng_table_6490[] = {
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@@ -1113,6 +1113,7 @@ struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
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NULL,
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NULL,
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NULL,
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NULL,
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hal_rx_mpdu_start_tlv_tag_valid_8074v1,
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hal_rx_mpdu_start_tlv_tag_valid_8074v1,
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NULL,
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};
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};
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struct hal_hw_srng_config hw_srng_table_8074[] = {
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struct hal_hw_srng_config hw_srng_table_8074[] = {
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@@ -1116,6 +1116,7 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
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NULL,
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NULL,
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NULL,
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NULL,
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hal_rx_mpdu_start_tlv_tag_valid_8074v2,
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hal_rx_mpdu_start_tlv_tag_valid_8074v2,
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NULL,
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};
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};
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struct hal_hw_srng_config hw_srng_table_8074v2[] = {
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struct hal_hw_srng_config hw_srng_table_8074v2[] = {
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@@ -21,6 +21,9 @@
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#include "target_type.h"
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#include "target_type.h"
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#include "wcss_version.h"
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#include "wcss_version.h"
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#include "qdf_module.h"
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#include "qdf_module.h"
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#include "hal_9000_rx.h"
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#include "hal_api_mon.h"
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#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
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#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
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RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET
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RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET
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#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
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#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
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@@ -116,6 +119,60 @@
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#include <hal_generic_api.h>
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#include <hal_generic_api.h>
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#include <hal_wbm.h>
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#include <hal_wbm.h>
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/**
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* hal_rx_sw_mon_desc_info_get_9000(): API to read the
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* sw monitor ring descriptor
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*
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* @rxdma_dst_ring_desc: sw monitor ring descriptor
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* @desc_info_buf: Descriptor info buffer to which
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* sw monitor ring descriptor is populated to
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*
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* Return: void
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*/
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static void
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hal_rx_sw_mon_desc_info_get_9000(hal_ring_desc_t rxdma_dst_ring_desc,
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hal_rx_mon_desc_info_t desc_info_buf)
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{
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struct sw_monitor_ring *sw_mon_ring =
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(struct sw_monitor_ring *)rxdma_dst_ring_desc;
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struct buffer_addr_info *buf_addr_info;
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uint32_t *mpdu_info;
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uint32_t loop_cnt;
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struct hal_rx_mon_desc_info *desc_info;
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desc_info = (struct hal_rx_mon_desc_info *)desc_info_buf;
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mpdu_info = (uint32_t *)&sw_mon_ring->
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reo_level_mpdu_frame_info.rx_mpdu_desc_info_details;
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loop_cnt = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_7, LOOPING_COUNT);
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desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info);
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/* Get msdu link descriptor buf_addr_info */
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buf_addr_info = &sw_mon_ring->
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reo_level_mpdu_frame_info.msdu_link_desc_addr_info;
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desc_info->link_desc.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info)
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| ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(
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buf_addr_info)) << 32);
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desc_info->link_desc.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
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buf_addr_info = &sw_mon_ring->status_buff_addr_info;
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desc_info->status_buf.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info)
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(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32);
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desc_info->status_buf.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
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desc_info->end_of_ppdu = HAL_RX_GET(sw_mon_ring,
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SW_MONITOR_RING_6,
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END_OF_PPDU);
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desc_info->status_buf_count = HAL_RX_GET(sw_mon_ring,
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SW_MONITOR_RING_6,
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STATUS_BUF_COUNT);
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desc_info->rxdma_push_reason = HAL_RX_GET(sw_mon_ring,
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SW_MONITOR_RING_6,
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RXDMA_PUSH_REASON);
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desc_info->ppdu_id = HAL_RX_GET(sw_mon_ring,
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SW_MONITOR_RING_7,
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PHY_PPDU_ID);
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}
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/**
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/**
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* hal_rx_msdu_start_nss_get_9000(): API to get the NSS
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* hal_rx_msdu_start_nss_get_9000(): API to get the NSS
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* Interval from rx_msdu_start
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* Interval from rx_msdu_start
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@@ -1490,6 +1547,7 @@ struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
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NULL,
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NULL,
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NULL,
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NULL,
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hal_rx_mpdu_start_tlv_tag_valid_9000,
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hal_rx_mpdu_start_tlv_tag_valid_9000,
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hal_rx_sw_mon_desc_info_get_9000,
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};
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};
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struct hal_hw_srng_config hw_srng_table_9000[] = {
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struct hal_hw_srng_config hw_srng_table_9000[] = {
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@@ -1852,7 +1910,7 @@ struct hal_hw_srng_config hw_srng_table_9000[] = {
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{ /* RXDMA_MONITOR_DST */
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{ /* RXDMA_MONITOR_DST */
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.start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
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.start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
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.max_rings = 1,
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.max_rings = 1,
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.entry_size = sizeof(struct reo_entrance_ring) >> 2,
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.entry_size = sizeof(struct sw_monitor_ring) >> 2,
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.lmac_ring = TRUE,
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.lmac_ring = TRUE,
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.ring_dir = HAL_SRNG_DST_RING,
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.ring_dir = HAL_SRNG_DST_RING,
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/* reg_start is not set because LMAC rings are not accessed
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/* reg_start is not set because LMAC rings are not accessed
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@@ -16,6 +16,10 @@
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* PERFORMANCE OF THIS SOFTWARE.
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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*/
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#include "sw_monitor_ring.h"
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#include "hal_rx.h"
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#include "hal_api_mon.h"
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#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
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#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
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((uint8_t *)(link_desc_va) + \
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((uint8_t *)(link_desc_va) + \
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RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET)
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RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET)
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