samsung-sm8650/android_kernel_samsung_sm8650-modules
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disp: msm: sde: separate out DSC 4HS config programming

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Dedicated registers are introduced for DSC 4HS merge block
programming from MDSS.9.0. This change adds support in the
driver to identify the change using a DSC feature flag
and separates out 4HS merge block programming to use appropriate
registers based on the DSC HW feature.

Change-Id: Ia64a1ed4bc5f5f301ab422144916cdce2a1dadac
Signed-off-by: Michael Ru <mru@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
Cette révision appartient à :
Jeykumar Sankaran
2021-08-30 20:34:53 -07:00
Parent 39e7775bff
révision 24aa389edc
3 fichiers modifiés avec 41 ajouts et 9 suppressions
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3
msm/sde/sde_hw_catalog.c
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@@ -3295,7 +3295,8 @@ static int sde_dsc_parse_dt(struct device_node *np,
if (PROP_VALUE_ACCESS(prop_value, DSC_422, i))
set_bit(SDE_DSC_NATIVE_422_EN,
&dsc->features);
if (SDE_HW_MAJOR(sde_cfg->hw_rev) >= SDE_HW_MAJOR(SDE_HW_VER_900))
set_bit(SDE_DSC_4HS, &dsc->features);
} else {
set_bit(SDE_DSC_HW_REV_1_1, &dsc->features);
}

2
msm/sde/sde_hw_catalog.h
Voir le fichier

@@ -471,6 +471,7 @@ enum {
* @SDE_DSC_NATIVE_422_EN, Supports native422 and native420 encoding
* @SDE_DSC_ENC, DSC encoder sub block
* @SDE_DSC_CTL, DSC ctl sub block
* @SDE_DSC_4HS, Dedicated DSC 4HS config registers
* @SDE_DSC_MAX
*/
enum {
@@ -480,6 +481,7 @@ enum {
SDE_DSC_NATIVE_422_EN,
SDE_DSC_ENC,
SDE_DSC_CTL,
SDE_DSC_4HS,
SDE_DSC_MAX
};

45
msm/sde/sde_hw_dsc_1_2.c
Voir le fichier

@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
@@ -55,7 +56,8 @@
#define DSC_CFG 0x04
#define DSC_DATA_IN_SWAP 0x08
#define DSC_CLK_CTRL 0x0C
#define DSC_4HS_MERGE_EN 0x10
#define DSC_4HS_MERGE_CFG 0x14
static int _dsc_calc_ob_max_addr(struct sde_hw_dsc *hw_dsc, int num_ss)
{
@@ -122,6 +124,36 @@ static void sde_hw_dsc_disable(struct sde_hw_dsc *hw_dsc)
SDE_REG_WRITE(dsc_c, DSC_MAIN_CONF + idx, 0);
}
static void sde_hw_dsc_4hs_config(struct sde_hw_dsc *hw_dsc,
struct msm_display_dsc_info *dsc, u32 mode, u32 idx)
{
struct sde_hw_blk_reg_map *dsc_c;
u32 data = 0;
if (!dsc->dsc_4hsmerge_en)
return;
dsc_c = &hw_dsc->hw;
if (test_bit(SDE_DSC_4HS, &hw_dsc->caps->features)) {
data = dsc->dsc_4hsmerge_alignment << 12;
data |= dsc->dsc_4hsmerge_padding << 8;
data |= ((mode & DSC_MODE_VIDEO) ? 1 : 0);
SDE_REG_WRITE(dsc_c, DSC_4HS_MERGE_CFG + idx, data);
SDE_REG_WRITE(dsc_c, DSC_4HS_MERGE_EN + idx, BIT(0));
} else {
data = SDE_REG_READ(dsc_c, DSC_CFG + idx);
data |= dsc->dsc_4hsmerge_padding << 18;
data |= dsc->dsc_4hsmerge_alignment << 22;
data |= ((mode & DSC_MODE_VIDEO) ? 1 : 0) << 17;
data |= BIT(16);
SDE_REG_WRITE(dsc_c, DSC_CFG + idx, data);
}
}
static void sde_hw_dsc_config(struct sde_hw_dsc *hw_dsc,
struct msm_display_dsc_info *dsc, u32 mode,
bool ich_reset_override)
@@ -258,15 +290,12 @@ static void sde_hw_dsc_config(struct sde_hw_dsc *hw_dsc,
data |= BIT(12);
if (mode & DSC_MODE_MULTIPLEX)
data |= BIT(13);
if (!(mode & DSC_MODE_VIDEO))
data |= BIT(17);
if (dsc->dsc_4hsmerge_en) {
data |= dsc->dsc_4hsmerge_padding << 18;
data |= dsc->dsc_4hsmerge_alignment << 22;
data |= BIT(16);
}
SDE_REG_WRITE(dsc_c, DSC_CFG + idx, data);
wmb(); /* ensure the register is committed */
sde_hw_dsc_4hs_config(hw_dsc, dsc, mode, idx);
}
static void sde_hw_dsc_config_thresh(struct sde_hw_dsc *hw_dsc,