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@@ -507,6 +507,9 @@ static int cam_vfe_camif_ver3_resource_start(
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irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] =
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irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] =
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rsrc_data->reg_data->sof_irq_mask;
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rsrc_data->reg_data->sof_irq_mask;
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+ if (rsrc_data->cam_common_cfg.input_mux_sel_pp & 0x3)
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+ irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS0] =
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+ rsrc_data->reg_data->frame_id_irq_mask;
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if (!rsrc_data->sof_irq_handle) {
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if (!rsrc_data->sof_irq_handle) {
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rsrc_data->sof_irq_handle = cam_irq_controller_subscribe_irq(
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rsrc_data->sof_irq_handle = cam_irq_controller_subscribe_irq(
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@@ -1191,10 +1194,21 @@ static int cam_vfe_camif_ver3_handle_irq_top_half(uint32_t evt_id,
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}
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}
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cam_isp_hw_get_timestamp(&evt_payload->ts);
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cam_isp_hw_get_timestamp(&evt_payload->ts);
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+ evt_payload->th_reg_val = 0;
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for (i = 0; i < th_payload->num_registers; i++)
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for (i = 0; i < th_payload->num_registers; i++)
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evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i];
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evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i];
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+ /* Read frame_id meta at every epoch if custom hw is enabled */
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+ if (evt_payload->irq_reg_val[CAM_IFE_IRQ_CAMIF_REG_STATUS1]
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+ & camif_priv->reg_data->epoch0_irq_mask) {
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+ if ((camif_priv->common_reg->custom_frame_idx) &&
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+ (camif_priv->cam_common_cfg.input_mux_sel_pp & 0x3))
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+ evt_payload->th_reg_val = cam_io_r_mb(
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+ camif_priv->mem_base +
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+ camif_priv->common_reg->custom_frame_idx);
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+ }
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+
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th_payload->evt_payload_priv = evt_payload;
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th_payload->evt_payload_priv = evt_payload;
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CAM_DBG(CAM_ISP, "Exit");
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CAM_DBG(CAM_ISP, "Exit");
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@@ -1210,6 +1224,7 @@ static int cam_vfe_camif_ver3_handle_irq_bottom_half(void *handler_priv,
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struct cam_vfe_top_irq_evt_payload *payload;
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struct cam_vfe_top_irq_evt_payload *payload;
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struct cam_isp_hw_event_info evt_info;
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struct cam_isp_hw_event_info evt_info;
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uint32_t irq_status[CAM_IFE_IRQ_REGISTERS_MAX] = {0};
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uint32_t irq_status[CAM_IFE_IRQ_REGISTERS_MAX] = {0};
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+ uint32_t val = 0;
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int i = 0;
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int i = 0;
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if (!handler_priv || !evt_payload_priv) {
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if (!handler_priv || !evt_payload_priv) {
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@@ -1229,6 +1244,7 @@ static int cam_vfe_camif_ver3_handle_irq_bottom_half(void *handler_priv,
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evt_info.hw_idx = camif_node->hw_intf->hw_idx;
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evt_info.hw_idx = camif_node->hw_intf->hw_idx;
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evt_info.res_id = camif_node->res_id;
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evt_info.res_id = camif_node->res_id;
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evt_info.res_type = camif_node->res_type;
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evt_info.res_type = camif_node->res_type;
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+ evt_info.th_reg_val = 0;
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if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1]
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if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1]
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& camif_priv->reg_data->sof_irq_mask) {
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& camif_priv->reg_data->sof_irq_mask) {
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@@ -1259,6 +1275,7 @@ static int cam_vfe_camif_ver3_handle_irq_bottom_half(void *handler_priv,
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if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1]
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if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1]
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& camif_priv->reg_data->epoch0_irq_mask) {
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& camif_priv->reg_data->epoch0_irq_mask) {
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CAM_DBG(CAM_ISP, "VFE:%d Received EPOCH", evt_info.hw_idx);
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CAM_DBG(CAM_ISP, "VFE:%d Received EPOCH", evt_info.hw_idx);
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+ evt_info.th_reg_val = payload->th_reg_val;
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if (camif_priv->event_cb)
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if (camif_priv->event_cb)
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camif_priv->event_cb(camif_priv->priv,
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camif_priv->event_cb(camif_priv->priv,
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@@ -1294,6 +1311,15 @@ static int cam_vfe_camif_ver3_handle_irq_bottom_half(void *handler_priv,
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cam_vfe_camif_ver3_reg_dump(camif_node);
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cam_vfe_camif_ver3_reg_dump(camif_node);
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}
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}
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+ if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS0]
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+ & camif_priv->reg_data->frame_id_irq_mask) {
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+ val = cam_io_r_mb(camif_priv->mem_base +
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+ camif_priv->common_reg->custom_frame_idx);
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+ CAM_DBG(CAM_ISP,
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+ "VFE:%d Frame id change to: %u", evt_info.hw_idx,
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+ val);
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+ }
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+
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if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS2]) {
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if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS2]) {
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CAM_ERR(CAM_ISP, "VFE:%d Violation", evt_info.hw_idx);
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CAM_ERR(CAM_ISP, "VFE:%d Violation", evt_info.hw_idx);
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