disp: msm: sde: fix ich reset override logic

This change fixes the detection logic for overriding the ich
reset in both single and dual dsc case. In the previous logic
ich reset override was not getting triggered when partial update
on single dsc was enabled. This override is required to change the
default Hw behavior of changing the ich reset position.

ICH reset needs to be overridden in dual dsc merge case when
partial update disables the dsc merge and no. of slices per
encoder drops to 1. Similarly for single dsc case partial update
case when DSC encoder configuration changes from 2 slices to
single slice this override is required.

Change-Id: I435dc7ff10c9fb0edb8e40e6701608aa22136981
Signed-off-by: Abhijit Kulkarni <[email protected]>

msm/msm_drv.h

@@ -370,8 +370,8 @@ struct msm_roi_caps {
  * @dsc_4hsmerge_en:         Using DSC 4HS merge topology
  * @dsc_4hsmerge_padding     4HS merge DSC pair padding value in bytes
  * @dsc_4hsmerge_alignment   4HS merge DSC alignment value in bytes
- * @half_panel_pu            True For Dual dsc encoders if partial update is
- *                           enabled and only one encoder needs to be used,
+ * @half_panel_pu            True for single and dual dsc encoders if partial
+ *                           update sets the roi width to half of mode width
  *                           False in all other cases
  */
 struct msm_display_dsc_info {

msm/sde/sde_encoder_dce.c

@@ -299,13 +299,14 @@ static void _dce_vdc_pipe_cfg(struct sde_hw_vdc *hw_vdc,
 }
 
 static inline bool _dce_check_half_panel_update(int num_lm,
-		unsigned long affected_displays)
+			struct sde_encoder_virt *sde_enc)
 {
 	/**
 	 * partial update logic is currently supported only upto dual
 	 * pipe configurations.
 	 */
-	return (hweight_long(affected_displays) != num_lm);
+	return (sde_enc->cur_conn_roi.w <=
+			(sde_enc->cur_master->cached_mode.hdisplay / 2));
 }
 
 static int _dce_dsc_setup_single(struct sde_encoder_virt *sde_enc,
@@ -402,7 +403,7 @@ static int _dce_dsc_setup_helper(struct sde_encoder_virt *sde_enc,
 	const struct sde_rm_topology_def *def;
 	const struct sde_rect *roi;
 	enum sde_3d_blend_mode mode_3d;
-	bool half_panel_partial_update, dsc_merge, merge_3d, dsc_4hsmerge;
+	bool dsc_merge, merge_3d, dsc_4hsmerge;
 	bool disable_merge_3d = false;
 	int this_frame_slices;
 	int intf_ip_w, enc_ip_w;
@@ -427,12 +428,10 @@ static int _dce_dsc_setup_helper(struct sde_encoder_virt *sde_enc,
 	mode_3d = (num_lm > num_dsc) ? BLEND_3D_H_ROW_INT : BLEND_3D_NONE;
 	merge_3d = (mode_3d != BLEND_3D_NONE) ? true : false;
 
-	half_panel_partial_update = _dce_check_half_panel_update(num_lm,
-			affected_displays);
-	dsc->half_panel_pu = half_panel_partial_update;
-	dsc_merge = ((num_dsc > num_intf) && !half_panel_partial_update) ?
+	dsc->half_panel_pu = _dce_check_half_panel_update(num_lm, sde_enc);
+	dsc_merge = ((num_dsc > num_intf) && !dsc->half_panel_pu) ?
 			true : false;
-	disable_merge_3d = (merge_3d && half_panel_partial_update) ?
+	disable_merge_3d = (merge_3d && dsc->half_panel_pu) ?
 			false : true;
 	dsc_4hsmerge = (dsc_merge && num_dsc == 4 && num_intf == 1) ?
 			true : false;
@@ -457,9 +456,9 @@ static int _dce_dsc_setup_helper(struct sde_encoder_virt *sde_enc,
 	intf_ip_w = this_frame_slices * dsc->config.slice_width;
 	enc_ip_w = intf_ip_w;
 
-	if (!half_panel_partial_update)
+	if (!dsc->half_panel_pu)
 		intf_ip_w /= num_intf;
-	if (!half_panel_partial_update && (num_dsc > 1))
+	if (!dsc->half_panel_pu && (num_dsc > 1))
 		dsc_common_mode |= DSC_MODE_SPLIT_PANEL;
 	if (dsc_merge) {
 		dsc_common_mode |= DSC_MODE_MULTIPLEX;
@@ -481,8 +480,7 @@ static int _dce_dsc_setup_helper(struct sde_encoder_virt *sde_enc,
 	 * __is_ich_reset_override_needed should be called only after
 	 * updating pic dimension, mdss_panel_dsc_update_pic_dim.
 	 */
-	ich_res = _dce_dsc_ich_reset_override_needed(
-			(half_panel_partial_update && !merge_3d), dsc);
+	ich_res = _dce_dsc_ich_reset_override_needed(dsc->half_panel_pu, dsc);
 
 	SDE_DEBUG_DCE(sde_enc, "pic_w: %d pic_h: %d mode:%d\n",
 				roi->w, roi->h, dsc_common_mode);
@@ -491,7 +489,7 @@ static int _dce_dsc_setup_helper(struct sde_encoder_virt *sde_enc,
 		rc = _dce_dsc_setup_single(sde_enc, dsc, affected_displays, i,
 				roi, dsc_common_mode, merge_3d,
 				disable_merge_3d, mode_3d, dsc_4hsmerge,
-				half_panel_partial_update, ich_res);
+				dsc->half_panel_pu, ich_res);
 		if (rc)
 			break;
 	}
@@ -612,7 +610,7 @@ static int _dce_vdc_setup(struct sde_encoder_virt *sde_enc,
 	_dce_vdc_update_pic_dim(vdc, roi->w, roi->h);
 	merge_3d = (mode_3d != BLEND_3D_NONE) ? true : false;
 	half_panel_partial_update = _dce_check_half_panel_update(num_lm,
-		params->affected_displays);
+		sde_enc);
 
 	if (half_panel_partial_update && merge_3d)
 		disable_merge_3d = true;