msm: camera: isp: Add headers for CSID980

Add target headers for CSID 980.

CRs-Fixed: 3321317
Change-Id: I5edea2170268fb7a803947be8cba61ed86675694
Signed-off-by: Gaurav Jindal<[email protected]>
Signed-off-by: Li Sha Lim <[email protected]>
Signed-off-by: Ashish Bhimanpalliwar <[email protected]>
Signed-off-by: Mukund Madhusudan Atre <[email protected]>

drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c

@@ -13662,7 +13662,8 @@ static int cam_ife_hw_mgr_handle_csid_error(
 	/* Notify IFE/SFE devices, determine bus overflow */
 	if (err_type & (CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW |
 		CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW |
-		CAM_ISP_HW_ERROR_CSID_FRAME_SIZE))
+		CAM_ISP_HW_ERROR_CSID_FRAME_SIZE |
+		CAM_ISP_HW_ERROR_CSID_CAMIF_FRAME_DROP))
 		cam_ife_hw_mgr_check_and_notify_overflow(event_info,
 			ctx, &is_bus_overflow);
 

drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h

@@ -131,6 +131,7 @@ enum cam_isp_hw_err_type {
 	CAM_ISP_HW_ERROR_CSID_SENSOR_FRAME_DROP       = 0x00004000,
 	CAM_ISP_HW_ERROR_CSID_MISSING_EOT             = 0x00008000,
 	CAM_ISP_HW_ERROR_CSID_PKT_PAYLOAD_CORRUPTED   = 0x00010000,
+	CAM_ISP_HW_ERROR_CSID_CAMIF_FRAME_DROP        = 0x00020000,
 };
 
 /**

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid980.h

@@ -0,0 +1,1797 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CAM_IFE_CSID_980_H_
+#define _CAM_IFE_CSID_980_H_
+
+#include <linux/module.h>
+#include "cam_ife_csid_dev.h"
+#include "camera_main.h"
+#include "cam_ife_csid_common.h"
+#include "cam_ife_csid_hw_ver2.h"
+#include "cam_irq_controller.h"
+#include "cam_isp_hw_mgr_intf.h"
+
+#define CAM_CSID_VERSION_V980                 0x90080000
+
+static const struct cam_ife_csid_irq_desc cam_ife_csid_980_rx_irq_desc[][32] = {
+	{
+		{
+			.bitmask = BIT(0),
+			.desc = "DL0_EOT",
+		},
+		{
+			.bitmask = BIT(1),
+			.desc = "DL1_EOT",
+		},
+		{
+			.bitmask = BIT(2),
+			.desc = "DL2_EOT",
+		},
+		{
+			.bitmask = BIT(3),
+			.desc = "DL3_EOT",
+		},
+		{
+			.bitmask = BIT(4),
+			.desc = "DL0_SOT",
+		},
+		{
+			.bitmask = BIT(5),
+			.desc = "DL1_SOT",
+		},
+		{
+			.bitmask = BIT(6),
+			.desc = "DL2_SOT",
+		},
+		{
+			.bitmask = BIT(7),
+			.desc = "DL3_SOT",
+		},
+		{
+			.bitmask = BIT(8),
+			.desc = "DPHY_PH_ECC_SEC",
+		},
+		{
+			.bitmask = BIT(9),
+			.desc = "SENSOR_MODE_ID_CHANGE",
+		},
+		{
+			.bitmask = BIT(12),
+			.desc = "ERROR_DL0_EOT_LOST",
+		},
+		{
+			.bitmask = BIT(13),
+			.desc = "ERROR_DL1_EOT_LOST",
+		},
+		{
+			.bitmask = BIT(14),
+			.desc = "ERROR_DL2_EOT_LOST",
+		},
+		{
+			.bitmask = BIT(15),
+			.desc = "ERROR_DL3_EOT_LOST",
+		},
+		{
+			.bitmask = BIT(16),
+			.desc = "ERROR_DL0_SOT_LOST",
+		},
+		{
+			.bitmask = BIT(17),
+			.desc = "ERROR_DL1_SOT_LOST",
+		},
+		{
+			.bitmask = BIT(18),
+			.desc = "ERROR_DL2_SOT_LOST",
+		},
+		{
+			.bitmask = BIT(19),
+			.desc = "ERROR_DL3_SOT_LOST",
+		},
+		{
+			.bitmask = BIT(20),
+			.desc = "ERROR_DL0_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(21),
+			.desc = "ERROR_DL1_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(22),
+			.desc = "ERROR_DL2_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(23),
+			.desc = "ERROR_DL3_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(24),
+			.desc = "ERROR_CPHY_PH_CRC",
+		},
+		{
+			.bitmask = BIT(25),
+			.desc = "ERROR_PAYLOAD_CRC",
+		},
+		{
+			.bitmask = BIT(26),
+			.desc = "ERROR_DPHY_PH_ECC_DED",
+		},
+		{
+			.bitmask = BIT(27),
+			.desc = "ERROR_MMAPPED_VC_DT",
+		},
+		{
+			.bitmask = BIT(28),
+			.desc = "ERROR_UNMAPPED_VC_DT",
+		},
+		{
+			.bitmask = BIT(29),
+			.desc = "ERROR_STREAM_UNDERFLOW",
+		},
+		{
+			.bitmask = BIT(31),
+			.desc = "CSI2_RX_IRQ_STATUS_2",
+		},
+	},
+	{
+		{
+			.bitmask = BIT(0),
+			.desc = "LONG_PKT",
+		},
+		{
+			.bitmask = BIT(1),
+			.desc = "SHORT_PKT",
+		},
+		{
+			.bitmask = BIT(2),
+			.desc = "CPHY_PKT_HDR",
+		},
+		{
+			.bitmask = BIT(3),
+			.desc = "ERROR_ILLEGAL_PROGRAMMING_IRQ",
+		},
+	},
+};
+
+static const uint32_t cam_ife_csid_980_num_rx_irq_desc[] = {
+	ARRAY_SIZE(cam_ife_csid_980_rx_irq_desc[0]),
+	ARRAY_SIZE(cam_ife_csid_980_rx_irq_desc[1]),
+};
+
+static const struct cam_ife_csid_irq_desc cam_ife_csid_980_path_irq_desc[] = {
+	{
+		.bitmask = BIT(0),
+		.err_type = CAM_ISP_HW_ERROR_CSID_FATAL,
+		.desc = "ILLEGAL_PROGRAMMING",
+		.err_handler = cam_ife_csid_ver2_print_illegal_programming_irq_status,
+	},
+	{0},
+	{
+		.bitmask = BIT(2),
+		.desc = "ERROR_FIFO_OVERFLOW",
+	},
+	{
+		.bitmask = BIT(3),
+		.desc = "CAMIF_EOF",
+	},
+	{
+		.bitmask = BIT(4),
+		.desc = "CAMIF_SOF",
+	},
+	{0},
+	{0},
+	{0},
+	{0},
+	{
+		.bitmask = BIT(9),
+		.desc = "INFO_INPUT_EOF",
+	},
+	{
+		.bitmask = BIT(10),
+		.desc = "INFO_INPUT_EOL",
+	},
+	{
+		.bitmask = BIT(11),
+		.desc = "INFO_INPUT_SOL",
+	},
+	{
+		.bitmask = BIT(12),
+		.desc = "INFO_INPUT_SOF",
+	},
+	{
+		.bitmask = BIT(13),
+		.err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE,
+		.desc = "ERROR_PIX_COUNT",
+		.err_handler = cam_ife_csid_ver2_print_format_measure_info,
+	},
+	{
+		.bitmask = BIT(14),
+		.err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE,
+		.desc = "ERROR_LINE_COUNT",
+		.err_handler = cam_ife_csid_ver2_print_format_measure_info,
+	},
+	{
+		.bitmask = BIT(15),
+		.desc = "VCDT_GRP1_SEL",
+	},
+	{
+		.bitmask = BIT(16),
+		.desc = "VCDT_GRP0_SEL",
+	},
+	{
+		.bitmask = BIT(17),
+		.desc = "VCDT_GRP_CHANGE",
+	},
+	{
+		.bitmask = BIT(18),
+		.err_type = CAM_ISP_HW_ERROR_CSID_CAMIF_FRAME_DROP,
+		.desc = "CAMIF_FRAME_DROP",
+	},
+	{
+		.bitmask = BIT(19),
+		.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
+		.desc = "OVERFLOW_RECOVERY: Back pressure/output fifo ovrfl",
+	},
+	{
+		.bitmask = BIT(20),
+		.desc = "ERROR_REC_CCIF_VIOLATION From Camif",
+	},
+	{
+		.bitmask = BIT(21),
+		.desc = "CAMIF_EPOCH0",
+	},
+	{
+		.bitmask = BIT(22),
+		.desc = "CAMIF_EPOCH1",
+	},
+	{
+		.bitmask = BIT(23),
+		.desc = "RUP_DONE",
+	},
+	{
+		.bitmask = BIT(24),
+		.desc = "ILLEGAL_BATCH_ID",
+	},
+	{
+		.bitmask = BIT(25),
+		.desc = "BATCH_END_MISSING_VIOLATION",
+	},
+	{
+		.bitmask = BIT(26),
+		.desc = "UNBOUNDED_FRAME",
+	},
+	{
+		.bitmask = BIT(28),
+		.desc = "SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP",
+		.err_handler = cam_ife_csid_hw_ver2_mup_mismatch_handler,
+	},
+	{
+		.bitmask = BIT(29),
+		.desc = "CCIF_VIOLATION: Bad frame timings",
+	},
+};
+
+static const struct cam_ife_csid_top_irq_desc cam_ife_csid_980_top_irq_desc[][32] = {
+	{
+		{
+			.bitmask  = BIT(1),
+			.err_type = CAM_ISP_HW_ERROR_CSID_SENSOR_SWITCH_ERROR,
+			.err_name = "FATAL_SENSOR_SWITCHING_IRQ",
+			.desc = "Fatal Error during dynamically switching between 2 sensors",
+		},
+	},
+	{
+		{
+			.bitmask  = BIT(2),
+			.err_name = "ERROR_NO_VOTE_DN",
+			.desc = "vote_up is asserted before IDLE is encountered in a frame",
+		},
+		{
+			.bitmask  = BIT(3),
+			.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
+			.err_name = "ERROR_VOTE_UP_LATE",
+			.desc = "vote_up is asserted at the same time as an SOF",
+			.err_handler = cam_ife_csid_hw_ver2_drv_err_handler,
+		},
+		{
+			.bitmask  = BIT(4),
+			.err_type = CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW,
+			.err_name = "ERROR_RDI_LINE_BUFFER_CONFLICT",
+			.desc = "Two or more RDIs programmed to access the shared line buffer",
+			.err_handler = cam_ife_csid_hw_ver2_rdi_line_buffer_conflict_handler,
+		},
+	},
+};
+
+static const uint32_t cam_ife_csid_980_num_top_irq_desc[] = {
+	ARRAY_SIZE(cam_ife_csid_980_top_irq_desc[0]),
+	ARRAY_SIZE(cam_ife_csid_980_top_irq_desc[1]),
+};
+
+static struct cam_irq_register_set cam_ife_csid_980_irq_reg_set[CAM_IFE_CSID_IRQ_REG_MAX] = {
+	/* Top_1 */
+	{
+		.mask_reg_offset   = 0x00000088,
+		.clear_reg_offset  = 0x0000008C,
+		.status_reg_offset = 0x00000084,
+		.set_reg_offset    = 0x00000090,
+		.test_set_val      = BIT(0),
+		.test_sub_val      = BIT(0),
+	},
+	/* RX_1 */
+	{
+		.mask_reg_offset   = 0x000000B8,
+		.clear_reg_offset  = 0x000000BC,
+		.status_reg_offset = 0x000000B4,
+	},
+	/* RDI0 */
+	{
+		.mask_reg_offset   = 0x00000118,
+		.clear_reg_offset  = 0x0000011C,
+		.status_reg_offset = 0x00000114,
+	},
+	/* RDI1 */
+	{
+		.mask_reg_offset   = 0x00000128,
+		.clear_reg_offset  = 0x0000012C,
+		.status_reg_offset = 0x00000124,
+	},
+	/* RDI2 */
+	{
+		.mask_reg_offset   = 0x00000138,
+		.clear_reg_offset  = 0x0000013C,
+		.status_reg_offset = 0x00000134,
+	},
+	/* RDI3 */
+	{
+		.mask_reg_offset   = 0x00000148,
+		.clear_reg_offset  = 0x0000014C,
+		.status_reg_offset = 0x00000144,
+	},
+	/* RDI4 */
+	{
+		.mask_reg_offset   = 0x00000158,
+		.clear_reg_offset  = 0x0000015C,
+		.status_reg_offset = 0x00000154,
+	},
+	/* IPP_0 */
+	{
+		.mask_reg_offset   = 0x000000D8,
+		.clear_reg_offset  = 0x000000DC,
+		.status_reg_offset = 0x000000D4,
+	},
+	/* PPP */
+	{
+		.mask_reg_offset   = 0x00000108,
+		.clear_reg_offset  = 0x0000010C,
+		.status_reg_offset = 0x00000104,
+	},
+	/* UDI_0 */
+	{0},
+	/* UDI_1 */
+	{0},
+	/* UDI_2 */
+	{0},
+
+	/* Top_2 */
+	{
+		.mask_reg_offset   = 0x00000098,
+		.clear_reg_offset  = 0x0000009C,
+		.status_reg_offset = 0x00000094,
+		.set_reg_offset    = 0x00000090,
+	},
+	/* RX_2 */
+	{
+		.mask_reg_offset   = 0x000000C8,
+		.clear_reg_offset  = 0x000000CC,
+		.status_reg_offset = 0x000000C4,
+	},
+	/* IPP_1 */
+	{
+		.mask_reg_offset   = 0x000000E8,
+		.clear_reg_offset  = 0x000000EC,
+		.status_reg_offset = 0x000000E4,
+	},
+	/* IPP_2 */
+	{
+		.mask_reg_offset   = 0x000000F8,
+		.clear_reg_offset  = 0x000000FC,
+		.status_reg_offset = 0x000000F4,
+	},
+};
+
+static struct cam_irq_controller_reg_info cam_ife_csid_980_top_irq_reg_info[] = {
+	{
+	.num_registers = 1,
+	.irq_reg_set = &cam_ife_csid_980_irq_reg_set[CAM_IFE_CSID_IRQ_REG_TOP],
+	.global_irq_cmd_offset = 0x00000014,
+	.global_clear_bitmask  = 0x00000001,
+	.global_set_bitmask    = 0x00000010,
+	.clear_all_bitmask     = 0xFFFFFFFF,
+	},
+	{
+	.num_registers = 1,
+	.irq_reg_set = &cam_ife_csid_980_irq_reg_set[CAM_IFE_CSID_IRQ_REG_TOP_2],
+	.global_irq_cmd_offset = 0,
+	},
+
+};
+
+static struct cam_irq_controller_reg_info cam_ife_csid_980_rx_irq_reg_info[] = {
+	{
+	.num_registers = 1,
+	.irq_reg_set = &cam_ife_csid_980_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RX],
+	.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+	.num_registers = 1,
+	.irq_reg_set = &cam_ife_csid_980_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RX_2],
+	.global_irq_cmd_offset = 0, /* intentionally set to zero */
+
+	},
+};
+
+static struct cam_irq_controller_reg_info
+	cam_ife_csid_980_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_MAX] = {
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_980_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_0],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_980_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_1],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_980_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_2],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_980_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_3],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_980_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_4],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_980_irq_reg_set[CAM_IFE_CSID_IRQ_REG_IPP],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_980_irq_reg_set[CAM_IFE_CSID_IRQ_REG_PPP],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	/* UDI_0 */
+	{0},
+	/* UDI_1 */
+	{0},
+	/* UDI_2 */
+	{0},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_980_irq_reg_set[CAM_IFE_CSID_IRQ_REG_IPP_1],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_980_irq_reg_set[CAM_IFE_CSID_IRQ_REG_IPP_2],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+
+};
+
+static struct cam_irq_register_set cam_ife_csid_980_buf_done_irq_reg_set[1] = {
+	{
+		.mask_reg_offset   = 0x000000A8,
+		.clear_reg_offset  = 0x000000AC,
+		.status_reg_offset = 0x000000A4,
+	},
+};
+
+static struct cam_irq_controller_reg_info
+	cam_ife_csid_980_buf_done_irq_reg_info = {
+	.num_registers = 1,
+	.irq_reg_set = cam_ife_csid_980_buf_done_irq_reg_set,
+	.global_irq_cmd_offset  = 0, /* intentionally set to zero */
+};
+
+static struct cam_ife_csid_ver2_path_reg_info
+	cam_ife_csid_980_ipp_reg_info = {
+		.irq_status_addr                  = 0x00D4,
+		.irq_mask_addr                    = 0x00D8,
+		.irq_clear_addr                   = 0x00DC,
+		.irq_set_addr                     = 0x00E0,
+		.cfg0_addr                        = 0x0600,
+		.ctrl_addr                        = 0x0604,
+		.debug_clr_cmd_addr               = 0x0608,
+		.multi_vcdt_cfg0_addr             = 0x060C,
+		.cfg1_addr                        = 0,
+		.sparse_pd_extractor_cfg_addr     = 0,
+		.err_recovery_cfg0_addr           = 0,
+		.err_recovery_cfg1_addr           = 0,
+		.err_recovery_cfg2_addr           = 0,
+		.bin_pd_detect_cfg0_addr          = 0,
+		.bin_pd_detect_cfg1_addr          = 0,
+		.bin_pd_detect_cfg2_addr	      = 0,
+		.camif_frame_cfg_addr             = 0x0638,
+		.epoch_irq_cfg_addr               = 0,
+		.epoch0_subsample_ptrn_addr       = 0,
+		.epoch1_subsample_ptrn_addr       = 0,
+		.debug_rup_aup_status             = 0x0648,
+		.debug_camif_1_addr               = 0x064C,
+		.debug_camif_0_addr               = 0x0650,
+		.frm_drop_pattern_addr            = 0x0680,
+		.frm_drop_period_addr             = 0x0684,
+		.irq_subsample_pattern_addr       = 0x0688,
+		.irq_subsample_period_addr        = 0x068C,
+		.hcrop_addr                       = 0,
+		.vcrop_addr                       = 0,
+		.pix_drop_pattern_addr            = 0,
+		.pix_drop_period_addr             = 0,
+		.line_drop_pattern_addr           = 0,
+		.line_drop_period_addr            = 0,
+		.debug_halt_status_addr           = 0x0654,
+		.debug_misr_val0_addr             = 0x0658,
+		.debug_misr_val1_addr             = 0x065C,
+		.debug_misr_val2_addr             = 0x0660,
+		.debug_misr_val3_addr             = 0x0664,
+		.format_measure_cfg0_addr         = 0x0690,
+		.format_measure_cfg1_addr         = 0x0694,
+		.format_measure_cfg2_addr         = 0x0698,
+		.format_measure0_addr             = 0x069C,
+		.format_measure1_addr             = 0x06A0,
+		.format_measure2_addr             = 0x06A4,
+		.timestamp_curr0_sof_addr         = 0x06A8,
+		.timestamp_curr1_sof_addr         = 0x06AC,
+		.timestamp_perv0_sof_addr         = 0x06B0,
+		.timestamp_perv1_sof_addr         = 0x06B4,
+		.timestamp_curr0_eof_addr         = 0x06B8,
+		.timestamp_curr1_eof_addr         = 0x06BC,
+		.timestamp_perv0_eof_addr         = 0x06C0,
+		.timestamp_perv1_eof_addr         = 0x06C4,
+		.lut_bank_cfg_addr                = 0,
+		.batch_id_cfg0_addr               = 0x06CC,
+		.batch_id_cfg1_addr               = 0x06D0,
+		.batch_period_cfg_addr            = 0x06D4,
+		.batch_stream_id_cfg_addr         = 0x06D8,
+		.epoch0_cfg_batch_id0_addr        = 0x06DC,
+		.epoch1_cfg_batch_id0_addr        = 0x06E0,
+		.epoch0_cfg_batch_id1_addr        = 0x06E4,
+		.epoch1_cfg_batch_id1_addr        = 0x06E8,
+		.epoch0_cfg_batch_id2_addr        = 0x06EC,
+		.epoch1_cfg_batch_id2_addr        = 0x06F0,
+		.epoch0_cfg_batch_id3_addr        = 0x06F4,
+		.epoch1_cfg_batch_id3_addr        = 0x06F8,
+		.epoch0_cfg_batch_id4_addr        = 0x06FC,
+		.epoch1_cfg_batch_id4_addr        = 0x0700,
+		.epoch0_cfg_batch_id5_addr        = 0x0704,
+		.epoch1_cfg_batch_id5_addr        = 0x0708,
+		.secure_mask_cfg0                 = 0,
+		.path_batch_status                = 0x070C,
+		.path_frame_id                    = 0x0710,
+		.cfg2_addr                        = 0x0714,
+
+		/* configurations */
+		.resume_frame_boundary            = 1,
+		.binning_supported                = 0x7,
+		.capabilities                     = CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
+		.start_mode_internal              = 0x0,
+		.start_mode_global                = 0x1,
+		.start_mode_master                = 0x2,
+		.start_mode_slave                 = 0x3,
+		.sof_retiming_dis_shift           = 5,
+		.start_mode_shift                 = 2,
+		.start_master_sel_val             = 0,
+		.start_master_sel_shift           = 4,
+		.crop_v_en_shift_val              = 13,
+		.crop_h_en_shift_val              = 12,
+		.drop_v_en_shift_val              = 11,
+		.drop_h_en_shift_val              = 10,
+		.pix_store_en_shift_val           = 0,
+		.early_eof_en_shift_val           = 16,
+		.bin_h_en_shift_val               = 20,
+		.bin_v_en_shift_val               = 21,
+		.bin_en_shift_val                 = 18,
+		.bin_qcfa_en_shift_val            = 19,
+		.format_measure_en_shift_val      = 4,
+		.timestamp_en_shift_val           = 6,
+		.overflow_ctrl_en                 = 0,
+		.overflow_ctrl_mode_val           = 0x8,
+		.min_hbi_shift_val                = 4,
+		.start_master_sel_shift_val       = 4,
+		.bin_pd_en_shift_val              = 0,
+		.bin_pd_blk_w_shift_val           = 8,
+		.bin_pd_blk_h_shift_val           = 24,
+		.bin_pd_detect_x_offset_shift_val = 0,
+		.bin_pd_detect_x_end_shift_val    = 16,
+		.bin_pd_detect_y_offset_shift_val = 0,
+		.bin_pd_detect_y_end_shift_val    = 16,
+		.lut_bank_0_sel_val               = 0,
+		.lut_bank_1_sel_val               = 1,
+		.fatal_err_mask                   = 0x241c6001,
+		.non_fatal_err_mask               = 0x12000004,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
+		.rup_mask                         = 0x1,
+		.aup_mask                         = 0x1,
+		.rup_aup_set_mask                 = 0x1,
+		.top_irq_mask                     = {0x100,},
+		.epoch0_shift_val                 = 16,
+		.epoch1_shift_val                 = 0,
+};
+
+static struct cam_ife_csid_ver2_path_reg_info
+	cam_ife_csid_980_ipp_1_reg_info = {
+		.irq_status_addr                  = 0x00E4,
+		.irq_mask_addr                    = 0x00E8,
+		.irq_clear_addr                   = 0x00EC,
+		.irq_set_addr                     = 0x00F0,
+		.cfg0_addr                        = 0x0800,
+		.ctrl_addr                        = 0x0804,
+		.debug_clr_cmd_addr               = 0x0808,
+		.multi_vcdt_cfg0_addr             = 0x080C,
+		.cfg1_addr                        = 0,
+		.sparse_pd_extractor_cfg_addr     = 0,
+		.err_recovery_cfg0_addr           = 0,
+		.err_recovery_cfg1_addr           = 0,
+		.err_recovery_cfg2_addr           = 0,
+		.bin_pd_detect_cfg0_addr          = 0,
+		.bin_pd_detect_cfg1_addr          = 0,
+		.bin_pd_detect_cfg2_addr	      = 0,
+		.camif_frame_cfg_addr             = 0x0838,
+		.epoch_irq_cfg_addr               = 0,
+		.epoch0_subsample_ptrn_addr       = 0,
+		.epoch1_subsample_ptrn_addr       = 0,
+		.debug_rup_aup_status             = 0x0848,
+		.debug_camif_1_addr               = 0x084C,
+		.debug_camif_0_addr               = 0x0850,
+		.frm_drop_pattern_addr            = 0x0880,
+		.frm_drop_period_addr             = 0x0884,
+		.irq_subsample_pattern_addr       = 0x0888,
+		.irq_subsample_period_addr        = 0x088C,
+		.hcrop_addr                       = 0,
+		.vcrop_addr                       = 0,
+		.pix_drop_pattern_addr            = 0,
+		.pix_drop_period_addr             = 0,
+		.line_drop_pattern_addr           = 0,
+		.line_drop_period_addr            = 0,
+		.debug_halt_status_addr           = 0x0854,
+		.debug_misr_val0_addr             = 0x0858,
+		.debug_misr_val1_addr             = 0x085C,
+		.debug_misr_val2_addr             = 0x0860,
+		.debug_misr_val3_addr             = 0x0864,
+		.format_measure_cfg0_addr         = 0x0890,
+		.format_measure_cfg1_addr         = 0x0894,
+		.format_measure_cfg2_addr         = 0x0898,
+		.format_measure0_addr             = 0x089C,
+		.format_measure1_addr             = 0x08A0,
+		.format_measure2_addr             = 0x08A4,
+		.timestamp_curr0_sof_addr         = 0x08A8,
+		.timestamp_curr1_sof_addr         = 0x08AC,
+		.timestamp_perv0_sof_addr         = 0x08B0,
+		.timestamp_perv1_sof_addr         = 0x08B4,
+		.timestamp_curr0_eof_addr         = 0x08B8,
+		.timestamp_curr1_eof_addr         = 0x08BC,
+		.timestamp_perv0_eof_addr         = 0x08C0,
+		.timestamp_perv1_eof_addr         = 0x08C4,
+		.lut_bank_cfg_addr                = 0,
+		.batch_id_cfg0_addr               = 0x08CC,
+		.batch_id_cfg1_addr               = 0x08D0,
+		.batch_period_cfg_addr            = 0x08D4,
+		.batch_stream_id_cfg_addr         = 0x08D8,
+		.epoch0_cfg_batch_id0_addr        = 0x08DC,
+		.epoch1_cfg_batch_id0_addr        = 0x08E0,
+		.epoch0_cfg_batch_id1_addr        = 0x08E4,
+		.epoch1_cfg_batch_id1_addr        = 0x08E8,
+		.epoch0_cfg_batch_id2_addr        = 0x08EC,
+		.epoch1_cfg_batch_id2_addr        = 0x08F0,
+		.epoch0_cfg_batch_id3_addr        = 0x08F4,
+		.epoch1_cfg_batch_id3_addr        = 0x08F8,
+		.epoch0_cfg_batch_id4_addr        = 0x08FC,
+		.epoch1_cfg_batch_id4_addr        = 0x0900,
+		.epoch0_cfg_batch_id5_addr        = 0x0904,
+		.epoch1_cfg_batch_id5_addr        = 0x0908,
+		.secure_mask_cfg0                 = 0,
+		.path_batch_status                = 0x090C,
+		.path_frame_id                    = 0x0910,
+		.cfg2_addr                        = 0x0914,
+
+		/* configurations */
+		.resume_frame_boundary            = 1,
+		.binning_supported                = 0x7,
+		.capabilities                     = CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
+		.start_mode_internal              = 0x0,
+		.start_mode_global                = 0x1,
+		.start_mode_master                = 0x2,
+		.start_mode_slave                 = 0x3,
+		.sof_retiming_dis_shift           = 5,
+		.start_mode_shift                 = 2,
+		.start_master_sel_val             = 0,
+		.start_master_sel_shift           = 4,
+		.timestamp_en_shift_val           = 6,
+		.start_master_sel_shift_val       = 4,
+		.fatal_err_mask                   = 0x241c6001,
+		.non_fatal_err_mask               = 0x12000004,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
+		.rup_mask                         = 0x2,
+		.aup_mask                         = 0x2,
+		.rup_aup_set_mask                 = 0x1,
+		.top_irq_mask                     = {0x100,},
+};
+
+static struct cam_ife_csid_ver2_path_reg_info
+	cam_ife_csid_980_ipp_2_reg_info = {
+		.irq_status_addr                  = 0x00F4,
+		.irq_mask_addr                    = 0x00F8,
+		.irq_clear_addr                   = 0x00FC,
+		.irq_set_addr                     = 0x0100,
+		.cfg0_addr                        = 0x0A00,
+		.ctrl_addr                        = 0x0A04,
+		.debug_clr_cmd_addr               = 0x0A08,
+		.multi_vcdt_cfg0_addr             = 0x0A0C,
+		.cfg1_addr                        = 0,
+		.sparse_pd_extractor_cfg_addr     = 0,
+		.err_recovery_cfg0_addr           = 0,
+		.err_recovery_cfg1_addr           = 0,
+		.err_recovery_cfg2_addr           = 0,
+		.bin_pd_detect_cfg0_addr          = 0,
+		.bin_pd_detect_cfg1_addr          = 0,
+		.bin_pd_detect_cfg2_addr	      = 0,
+		.camif_frame_cfg_addr             = 0x0A38,
+		.epoch_irq_cfg_addr               = 0,
+		.epoch0_subsample_ptrn_addr       = 0,
+		.epoch1_subsample_ptrn_addr       = 0,
+		.debug_rup_aup_status             = 0x0A48,
+		.debug_camif_1_addr               = 0x0A4C,
+		.debug_camif_0_addr               = 0x0A50,
+		.frm_drop_pattern_addr            = 0x0A80,
+		.frm_drop_period_addr             = 0x0A84,
+		.irq_subsample_pattern_addr       = 0x0A88,
+		.irq_subsample_period_addr        = 0x0A8C,
+		.hcrop_addr                       = 0,
+		.vcrop_addr                       = 0,
+		.pix_drop_pattern_addr            = 0,
+		.pix_drop_period_addr             = 0,
+		.line_drop_pattern_addr           = 0,
+		.line_drop_period_addr            = 0,
+		.debug_halt_status_addr           = 0x0A54,
+		.debug_misr_val0_addr             = 0x0A58,
+		.debug_misr_val1_addr             = 0x0A5C,
+		.debug_misr_val2_addr             = 0x0A60,
+		.debug_misr_val3_addr             = 0x0A64,
+		.format_measure_cfg0_addr         = 0x0A90,
+		.format_measure_cfg1_addr         = 0x0A94,
+		.format_measure_cfg2_addr         = 0x0A98,
+		.format_measure0_addr             = 0x0A9C,
+		.format_measure1_addr             = 0x0AA0,
+		.format_measure2_addr             = 0x0AA4,
+		.timestamp_curr0_sof_addr         = 0x0AA8,
+		.timestamp_curr1_sof_addr         = 0x0AAC,
+		.timestamp_perv0_sof_addr         = 0x0AB0,
+		.timestamp_perv1_sof_addr         = 0x0AB4,
+		.timestamp_curr0_eof_addr         = 0x0AB8,
+		.timestamp_curr1_eof_addr         = 0x0ABC,
+		.timestamp_perv0_eof_addr         = 0x0AC0,
+		.timestamp_perv1_eof_addr         = 0x0AC4,
+		.lut_bank_cfg_addr                = 0,
+		.batch_id_cfg0_addr               = 0x0ACC,
+		.batch_id_cfg1_addr               = 0x0AD0,
+		.batch_period_cfg_addr            = 0x0AD4,
+		.batch_stream_id_cfg_addr         = 0x0AD8,
+		.epoch0_cfg_batch_id0_addr        = 0x0ADC,
+		.epoch1_cfg_batch_id0_addr        = 0x0AE0,
+		.epoch0_cfg_batch_id1_addr        = 0x0AE4,
+		.epoch1_cfg_batch_id1_addr        = 0x0AE8,
+		.epoch0_cfg_batch_id2_addr        = 0x0AEC,
+		.epoch1_cfg_batch_id2_addr        = 0x0AF0,
+		.epoch0_cfg_batch_id3_addr        = 0x0AF4,
+		.epoch1_cfg_batch_id3_addr        = 0x0AF8,
+		.epoch0_cfg_batch_id4_addr        = 0x0AFC,
+		.epoch1_cfg_batch_id4_addr        = 0x0B00,
+		.epoch0_cfg_batch_id5_addr        = 0x0B04,
+		.epoch1_cfg_batch_id5_addr        = 0x0B08,
+		.secure_mask_cfg0                 = 0,
+		.path_batch_status                = 0x0B0C,
+		.path_frame_id                    = 0x0B10,
+		.cfg2_addr                        = 0x0B14,
+
+		/* configurations */
+		.resume_frame_boundary            = 1,
+		.binning_supported                = 0x7,
+		.capabilities                     = CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
+		.start_mode_internal              = 0x0,
+		.start_mode_global                = 0x1,
+		.start_mode_master                = 0x2,
+		.start_mode_slave                 = 0x3,
+		.sof_retiming_dis_shift           = 5,
+		.start_mode_shift                 = 2,
+		.start_master_sel_val             = 0,
+		.start_master_sel_shift           = 4,
+		.timestamp_en_shift_val           = 6,
+		.start_master_sel_shift_val       = 4,
+		.fatal_err_mask                   = 0x241c6001,
+		.non_fatal_err_mask               = 0x12000004,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
+		.rup_mask                         = 0x4,
+		.aup_mask                         = 0x4,
+		.rup_aup_set_mask                 = 0x1,
+		.top_irq_mask                     = {0x100,},
+};
+
+
+static struct cam_ife_csid_ver2_path_reg_info
+	cam_ife_csid_980_ppp_reg_info = {
+		.irq_status_addr                  = 0x0104,
+		.irq_mask_addr                    = 0x0108,
+		.irq_clear_addr                   = 0x010C,
+		.irq_set_addr                     = 0x0110,
+		.cfg0_addr                        = 0x0C00,
+		.ctrl_addr                        = 0x0C04,
+		.debug_clr_cmd_addr               = 0x0C08,
+		.multi_vcdt_cfg0_addr             = 0x0C0C,
+		.cfg1_addr                        = 0x0C10,
+		.bin_cfg0_addr                    = 0x0C14,
+		.pix_store_cfg0_addr              = 0x0C18,
+		.sparse_pd_extractor_cfg_addr     = 0x0C1C,
+		.err_recovery_cfg0_addr           = 0,
+		.err_recovery_cfg1_addr           = 0,
+		.err_recovery_cfg2_addr           = 0,
+		.bin_pd_detect_cfg0_addr          = 0,
+		.bin_pd_detect_cfg1_addr          = 0,
+		.bin_pd_detect_cfg2_addr	      = 0,
+		.camif_frame_cfg_addr             = 0x0C38,
+		.epoch_irq_cfg_addr               = 0x0C3C,
+		.epoch0_subsample_ptrn_addr       = 0x0C40,
+		.epoch1_subsample_ptrn_addr       = 0x0C44,
+		.debug_rup_aup_status             = 0x0C48,
+		.debug_camif_1_addr               = 0x0C4C,
+		.debug_camif_0_addr               = 0x0C50,
+		.frm_drop_pattern_addr            = 0x0C80,
+		.frm_drop_period_addr             = 0x0C84,
+		.irq_subsample_pattern_addr       = 0x0C88,
+		.irq_subsample_period_addr        = 0x0C8C,
+		.hcrop_addr                       = 0x0C68,
+		.vcrop_addr                       = 0x0C6C,
+		.pix_drop_pattern_addr            = 0x0C70,
+		.pix_drop_period_addr             = 0x0C74,
+		.line_drop_pattern_addr           = 0x0C78,
+		.line_drop_period_addr            = 0x0C7C,
+		.debug_halt_status_addr           = 0x0C54,
+		.debug_misr_val0_addr             = 0x0C58,
+		.debug_misr_val1_addr             = 0x0C5C,
+		.debug_misr_val2_addr             = 0x0C60,
+		.debug_misr_val3_addr             = 0x0C64,
+		.format_measure_cfg0_addr         = 0x0C90,
+		.format_measure_cfg1_addr         = 0x0C94,
+		.format_measure_cfg2_addr         = 0x0C98,
+		.format_measure0_addr             = 0x0C9C,
+		.format_measure1_addr             = 0x0CA0,
+		.format_measure2_addr             = 0x0CA4,
+		.timestamp_curr0_sof_addr         = 0x0CA8,
+		.timestamp_curr1_sof_addr         = 0x0CAC,
+		.timestamp_perv0_sof_addr         = 0x0CB0,
+		.timestamp_perv1_sof_addr         = 0x0CB4,
+		.timestamp_curr0_eof_addr         = 0x0CB8,
+		.timestamp_curr1_eof_addr         = 0x0CBC,
+		.timestamp_perv0_eof_addr         = 0x0CC0,
+		.timestamp_perv1_eof_addr         = 0x0CC4,
+		.lut_bank_cfg_addr                = 0x0CC8,
+		.batch_id_cfg0_addr               = 0x0CCC,
+		.batch_id_cfg1_addr               = 0x0CD0,
+		.batch_period_cfg_addr            = 0x0CD4,
+		.batch_stream_id_cfg_addr         = 0x0CD8,
+		.epoch0_cfg_batch_id0_addr        = 0x0CDC,
+		.epoch1_cfg_batch_id0_addr        = 0x0CE0,
+		.epoch0_cfg_batch_id1_addr        = 0x0CE4,
+		.epoch1_cfg_batch_id1_addr        = 0x0CE8,
+		.epoch0_cfg_batch_id2_addr        = 0x0CEC,
+		.epoch1_cfg_batch_id2_addr        = 0x0CF0,
+		.epoch0_cfg_batch_id3_addr        = 0x0CF4,
+		.epoch1_cfg_batch_id3_addr        = 0x0CF8,
+		.epoch0_cfg_batch_id4_addr        = 0x0CFC,
+		.epoch1_cfg_batch_id4_addr        = 0x0D00,
+		.epoch0_cfg_batch_id5_addr        = 0x0D04,
+		.epoch1_cfg_batch_id5_addr        = 0x0D08,
+		.secure_mask_cfg0                 = 0,
+		.path_batch_status                = 0x0D0C,
+		.path_frame_id                    = 0x0D10,
+		.debug_sim_monitor                = 0x0D14,
+
+		/* configurations */
+		.capabilities                     = CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
+		.resume_frame_boundary            = 1,
+		.start_mode_shift                 = 2,
+		.start_mode_internal              = 0x0,
+		.start_mode_global                = 0x1,
+		.start_mode_master                = 0x2,
+		.start_mode_slave                 = 0x3,
+		.start_master_sel_val             = 3,
+		.start_master_sel_shift           = 4,
+		.binning_supported                = 0x1,
+		.bin_h_en_shift_val               = 18,
+		.bin_en_shift_val                 = 18,
+		.early_eof_en_shift_val           = 16,
+		.pix_store_en_shift_val           = 0,
+		.crop_v_en_shift_val              = 13,
+		.crop_h_en_shift_val              = 12,
+		.drop_v_en_shift_val              = 11,
+		.drop_h_en_shift_val              = 10,
+		.format_measure_en_shift_val      = 4,
+		.timestamp_en_shift_val           = 6,
+		.overflow_ctrl_en                 = 1,
+		.overflow_ctrl_mode_val           = 0x8,
+		.min_hbi_shift_val                = 1,
+		.start_master_sel_shift_val       = 4,
+		.lut_bank_0_sel_val               = 0,
+		.lut_bank_1_sel_val               = 1,
+		.fatal_err_mask                   = 0x241c6001,
+		.non_fatal_err_mask               = 0x12000004,
+		.rup_mask                         = 0x10000,
+		.aup_mask                         = 0x10000,
+		.rup_aup_set_mask                 = 0x1,
+		.top_irq_mask                     = {0x10,},
+		.epoch0_shift_val                 = 16,
+		.epoch1_shift_val                 = 0,
+		.sof_retiming_dis_shift           = 5,
+};
+
+static struct cam_ife_csid_ver2_path_reg_info
+	cam_ife_csid_980_rdi_0_reg_info = {
+		.irq_status_addr                  = 0x0114,
+		.irq_mask_addr                    = 0x0118,
+		.irq_clear_addr                   = 0x011C,
+		.irq_set_addr                     = 0x0120,
+		.cfg0_addr                        = 0x0E00,
+		.ctrl_addr                        = 0x0E04,
+		.debug_clr_cmd_addr               = 0x0E08,
+		.multi_vcdt_cfg0_addr             = 0x0E0C,
+		.cfg1_addr                        = 0x0E10,
+		.pix_store_cfg0_addr              = 0x0E14,
+		.err_recovery_cfg0_addr           = 0,
+		.err_recovery_cfg1_addr           = 0,
+		.err_recovery_cfg2_addr           = 0,
+		.debug_byte_cntr_ping_addr        = 0x0E24,
+		.debug_byte_cntr_pong_addr        = 0x0E28,
+		.camif_frame_cfg_addr             = 0x0E2C,
+		.epoch_irq_cfg_addr               = 0x0E30,
+		.epoch0_subsample_ptrn_addr       = 0x0E34,
+		.epoch1_subsample_ptrn_addr       = 0x0E38,
+		.debug_rup_aup_status             = 0x0E3C,
+		.debug_camif_1_addr               = 0x0E40,
+		.debug_camif_0_addr               = 0x0E44,
+		.frm_drop_pattern_addr            = 0x0E48,
+		.frm_drop_period_addr             = 0x0E4C,
+		.irq_subsample_pattern_addr       = 0x0E50,
+		.irq_subsample_period_addr        = 0x0E54,
+		.hcrop_addr                       = 0x0E58,
+		.vcrop_addr                       = 0x0E5C,
+		.pix_drop_pattern_addr            = 0x0E60,
+		.pix_drop_period_addr             = 0x0E64,
+		.line_drop_pattern_addr           = 0x0E68,
+		.line_drop_period_addr            = 0x0E6C,
+		.debug_halt_status_addr           = 0x0E74,
+		.debug_misr_val0_addr             = 0x0E78,
+		.debug_misr_val1_addr             = 0x0E7C,
+		.debug_misr_val2_addr             = 0x0E80,
+		.debug_misr_val3_addr             = 0x0E84,
+		.format_measure_cfg0_addr         = 0x0E88,
+		.format_measure_cfg1_addr         = 0x0E8C,
+		.format_measure_cfg2_addr         = 0x0E90,
+		.format_measure0_addr             = 0x0E94,
+		.format_measure1_addr             = 0x0E98,
+		.format_measure2_addr             = 0x0E9C,
+		.timestamp_curr0_sof_addr         = 0x0EA0,
+		.timestamp_curr1_sof_addr         = 0x0EA4,
+		.timestamp_perv0_sof_addr         = 0x0EA8,
+		.timestamp_perv1_sof_addr         = 0x0EAC,
+		.timestamp_curr0_eof_addr         = 0x0EB0,
+		.timestamp_curr1_eof_addr         = 0x0EB4,
+		.timestamp_perv0_eof_addr         = 0x0EB8,
+		.timestamp_perv1_eof_addr         = 0x0EBC,
+		.batch_id_cfg0_addr               = 0x0EC0,
+		.batch_id_cfg1_addr               = 0x0EC4,
+		.batch_period_cfg_addr            = 0x0EC8,
+		.batch_stream_id_cfg_addr         = 0x0ECC,
+		.epoch0_cfg_batch_id0_addr        = 0x0ED0,
+		.epoch1_cfg_batch_id0_addr        = 0x0ED4,
+		.epoch0_cfg_batch_id1_addr        = 0x0ED8,
+		.epoch1_cfg_batch_id1_addr        = 0x0EDC,
+		.epoch0_cfg_batch_id2_addr        = 0x0EE0,
+		.epoch1_cfg_batch_id2_addr        = 0x0EE4,
+		.epoch0_cfg_batch_id3_addr        = 0x0EE8,
+		.epoch1_cfg_batch_id3_addr        = 0x0EEC,
+		.epoch0_cfg_batch_id4_addr        = 0x0EF0,
+		.epoch1_cfg_batch_id4_addr        = 0x0EF4,
+		.epoch0_cfg_batch_id5_addr        = 0x0EF8,
+		.epoch1_cfg_batch_id5_addr        = 0x0EFC,
+		.secure_mask_cfg0                 = 0,
+		.path_batch_status                = 0x0F00,
+		.path_frame_id                    = 0x0F04,
+		.cfg2_addr                        = 0x0F08,
+		.debug_sim_monitor                = 0x0F0C,
+
+		/* configurations */
+		.resume_frame_boundary            = 1,
+		.overflow_ctrl_en                 = 1,
+		.capabilities                     = CAM_IFE_CSID_CAP_INPUT_LCR |
+							CAM_IFE_CSID_CAP_RDI_UNPACK_MSB |
+							CAM_IFE_CSID_CAP_LINE_SMOOTHING_IN_RDI |
+							CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
+		.start_mode_internal              = 0x0,
+		.start_mode_global                = 0x1,
+		.start_mode_shift                 = 2,
+		.overflow_ctrl_mode_val           = 0x8,
+		.offline_mode_supported           = 1,
+		.mipi_pack_supported              = 1,
+		.packing_fmt_shift_val            = 15,
+		.plain_alignment_shift_val        = 11,
+		.plain_fmt_shift_val              = 12,
+		.crop_v_en_shift_val              = 8,
+		.crop_h_en_shift_val              = 7,
+		.drop_v_en_shift_val              = 6,
+		.drop_h_en_shift_val              = 5,
+		.early_eof_en_shift_val           = 14,
+		.format_measure_en_shift_val      = 4,
+		.timestamp_en_shift_val           = 6,
+		.debug_byte_cntr_rst_shift_val    = 7,
+		.offline_mode_en_shift_val        = 2,
+		.ccif_violation_en                = 1,
+		.fatal_err_mask                   = 0x241c6001,
+		.non_fatal_err_mask               = 0x12000004,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
+		.rup_mask                         = 0x100,
+		.aup_mask                         = 0x100,
+		.rup_aup_set_mask                 = 0x1,
+		.top_irq_mask                     = {0x10000,},
+		.epoch0_shift_val                 = 16,
+		.epoch1_shift_val                 = 0,
+		.pix_store_en_shift_val           = 10,
+		.sof_retiming_dis_shift           = 5,
+		.default_out_format               = CAM_FORMAT_PLAIN16_16,
+};
+
+static struct cam_ife_csid_ver2_path_reg_info
+	cam_ife_csid_980_rdi_1_reg_info = {
+		.irq_status_addr                  = 0x0124,
+		.irq_mask_addr                    = 0x0128,
+		.irq_clear_addr                   = 0x012C,
+		.irq_set_addr                     = 0x0130,
+		.cfg0_addr                        = 0x1000,
+		.ctrl_addr                        = 0x1004,
+		.debug_clr_cmd_addr               = 0x1008,
+		.multi_vcdt_cfg0_addr             = 0x100C,
+		.cfg1_addr                        = 0x1010,
+		.pix_store_cfg0_addr              = 0x1014,
+		.err_recovery_cfg0_addr           = 0,
+		.err_recovery_cfg1_addr           = 0,
+		.err_recovery_cfg2_addr           = 0,
+		.debug_byte_cntr_ping_addr        = 0x1024,
+		.debug_byte_cntr_pong_addr        = 0x1028,
+		.camif_frame_cfg_addr             = 0x102C,
+		.epoch_irq_cfg_addr               = 0x1030,
+		.epoch0_subsample_ptrn_addr       = 0x1034,
+		.epoch1_subsample_ptrn_addr       = 0x1038,
+		.debug_rup_aup_status             = 0x103C,
+		.debug_camif_1_addr               = 0x1040,
+		.debug_camif_0_addr               = 0x1044,
+		.frm_drop_pattern_addr            = 0x1048,
+		.frm_drop_period_addr             = 0x104C,
+		.irq_subsample_pattern_addr       = 0x1050,
+		.irq_subsample_period_addr        = 0x1054,
+		.hcrop_addr                       = 0x1058,
+		.vcrop_addr                       = 0x105C,
+		.pix_drop_pattern_addr            = 0x1060,
+		.pix_drop_period_addr             = 0x1064,
+		.line_drop_pattern_addr           = 0x1068,
+		.line_drop_period_addr            = 0x106C,
+		.debug_halt_status_addr           = 0x1074,
+		.debug_misr_val0_addr             = 0x1078,
+		.debug_misr_val1_addr             = 0x107C,
+		.debug_misr_val2_addr             = 0x1080,
+		.debug_misr_val3_addr             = 0x1084,
+		.format_measure_cfg0_addr         = 0x1088,
+		.format_measure_cfg1_addr         = 0x108C,
+		.format_measure_cfg2_addr         = 0x1090,
+		.format_measure0_addr             = 0x1094,
+		.format_measure1_addr             = 0x1098,
+		.format_measure2_addr             = 0x109C,
+		.timestamp_curr0_sof_addr         = 0x10A0,
+		.timestamp_curr1_sof_addr         = 0x10A4,
+		.timestamp_perv0_sof_addr         = 0x10A8,
+		.timestamp_perv1_sof_addr         = 0x10AC,
+		.timestamp_curr0_eof_addr         = 0x10B0,
+		.timestamp_curr1_eof_addr         = 0x10B4,
+		.timestamp_perv0_eof_addr         = 0x10B8,
+		.timestamp_perv1_eof_addr         = 0x10BC,
+		.batch_id_cfg0_addr               = 0x10C0,
+		.batch_id_cfg1_addr               = 0x10C4,
+		.batch_period_cfg_addr            = 0x10C8,
+		.batch_stream_id_cfg_addr         = 0x10CC,
+		.epoch0_cfg_batch_id0_addr        = 0x10D0,
+		.epoch1_cfg_batch_id0_addr        = 0x10D4,
+		.epoch0_cfg_batch_id1_addr        = 0x10D8,
+		.epoch1_cfg_batch_id1_addr        = 0x10DC,
+		.epoch0_cfg_batch_id2_addr        = 0x10E0,
+		.epoch1_cfg_batch_id2_addr        = 0x10E4,
+		.epoch0_cfg_batch_id3_addr        = 0x10E8,
+		.epoch1_cfg_batch_id3_addr        = 0x10EC,
+		.epoch0_cfg_batch_id4_addr        = 0x10F0,
+		.epoch1_cfg_batch_id4_addr        = 0x10F4,
+		.epoch0_cfg_batch_id5_addr        = 0x10F8,
+		.epoch1_cfg_batch_id5_addr        = 0x10FC,
+		.secure_mask_cfg0                 = 0,
+		.path_batch_status                = 0x1100,
+		.path_frame_id                    = 0x1104,
+		.cfg2_addr                        = 0x1108,
+		.debug_sim_monitor                = 0x110C,
+
+		/* configurations */
+		.resume_frame_boundary            = 1,
+		.overflow_ctrl_en                 = 1,
+		.capabilities                     = CAM_IFE_CSID_CAP_INPUT_LCR |
+							CAM_IFE_CSID_CAP_RDI_UNPACK_MSB |
+							CAM_IFE_CSID_CAP_LINE_SMOOTHING_IN_RDI |
+							CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
+		.start_mode_internal              = 0x0,
+		.start_mode_global                = 0x1,
+		.start_mode_shift                 = 2,
+		.overflow_ctrl_mode_val           = 0x8,
+		.offline_mode_supported           = 1,
+		.mipi_pack_supported              = 1,
+		.packing_fmt_shift_val            = 15,
+		.plain_alignment_shift_val        = 11,
+		.plain_fmt_shift_val              = 12,
+		.crop_v_en_shift_val              = 8,
+		.crop_h_en_shift_val              = 7,
+		.drop_v_en_shift_val              = 6,
+		.drop_h_en_shift_val              = 5,
+		.early_eof_en_shift_val           = 14,
+		.format_measure_en_shift_val      = 4,
+		.timestamp_en_shift_val           = 6,
+		.debug_byte_cntr_rst_shift_val    = 7,
+		.offline_mode_en_shift_val        = 2,
+		.ccif_violation_en                = 1,
+		.fatal_err_mask                   = 0x241c6001,
+		.non_fatal_err_mask               = 0x12000004,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
+		.rup_mask                         = 0x200,
+		.aup_mask                         = 0x200,
+		.rup_aup_set_mask                 = 0x1,
+		.top_irq_mask                     = {0x20000,},
+		.epoch0_shift_val                 = 16,
+		.epoch1_shift_val                 = 0,
+		.pix_store_en_shift_val           = 10,
+		.sof_retiming_dis_shift           = 5,
+};
+
+static struct cam_ife_csid_ver2_path_reg_info
+	cam_ife_csid_980_rdi_2_reg_info = {
+		.irq_status_addr                  = 0x0134,
+		.irq_mask_addr                    = 0x0138,
+		.irq_clear_addr                   = 0x013C,
+		.irq_set_addr                     = 0x0140,
+		.cfg0_addr                        = 0x1200,
+		.ctrl_addr                        = 0x1204,
+		.debug_clr_cmd_addr               = 0x1208,
+		.multi_vcdt_cfg0_addr             = 0x120C,
+		.cfg1_addr                        = 0x1210,
+		.pix_store_cfg0_addr              = 0x1214,
+		.err_recovery_cfg0_addr           = 0,
+		.err_recovery_cfg1_addr           = 0,
+		.err_recovery_cfg2_addr           = 0,
+		.debug_byte_cntr_ping_addr        = 0x1224,
+		.debug_byte_cntr_pong_addr        = 0x1228,
+		.camif_frame_cfg_addr             = 0x122C,
+		.epoch_irq_cfg_addr               = 0x1230,
+		.epoch0_subsample_ptrn_addr       = 0x1234,
+		.epoch1_subsample_ptrn_addr       = 0x1238,
+		.debug_rup_aup_status             = 0x123C,
+		.debug_camif_1_addr               = 0x1240,
+		.debug_camif_0_addr               = 0x1244,
+		.frm_drop_pattern_addr            = 0x1248,
+		.frm_drop_period_addr             = 0x124C,
+		.irq_subsample_pattern_addr       = 0x1250,
+		.irq_subsample_period_addr        = 0x1254,
+		.hcrop_addr                       = 0x1258,
+		.vcrop_addr                       = 0x125C,
+		.pix_drop_pattern_addr            = 0x1260,
+		.pix_drop_period_addr             = 0x1264,
+		.line_drop_pattern_addr           = 0x1268,
+		.line_drop_period_addr            = 0x126C,
+		.debug_halt_status_addr           = 0x1274,
+		.debug_misr_val0_addr             = 0x1278,
+		.debug_misr_val1_addr             = 0x127C,
+		.debug_misr_val2_addr             = 0x1280,
+		.debug_misr_val3_addr             = 0x1284,
+		.format_measure_cfg0_addr         = 0x1288,
+		.format_measure_cfg1_addr         = 0x128C,
+		.format_measure_cfg2_addr         = 0x1290,
+		.format_measure0_addr             = 0x1294,
+		.format_measure1_addr             = 0x1298,
+		.format_measure2_addr             = 0x129C,
+		.timestamp_curr0_sof_addr         = 0x12A0,
+		.timestamp_curr1_sof_addr         = 0x12A4,
+		.timestamp_perv0_sof_addr         = 0x12A8,
+		.timestamp_perv1_sof_addr         = 0x12AC,
+		.timestamp_curr0_eof_addr         = 0x12B0,
+		.timestamp_curr1_eof_addr         = 0x12B4,
+		.timestamp_perv0_eof_addr         = 0x12B8,
+		.timestamp_perv1_eof_addr         = 0x12BC,
+		.batch_id_cfg0_addr               = 0x12C0,
+		.batch_id_cfg1_addr               = 0x12C4,
+		.batch_period_cfg_addr            = 0x12C8,
+		.batch_stream_id_cfg_addr         = 0x12CC,
+		.epoch0_cfg_batch_id0_addr        = 0x12D0,
+		.epoch1_cfg_batch_id0_addr        = 0x12D4,
+		.epoch0_cfg_batch_id1_addr        = 0x12D8,
+		.epoch1_cfg_batch_id1_addr        = 0x12DC,
+		.epoch0_cfg_batch_id2_addr        = 0x12E0,
+		.epoch1_cfg_batch_id2_addr        = 0x12E4,
+		.epoch0_cfg_batch_id3_addr        = 0x12E8,
+		.epoch1_cfg_batch_id3_addr        = 0x12EC,
+		.epoch0_cfg_batch_id4_addr        = 0x12F0,
+		.epoch1_cfg_batch_id4_addr        = 0x12F4,
+		.epoch0_cfg_batch_id5_addr        = 0x12F8,
+		.epoch1_cfg_batch_id5_addr        = 0x12FC,
+		.secure_mask_cfg0                 = 0,
+		.path_batch_status                = 0x1300,
+		.path_frame_id                    = 0x1304,
+		.cfg2_addr                        = 0x1308,
+		.debug_sim_monitor                = 0x130C,
+
+		/* configurations */
+		.resume_frame_boundary            = 1,
+		.overflow_ctrl_en                 = 1,
+		.capabilities                     = CAM_IFE_CSID_CAP_INPUT_LCR |
+							CAM_IFE_CSID_CAP_RDI_UNPACK_MSB |
+							CAM_IFE_CSID_CAP_LINE_SMOOTHING_IN_RDI |
+							CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
+		.start_mode_internal              = 0x0,
+		.start_mode_global                = 0x1,
+		.start_mode_shift                 = 2,
+		.overflow_ctrl_mode_val           = 0x8,
+		.offline_mode_supported           = 1,
+		.mipi_pack_supported              = 1,
+		.packing_fmt_shift_val            = 15,
+		.plain_alignment_shift_val        = 11,
+		.plain_fmt_shift_val              = 12,
+		.crop_v_en_shift_val              = 8,
+		.crop_h_en_shift_val              = 7,
+		.drop_v_en_shift_val              = 6,
+		.drop_h_en_shift_val              = 5,
+		.early_eof_en_shift_val           = 14,
+		.format_measure_en_shift_val      = 4,
+		.timestamp_en_shift_val           = 6,
+		.debug_byte_cntr_rst_shift_val    = 7,
+		.offline_mode_en_shift_val        = 2,
+		.ccif_violation_en                = 1,
+		.fatal_err_mask                   = 0x241c6001,
+		.non_fatal_err_mask               = 0x12000004,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
+		.rup_mask                         = 0x400,
+		.aup_mask                         = 0x400,
+		.rup_aup_set_mask                 = 0x1,
+		.top_irq_mask                     = {0x40000,},
+		.epoch0_shift_val                 = 16,
+		.epoch1_shift_val                 = 0,
+		.pix_store_en_shift_val           = 10,
+		.sof_retiming_dis_shift           = 5,
+
+};
+
+static struct cam_ife_csid_ver2_path_reg_info
+	cam_ife_csid_980_rdi_3_reg_info = {
+		.irq_status_addr                  = 0x0144,
+		.irq_mask_addr                    = 0x0148,
+		.irq_clear_addr                   = 0x014C,
+		.irq_set_addr                     = 0x0150,
+		.cfg0_addr                        = 0x1400,
+		.ctrl_addr                        = 0x1404,
+		.debug_clr_cmd_addr               = 0x1408,
+		.multi_vcdt_cfg0_addr             = 0x140C,
+		.cfg1_addr                        = 0x1410,
+		.debug_byte_cntr_ping_addr        = 0x1424,
+		.debug_byte_cntr_pong_addr        = 0x1428,
+		.camif_frame_cfg_addr             = 0x142C,
+		.epoch_irq_cfg_addr               = 0x1430,
+		.epoch0_subsample_ptrn_addr       = 0x1434,
+		.epoch1_subsample_ptrn_addr       = 0x1438,
+		.debug_rup_aup_status             = 0x143C,
+		.debug_camif_1_addr               = 0x1440,
+		.debug_camif_0_addr               = 0x1444,
+		.frm_drop_pattern_addr            = 0x1448,
+		.frm_drop_period_addr             = 0x144C,
+		.irq_subsample_pattern_addr       = 0x1450,
+		.irq_subsample_period_addr        = 0x1454,
+		.hcrop_addr                       = 0x1458,
+		.vcrop_addr                       = 0x145C,
+		.pix_drop_pattern_addr            = 0x1460,
+		.pix_drop_period_addr             = 0x1464,
+		.line_drop_pattern_addr           = 0x1468,
+		.line_drop_period_addr            = 0x146C,
+		.debug_halt_status_addr           = 0x1474,
+		.debug_misr_val0_addr             = 0x1478,
+		.debug_misr_val1_addr             = 0x147C,
+		.debug_misr_val2_addr             = 0x1480,
+		.debug_misr_val3_addr             = 0x1484,
+		.format_measure_cfg0_addr         = 0x1488,
+		.format_measure_cfg1_addr         = 0x148C,
+		.format_measure_cfg2_addr         = 0x1490,
+		.format_measure0_addr             = 0x1494,
+		.format_measure1_addr             = 0x1498,
+		.format_measure2_addr             = 0x149C,
+		.timestamp_curr0_sof_addr         = 0x14A0,
+		.timestamp_curr1_sof_addr         = 0x14A4,
+		.timestamp_perv0_sof_addr         = 0x14A8,
+		.timestamp_perv1_sof_addr         = 0x14AC,
+		.timestamp_curr0_eof_addr         = 0x14B0,
+		.timestamp_curr1_eof_addr         = 0x14B4,
+		.timestamp_perv0_eof_addr         = 0x14B8,
+		.timestamp_perv1_eof_addr         = 0x14BC,
+		.batch_id_cfg0_addr               = 0x14C0,
+		.batch_id_cfg1_addr               = 0x14C4,
+		.batch_period_cfg_addr            = 0x14C8,
+		.batch_stream_id_cfg_addr         = 0x14CC,
+		.epoch0_cfg_batch_id0_addr        = 0x14D0,
+		.epoch1_cfg_batch_id0_addr        = 0x14D4,
+		.epoch0_cfg_batch_id1_addr        = 0x14D8,
+		.epoch1_cfg_batch_id1_addr        = 0x14DC,
+		.epoch0_cfg_batch_id2_addr        = 0x14E0,
+		.epoch1_cfg_batch_id2_addr        = 0x14E4,
+		.epoch0_cfg_batch_id3_addr        = 0x14E8,
+		.epoch1_cfg_batch_id3_addr        = 0x14EC,
+		.epoch0_cfg_batch_id4_addr        = 0x14F0,
+		.epoch1_cfg_batch_id4_addr        = 0x14F4,
+		.epoch0_cfg_batch_id5_addr        = 0x14F8,
+		.epoch1_cfg_batch_id5_addr        = 0x14FC,
+		.secure_mask_cfg0                 = 0,
+		.path_batch_status                = 0x1500,
+		.path_frame_id                    = 0x1504,
+		.cfg2_addr                        = 0x1508,
+		.debug_sim_monitor                = 0x150C,
+
+		/* configurations */
+		.resume_frame_boundary            = 1,
+		.overflow_ctrl_en                 = 1,
+		.capabilities                     = CAM_IFE_CSID_CAP_INPUT_LCR |
+							CAM_IFE_CSID_CAP_RDI_UNPACK_MSB |
+							CAM_IFE_CSID_CAP_LINE_SMOOTHING_IN_RDI |
+							CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
+		.start_mode_internal              = 0x0,
+		.start_mode_global                = 0x1,
+		.start_mode_shift                 = 2,
+		.overflow_ctrl_mode_val           = 0x8,
+		.offline_mode_supported           = 1,
+		.mipi_pack_supported              = 1,
+		.packing_fmt_shift_val            = 15,
+		.plain_alignment_shift_val        = 11,
+		.plain_fmt_shift_val              = 12,
+		.crop_v_en_shift_val              = 8,
+		.crop_h_en_shift_val              = 7,
+		.drop_v_en_shift_val              = 6,
+		.drop_h_en_shift_val              = 5,
+		.early_eof_en_shift_val           = 14,
+		.format_measure_en_shift_val      = 4,
+		.timestamp_en_shift_val           = 6,
+		.debug_byte_cntr_rst_shift_val    = 7,
+		.offline_mode_en_shift_val        = 2,
+		.ccif_violation_en                = 1,
+		.fatal_err_mask                   = 0x241c6001,
+		.non_fatal_err_mask               = 0x12000004,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
+		.rup_mask                         = 0x800,
+		.aup_mask                         = 0x800,
+		.rup_aup_set_mask                 = 0x1,
+		.top_irq_mask                     = {0x80000,},
+		.epoch0_shift_val                 = 16,
+		.epoch1_shift_val                 = 0,
+		.pix_store_en_shift_val           = 10,
+		.sof_retiming_dis_shift           = 5,
+};
+
+static struct cam_ife_csid_ver2_path_reg_info
+	cam_ife_csid_980_rdi_4_reg_info = {
+		.irq_status_addr                  = 0x0154,
+		.irq_mask_addr                    = 0x0158,
+		.irq_clear_addr                   = 0x015C,
+		.irq_set_addr                     = 0x0160,
+		.cfg0_addr                        = 0x1600,
+		.ctrl_addr                        = 0x1604,
+		.debug_clr_cmd_addr               = 0x1608,
+		.multi_vcdt_cfg0_addr             = 0x160C,
+		.cfg1_addr                        = 0x1610,
+		.debug_byte_cntr_ping_addr        = 0x1624,
+		.debug_byte_cntr_pong_addr        = 0x1628,
+		.camif_frame_cfg_addr             = 0x162C,
+		.epoch_irq_cfg_addr               = 0x1630,
+		.epoch0_subsample_ptrn_addr       = 0x1634,
+		.epoch1_subsample_ptrn_addr       = 0x1638,
+		.debug_rup_aup_status             = 0x163C,
+		.debug_camif_1_addr               = 0x1640,
+		.debug_camif_0_addr               = 0x1644,
+		.frm_drop_pattern_addr            = 0x1648,
+		.frm_drop_period_addr             = 0x164C,
+		.irq_subsample_pattern_addr       = 0x1650,
+		.irq_subsample_period_addr        = 0x1654,
+		.hcrop_addr                       = 0x1658,
+		.vcrop_addr                       = 0x165C,
+		.pix_drop_pattern_addr            = 0x1660,
+		.pix_drop_period_addr             = 0x1664,
+		.line_drop_pattern_addr           = 0x1668,
+		.line_drop_period_addr            = 0x166C,
+		.debug_halt_status_addr           = 0x1674,
+		.debug_misr_val0_addr             = 0x1678,
+		.debug_misr_val1_addr             = 0x167C,
+		.debug_misr_val2_addr             = 0x1680,
+		.debug_misr_val3_addr             = 0x1684,
+		.format_measure_cfg0_addr         = 0x1688,
+		.format_measure_cfg1_addr         = 0x168C,
+		.format_measure_cfg2_addr         = 0x1690,
+		.format_measure0_addr             = 0x1694,
+		.format_measure1_addr             = 0x1698,
+		.format_measure2_addr             = 0x169C,
+		.timestamp_curr0_sof_addr         = 0x16A0,
+		.timestamp_curr1_sof_addr         = 0x16A4,
+		.timestamp_perv0_sof_addr         = 0x16A8,
+		.timestamp_perv1_sof_addr         = 0x16AC,
+		.timestamp_curr0_eof_addr         = 0x16B0,
+		.timestamp_curr1_eof_addr         = 0x16B4,
+		.timestamp_perv0_eof_addr         = 0x16B8,
+		.timestamp_perv1_eof_addr         = 0x16BC,
+		.batch_id_cfg0_addr               = 0x16C0,
+		.batch_id_cfg1_addr               = 0x16C4,
+		.batch_period_cfg_addr            = 0x16C8,
+		.batch_stream_id_cfg_addr         = 0x16CC,
+		.epoch0_cfg_batch_id0_addr        = 0x16D0,
+		.epoch1_cfg_batch_id0_addr        = 0x16D4,
+		.epoch0_cfg_batch_id1_addr        = 0x16D8,
+		.epoch1_cfg_batch_id1_addr        = 0x16DC,
+		.epoch0_cfg_batch_id2_addr        = 0x16E0,
+		.epoch1_cfg_batch_id2_addr        = 0x16E4,
+		.epoch0_cfg_batch_id3_addr        = 0x16E8,
+		.epoch1_cfg_batch_id3_addr        = 0x16EC,
+		.epoch0_cfg_batch_id4_addr        = 0x16F0,
+		.epoch1_cfg_batch_id4_addr        = 0x16F4,
+		.epoch0_cfg_batch_id5_addr        = 0x16F8,
+		.epoch1_cfg_batch_id5_addr        = 0x16FC,
+		.secure_mask_cfg0                 = 0,
+		.path_batch_status                = 0x1700,
+		.path_frame_id                    = 0x1704,
+		.cfg2_addr                        = 0x1708,
+		.debug_sim_monitor                = 0x170C,
+
+		/* configurations */
+		.resume_frame_boundary            = 1,
+		.overflow_ctrl_en                 = 1,
+		.capabilities                     = CAM_IFE_CSID_CAP_INPUT_LCR |
+							CAM_IFE_CSID_CAP_RDI_UNPACK_MSB |
+							CAM_IFE_CSID_CAP_LINE_SMOOTHING_IN_RDI |
+							CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
+		.start_mode_internal              = 0x0,
+		.start_mode_global                = 0x1,
+		.start_mode_shift                 = 2,
+		.overflow_ctrl_mode_val           = 0x8,
+		.offline_mode_supported           = 1,
+		.mipi_pack_supported              = 1,
+		.packing_fmt_shift_val            = 15,
+		.plain_alignment_shift_val        = 11,
+		.plain_fmt_shift_val              = 12,
+		.crop_v_en_shift_val              = 8,
+		.crop_h_en_shift_val              = 7,
+		.drop_v_en_shift_val              = 6,
+		.drop_h_en_shift_val              = 5,
+		.early_eof_en_shift_val           = 14,
+		.format_measure_en_shift_val      = 4,
+		.timestamp_en_shift_val           = 6,
+		.debug_byte_cntr_rst_shift_val    = 7,
+		.offline_mode_en_shift_val        = 2,
+		.ccif_violation_en                = 1,
+		.fatal_err_mask                   = 0x241c6001,
+		.non_fatal_err_mask               = 0x12000004,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
+		.rup_mask                         = 0x1000,
+		.aup_mask                         = 0x1000,
+		.rup_aup_set_mask                 = 0x1,
+		.top_irq_mask                     = {0x100000,},
+		.epoch0_shift_val                 = 16,
+		.epoch1_shift_val                 = 0,
+		.pix_store_en_shift_val           = 10,
+		.sof_retiming_dis_shift           = 5,
+};
+
+static struct cam_ife_csid_ver2_csi2_rx_reg_info
+	cam_ife_csid_980_csi2_reg_info = {
+		.irq_status_addr                 = {0x00B4, 0x00C4},
+		.irq_mask_addr                   = {0x00B8, 0x00C8},
+		.irq_clear_addr                  = {0x00BC, 0x00CC},
+		.irq_set_addr                    = {0x00C0, 0x00D0},
+		/*CSI2 rx control */
+		.cfg0_addr                       = 0x0400,
+		.cfg1_addr                       = 0x0404,
+		.capture_ctrl_addr               = 0x0408,
+		.rst_strobes_addr                = 0x040C,
+		.cap_unmap_long_pkt_hdr_0_addr   = 0x0410,
+		.cap_unmap_long_pkt_hdr_1_addr   = 0x0414,
+		.captured_short_pkt_0_addr       = 0x0418,
+		.captured_short_pkt_1_addr       = 0x041c,
+		.captured_long_pkt_0_addr        = 0x0420,
+		.captured_long_pkt_1_addr        = 0x0424,
+		.captured_long_pkt_ftr_addr      = 0x0428,
+		.captured_cphy_pkt_hdr_addr      = 0x042c,
+		.lane0_misr_addr                 = 0x0430,
+		.lane1_misr_addr                 = 0x0434,
+		.lane2_misr_addr                 = 0x0438,
+		.lane3_misr_addr                 = 0x043c,
+		.total_pkts_rcvd_addr            = 0x0440,
+		.stats_ecc_addr                  = 0x0444,
+		.total_crc_err_addr              = 0x0448,
+		.de_scramble_type3_cfg0_addr     = 0x044C,
+		.de_scramble_type3_cfg1_addr     = 0x0450,
+		.de_scramble_type2_cfg0_addr     = 0x0454,
+		.de_scramble_type2_cfg1_addr     = 0x0458,
+		.de_scramble_type1_cfg0_addr     = 0x045C,
+		.de_scramble_type1_cfg1_addr     = 0x0460,
+		.de_scramble_type0_cfg0_addr     = 0x0464,
+		.de_scramble_type0_cfg1_addr     = 0x0468,
+
+		.rst_done_shift_val              = 27,
+		.irq_mask_all                    = 0xFFFFFFF,
+		.misr_enable_shift_val           = 6,
+		.vc_mode_shift_val               = 2,
+		.capture_long_pkt_en_shift       = 0,
+		.capture_short_pkt_en_shift      = 1,
+		.capture_cphy_pkt_en_shift       = 2,
+		.capture_long_pkt_dt_shift       = 4,
+		.capture_long_pkt_vc_shift       = 10,
+		.capture_short_pkt_vc_shift      = 15,
+		.capture_cphy_pkt_dt_shift       = 20,
+		.capture_cphy_pkt_vc_shift       = 26,
+		.phy_num_mask                    = 0xf,
+		.vc_mask                         = 0x7C00000,
+		.dt_mask                         = 0x3f0000,
+		.wc_mask                         = 0xffff,
+		.vc_shift                        = 0x16,
+		.dt_shift                        = 0x10,
+		.wc_shift                        = 0,
+		.calc_crc_mask                   = 0xffff0000,
+		.expected_crc_mask               = 0xffff,
+		.calc_crc_shift                  = 0x10,
+		.ecc_correction_shift_en         = 0,
+		.lane_num_shift                  = 0,
+		.lane_cfg_shift                  = 4,
+		.phy_type_shift                  = 24,
+		.phy_num_shift                   = 20,
+		.tpg_mux_en_shift                = 27,
+		.tpg_num_sel_shift               = 28,
+		.phy_bist_shift_en               = 7,
+		.epd_mode_shift_en               = 8,
+		.eotp_shift_en                   = 9,
+		.dyn_sensor_switch_shift_en      = 10,
+		.rup_aup_latch_shift             = 11,
+		.rup_aup_latch_supported         = true,
+		.long_pkt_strobe_rst_shift       = 0,
+		.short_pkt_strobe_rst_shift      = 1,
+		.cphy_pkt_strobe_rst_shift       = 2,
+		.unmapped_pkt_strobe_rst_shift   = 3,
+		.fatal_err_mask                  = {0x38f00000,},
+		.part_fatal_err_mask             = {0xF0000,},
+		.non_fatal_err_mask              = {0x08000000,},
+		.top_irq_mask                    = {0x4,},
+};
+
+static struct cam_ife_csid_ver2_common_reg_info
+			cam_ife_csid_980_cmn_reg_info = {
+	.hw_version_addr                         = 0x0000,
+	.cfg0_addr                               = 0x0004,
+	.global_cmd_addr                         = 0x0008,
+	.reset_cfg_addr                          = 0x000C,
+	.reset_cmd_addr                          = 0x0010,
+	.irq_cmd_addr                            = 0x0014,
+	.rup_cmd_addr                            = 0x0018,
+	.aup_cmd_addr                            = 0x001C,
+	.rup_aup_cmd_addr                        = 0x0020,
+	.offline_cmd_addr                        = 0x0024,
+	.shdr_master_slave_cfg_addr              = 0x0028,
+	.multi_sensor_mode_addr                  = 0x002C,
+	.top_irq_status_addr                     = {0x0084,},
+	.top_irq_mask_addr                       = {0x0088,},
+	.top_irq_clear_addr                      = {0x008C,},
+	.top_irq_set_addr                        = {0x0090,},
+	.buf_done_irq_status_addr                = 0x00A4,
+	.buf_done_irq_mask_addr                  = 0x00A8,
+	.buf_done_irq_clear_addr                 = 0x00AC,
+	.buf_done_irq_set_addr                   = 0x00B0,
+	.test_bus_ctrl                           = 0x03F4,
+	.test_bus_debug                          = 0x03F8,
+	.drv_cfg0_addr                           = 0x0164,
+	.drv_cfg1_addr                           = 0x0168,
+	.drv_cfg2_addr                           = 0x016C,
+	.debug_drv_0_addr                        = 0x0170,
+	.debug_drv_1_addr                        = 0x0174,
+	.debug_sensor_hbi_irq_vcdt_addr          = 0x0180,
+	.debug_violation_addr                    = 0x03D4,
+	.debug_cfg_addr                          = 0x03E0,
+
+	/*configurations */
+	.major_version                           = 6,
+	.minor_version                           = 8,
+	.version_incr                            = 0,
+	.num_rdis                                = 5,
+	.num_pix                                 = 1,
+	.num_ppp                                 = 1,
+	.rst_done_shift_val                      = 1,
+	.path_en_shift_val                       = 31,
+	.dt_id_shift_val                         = 27,
+	.vc_shift_val                            = 22,
+	.vc_mask                                 = 0x1F,
+	.dt_shift_val                            = 16,
+	.dt_mask                                 = 0x3F,
+	.crop_shift_val                          = 16,
+	.decode_format_shift_val                 = 12,
+	.decode_format1_shift_val                = 16,
+	.decode_format1_supported                = true,
+	.decode_format_mask                      = 0xF,
+	.frame_id_decode_en_shift_val            = 1,
+	.multi_vcdt_vc1_shift_val                = 2,
+	.multi_vcdt_dt1_shift_val                = 7,
+	.multi_vcdt_en_shift_val                 = 0,
+	.timestamp_stb_sel_shift_val             = 8,
+	.vfr_en_shift_val                        = 0,
+	.mup_shift_val                           = 4,
+	.shdr_slave_ppp_shift                    = 16,
+	.shdr_slave_rdi2_shift                   = 18,
+	.shdr_slave_rdi1_shift                   = 17,
+	.shdr_master_rdi0_shift                  = 4,
+	.shdr_master_slave_en_shift              = 0,
+	.drv_en_shift                            = 0,
+	.drv_rup_en_shift                        = 0,
+	.early_eof_supported                     = 1,
+	.vfr_supported                           = 1,
+	.multi_vcdt_supported                    = 1,
+	.frame_id_dec_supported                  = 1,
+	.measure_en_hbi_vbi_cnt_mask             = 0xc,
+	.measure_pixel_line_en_mask              = 0x3,
+	.crop_pix_start_mask                     = 0x3fff,
+	.crop_pix_end_mask                       = 0xffff,
+	.crop_line_start_mask                    = 0x3fff,
+	.crop_line_end_mask                      = 0xffff,
+	.drop_supported                          = 1,
+	.ipp_irq_mask_all                        = 0x7FFF,
+	.rdi_irq_mask_all                        = 0x7FFF,
+	.ppp_irq_mask_all                        = 0xFFFF,
+	.top_err_irq_mask                        = {0x00000002,},
+	.rst_loc_path_only_val                   = 0x0,
+	.rst_loc_complete_csid_val               = 0x1,
+	.rst_mode_frame_boundary_val             = 0x0,
+	.rst_mode_immediate_val                  = 0x1,
+	.rst_cmd_hw_reset_complete_val           = 0x1,
+	.rst_cmd_sw_reset_complete_val           = 0x2,
+	.rst_cmd_irq_ctrl_only_val               = 0x4,
+	.timestamp_strobe_val                    = 0x2,
+	.top_reset_irq_mask                      = {0x1,},
+	.rst_location_shift_val                  = 4,
+	.rst_mode_shift_val                      = 0,
+	.epoch_factor                            = 50,
+	.global_reset                            = 1,
+	.rup_supported                           = 1,
+	.only_master_rup                         = 1,
+	.format_measure_height_mask_val          = 0xFFFF,
+	.format_measure_height_shift_val         = 0x10,
+	.format_measure_width_mask_val           = 0xFFFF,
+	.format_measure_width_shift_val          = 0x0,
+	.top_buf_done_irq_mask                   = 0x8,
+	.decode_format_payload_only              = 0xF,
+	.timestamp_enabled_in_cfg0               = true,
+	.camif_irq_support                       = true,
+	.capabilities                            = CAM_IFE_CSID_CAP_SPLIT_RUP_AUP,
+	.drv_rup_en_val_map = {
+		2, /*RDI0 */
+		3, /*RDI1 */
+		4, /*RDI2 */
+		5, /*RDI3 */
+		6, /*RDI4 */
+		0, /*IPP */
+		1, /*PPP */
+		0, /*UDI0 */
+		0, /*UDI1 */
+		0, /*UDI2 */
+	},
+	.drv_path_idle_en_val_map = {
+		BIT(4), /*CAM_ISP_PXL_PATH */
+		BIT(5), /*CAM_ISP_PPP_PATH */
+		0,      /* LCR not applicable */
+		BIT(6), /*CAM_ISP_RDI0_PATH */
+		BIT(7), /*CAM_ISP_RDI1_PATH */
+		BIT(8), /*CAM_ISP_RDI2_PATH */
+		BIT(9), /*CAM_ISP_RDI3_PATH */
+		BIT(10), /*CAM_ISP_RDI4_PATH */
+	},
+};
+
+struct cam_ife_csid_ver2_mc_reg_info
+	cam_ife_csid_980_ipp_mc_reg_info = {
+	.irq_comp_cfg0_addr                = 0x0178,
+	.ipp_src_ctxt_mask_shift           = 4,
+	.ipp_dst_ctxt_mask_shift           = 0,
+};
+
+static struct cam_ife_csid_ver2_reg_info cam_ife_csid_980_reg_info = {
+	.top_irq_reg_info      = cam_ife_csid_980_top_irq_reg_info,
+	.rx_irq_reg_info       = cam_ife_csid_980_rx_irq_reg_info,
+	.path_irq_reg_info     = {
+		&cam_ife_csid_980_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_0],
+		&cam_ife_csid_980_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_1],
+		&cam_ife_csid_980_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_2],
+		&cam_ife_csid_980_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_3],
+		&cam_ife_csid_980_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_4],
+		&cam_ife_csid_980_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_IPP],
+		&cam_ife_csid_980_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_PPP],
+		NULL,
+		NULL,
+		NULL,
+		&cam_ife_csid_980_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_IPP_1],
+		&cam_ife_csid_980_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_IPP_2],
+	},
+	.buf_done_irq_reg_info = &cam_ife_csid_980_buf_done_irq_reg_info,
+	.cmn_reg                              = &cam_ife_csid_980_cmn_reg_info,
+	.csi2_reg                             = &cam_ife_csid_980_csi2_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_IPP]   = &cam_ife_csid_980_ipp_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_IPP_1] = &cam_ife_csid_980_ipp_1_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_IPP_2] = &cam_ife_csid_980_ipp_2_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_PPP]   = &cam_ife_csid_980_ppp_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_0] = &cam_ife_csid_980_rdi_0_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_1] = &cam_ife_csid_980_rdi_1_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_2] = &cam_ife_csid_980_rdi_2_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_3] = &cam_ife_csid_980_rdi_3_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_4] = &cam_ife_csid_980_rdi_4_reg_info,
+	.ipp_mc_reg                           = &cam_ife_csid_980_ipp_mc_reg_info,
+	.need_top_cfg = 0x0,
+	.rx_irq_desc         = &cam_ife_csid_980_rx_irq_desc,
+	.path_irq_desc       = cam_ife_csid_980_path_irq_desc,
+	.top_irq_desc        = &cam_ife_csid_980_top_irq_desc,
+	.num_top_err_irqs    = cam_ife_csid_980_num_top_irq_desc,
+	.num_rx_err_irqs     = cam_ife_csid_980_num_rx_irq_desc,
+	.num_top_regs        = 1,
+	.num_rx_regs         = 1,
+};
+#endif /*_CAM_IFE_CSID_980_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.h

@@ -111,6 +111,10 @@ enum cam_ife_csid_irq_reg {
 	CAM_IFE_CSID_IRQ_REG_UDI_0,
 	CAM_IFE_CSID_IRQ_REG_UDI_1,
 	CAM_IFE_CSID_IRQ_REG_UDI_2,
+	CAM_IFE_CSID_IRQ_REG_TOP_2,
+	CAM_IFE_CSID_IRQ_REG_RX_2,
+	CAM_IFE_CSID_IRQ_REG_IPP_1,
+	CAM_IFE_CSID_IRQ_REG_IPP_2,
 	CAM_IFE_CSID_IRQ_REG_MAX,
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c

@@ -1700,7 +1700,7 @@ static int cam_ife_csid_ver2_parse_path_irq_status(
 
 	status = irq_status & err_mask;
 	while (status) {
-		if (status & 0x1 ) {
+		if ((csid_reg->path_irq_desc[bit_pos].bitmask != 0) && (status & 0x1)) {
 			CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len, "%s",
 				csid_reg->path_irq_desc[bit_pos].desc);
 			if (csid_reg->path_irq_desc[bit_pos].err_type)
@@ -1720,7 +1720,7 @@ static int cam_ife_csid_ver2_parse_path_irq_status(
 	status = irq_status & csid_hw->debug_info.path_mask;
 	bit_pos = 0;
 	while (status) {
-		if (status & 0x1)
+		if ((csid_reg->path_irq_desc[bit_pos].bitmask != 0) && (status & 0x1))
 			CAM_INFO(CAM_ISP, "CSID[%u] IRQ %s %s timestamp:[%lld.%09lld]",
 				csid_hw->hw_intf->hw_idx, irq_reg_tag[index],
 				csid_reg->path_irq_desc[bit_pos].desc,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h

@@ -360,6 +360,20 @@ struct cam_ife_csid_ver2_top_reg_info {
 	bool     sfe_pipeline_bypassed;
 };
 
+struct cam_ife_csid_ver2_mc_ctxt_reg_info {
+	uint32_t epoch_irq_cfg_addr;
+};
+
+struct cam_ife_csid_ver2_mc_bcast_reg_info {
+	uint32_t  pix_store_cfg_addr;
+};
+
+struct cam_ife_csid_ver2_mc_reg_info {
+	uint32_t           irq_comp_cfg0_addr;
+	uint32_t           ipp_src_ctxt_mask_shift;
+	uint32_t           ipp_dst_ctxt_mask_shift;
+};
+
 struct cam_ife_csid_ver2_path_reg_info {
 	uint32_t irq_status_addr;
 	uint32_t irq_mask_addr;
@@ -370,6 +384,8 @@ struct cam_ife_csid_ver2_path_reg_info {
 	uint32_t debug_clr_cmd_addr;
 	uint32_t multi_vcdt_cfg0_addr;
 	uint32_t cfg1_addr;
+	uint32_t bin_cfg0_addr;
+	uint32_t pix_store_cfg0_addr;
 	uint32_t sparse_pd_extractor_cfg_addr;
 	uint32_t err_recovery_cfg0_addr;
 	uint32_t err_recovery_cfg1_addr;
@@ -383,6 +399,7 @@ struct cam_ife_csid_ver2_path_reg_info {
 	uint32_t epoch_irq_cfg_addr;
 	uint32_t epoch0_subsample_ptrn_addr;
 	uint32_t epoch1_subsample_ptrn_addr;
+	uint32_t debug_rup_aup_status;
 	uint32_t debug_camif_1_addr;
 	uint32_t debug_camif_0_addr;
 	uint32_t frm_drop_pattern_addr;
@@ -402,6 +419,7 @@ struct cam_ife_csid_ver2_path_reg_info {
 	uint32_t debug_misr_val3_addr;
 	uint32_t format_measure_cfg0_addr;
 	uint32_t format_measure_cfg1_addr;
+	uint32_t format_measure_cfg2_addr;
 	uint32_t format_measure0_addr;
 	uint32_t format_measure1_addr;
 	uint32_t format_measure2_addr;
@@ -433,6 +451,8 @@ struct cam_ife_csid_ver2_path_reg_info {
 	uint32_t secure_mask_cfg0;
 	uint32_t path_batch_status;
 	uint32_t path_frame_id;
+	uint32_t cfg2_addr;
+	uint32_t debug_sim_monitor;
 
 	/*Shift Bit Configurations*/
 	uint32_t start_mode_master;
@@ -518,6 +538,7 @@ struct cam_ife_csid_ver2_common_reg_info {
 	uint32_t top_irq_mask_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX];
 	uint32_t top_irq_clear_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX];
 	uint32_t top_irq_set_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX];
+	uint32_t multi_sensor_mode_addr;
 	uint32_t irq_cmd_addr;
 	uint32_t buf_done_irq_status_addr;
 	uint32_t buf_done_irq_mask_addr;
@@ -530,6 +551,9 @@ struct cam_ife_csid_ver2_common_reg_info {
 	uint32_t drv_cfg2_addr;
 	uint32_t debug_drv_0_addr;
 	uint32_t debug_drv_1_addr;
+	uint32_t debug_sensor_hbi_irq_vcdt_addr;
+	uint32_t debug_violation_addr;
+	uint32_t debug_cfg_addr;
 
 	/*Shift Bit Configurations*/
 	uint32_t rst_done_shift_val;
@@ -695,6 +719,7 @@ struct cam_ife_csid_ver2_reg_info {
 	const struct cam_ife_csid_ver2_path_reg_info     *path_reg[
 						    CAM_IFE_PIX_PATH_RES_MAX];
 	const struct cam_ife_csid_ver2_top_reg_info      *top_reg;
+	const struct cam_ife_csid_ver2_mc_reg_info       *ipp_mc_reg;
 	const uint32_t                                    need_top_cfg;
 	const uint32_t                                    csid_cust_node_map[
 		    CAM_IFE_CSID_HW_NUM_MAX];

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite980.h

@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CAM_IFE_CSID_LITE_980_H_
+#define _CAM_IFE_CSID_LITE_980_H_
+
+#include "cam_ife_csid_lite880.h"
+
+static struct cam_ife_csid_ver2_reg_info cam_ife_csid_lite_980_reg_info = {
+	.top_irq_reg_info      = &cam_ife_csid_lite_880_top_irq_reg_info,
+	.rx_irq_reg_info       = &cam_ife_csid_lite_880_rx_irq_reg_info,
+	.path_irq_reg_info     = {
+		&cam_ife_csid_lite_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_0],
+		&cam_ife_csid_lite_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_1],
+		&cam_ife_csid_lite_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_2],
+		&cam_ife_csid_lite_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_3],
+		NULL,
+		&cam_ife_csid_lite_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_IPP],
+		},
+	.buf_done_irq_reg_info = &cam_ife_csid_lite_880_buf_done_irq_reg_info,
+	.cmn_reg               = &cam_ife_csid_lite_880_cmn_reg_info,
+	.csi2_reg              = &cam_ife_csid_lite_880_csi2_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_IPP]   = &cam_ife_csid_lite_880_ipp_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_PPP]   = NULL,
+	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_0] = &cam_ife_csid_lite_880_rdi_0_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_1] = &cam_ife_csid_lite_880_rdi_1_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_2] = &cam_ife_csid_lite_880_rdi_2_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_3] = &cam_ife_csid_lite_880_rdi_3_reg_info,
+	.need_top_cfg = 0,
+	.rx_irq_desc        = &cam_ife_csid_lite_880_rx_irq_desc,
+	.path_irq_desc      = cam_ife_csid_lite_880_path_irq_desc,
+	.top_irq_desc       = &cam_ife_csid_lite_880_top_irq_desc,
+	.num_top_err_irqs   = cam_ife_csid_lite_880_num_top_irq_desc,
+	.num_top_regs       = 1,
+	.num_rx_regs        = 1,
+};
+
+#endif /* _CAM_IFE_CSID_LITE_980_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_mod.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/module.h>
@@ -21,6 +21,7 @@
 #include "cam_ife_csid680_110.h"
 #include "cam_ife_csid780.h"
 #include "cam_ife_csid880.h"
+#include "cam_ife_csid980.h"
 
 #define CAM_CSID_DRV_NAME                    "csid"
 
@@ -84,6 +85,11 @@ static struct cam_ife_csid_core_info cam_ife_csid880_hw_info = {
 	.sw_version  = CAM_IFE_CSID_VER_2_0,
 };
 
+static struct cam_ife_csid_core_info cam_ife_csid980_hw_info = {
+	.csid_reg = &cam_ife_csid_980_reg_info,
+	.sw_version = CAM_IFE_CSID_VER_2_0,
+};
+
 static const struct of_device_id cam_ife_csid_dt_match[] = {
 
 	{
@@ -134,6 +140,10 @@ static const struct of_device_id cam_ife_csid_dt_match[] = {
 		.compatible = "qcom,csid880",
 		.data = &cam_ife_csid880_hw_info,
 	},
+	{
+		.compatible = "qcom,csid980",
+		.data = &cam_ife_csid980_hw_info,
+	},
 	{},
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h

@@ -29,6 +29,7 @@ enum cam_ife_csid_hw_irq_regs {
  */
 enum cam_ife_csid_top_irq_regs {
 	CAM_IFE_CSID_TOP_IRQ_STATUS_REG0,
+	CAM_IFE_CSID_TOP2_IRQ_STATUS_REG1,
 	CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX,
 };
 
@@ -37,6 +38,7 @@ enum cam_ife_csid_top_irq_regs {
  */
 enum cam_ife_csid_rx_irq_regs {
 	CAM_IFE_CSID_RX_IRQ_STATUS_REG0,
+	CAM_IFE_CSID_RX2_IRQ_STATUS_REG1,
 	CAM_IFE_CSID_RX_IRQ_STATUS_REG_MAX,
 };
 
@@ -65,6 +67,8 @@ enum cam_ife_pix_path_res_id {
 	CAM_IFE_PIX_PATH_RES_UDI_0,
 	CAM_IFE_PIX_PATH_RES_UDI_1,
 	CAM_IFE_PIX_PATH_RES_UDI_2,
+	CAM_IFE_PIX_PATH_RES_IPP_1,
+	CAM_IFE_PIX_PATH_RES_IPP_2,
 	CAM_IFE_PIX_PATH_RES_MAX,
 };