qcacmn: remove hal 9224v1

remove 9224v1 hal support and add 9224v1 crash if used

Change-Id: Icf22fa7b65d3d5b8eac44fd876316a4d35829756
CRs-Fixed: 3428599

hal/wifi3.0/hal_internal.h

@@ -1670,7 +1670,6 @@ void hal_qca8074_attach(struct hal_soc *hal_soc);
  */
 void hal_kiwi_attach(struct hal_soc *hal_soc);
 
-void hal_qcn9224v1_attach(struct hal_soc *hal_soc);
 void hal_qcn9224v2_attach(struct hal_soc *hal_soc);
 void hal_wcn6450_attach(struct hal_soc *hal_soc);
 

hal/wifi3.0/hal_srng.c

@@ -48,7 +48,6 @@ void hal_qca6490_attach(struct hal_soc *hal);
 void hal_qcn9000_attach(struct hal_soc *hal);
 #endif
 #ifdef QCA_WIFI_QCN9224
-void hal_qcn9224v1_attach(struct hal_soc *hal);
 void hal_qcn9224v2_attach(struct hal_soc *hal);
 #endif
 #if defined(QCA_WIFI_QCN6122) || defined(QCA_WIFI_QCN9160)
@@ -520,7 +519,7 @@ static void hal_target_based_configure(struct hal_soc *hal)
 		hal->use_register_windowing = true;
 		hal->static_window_map = true;
 		if (hal->version == 1)
-			hal_qcn9224v1_attach(hal);
+			qdf_assert_always(0);
 		else
 			hal_qcn9224v2_attach(hal);
 	break;

hal/wifi3.0/qcn9224/v1/hal_9224v1.c

@@ -1,571 +0,0 @@
-/*
- * Copyright (c) 2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-#include "hal_9224.h"
-
-struct hal_hw_srng_config hw_srng_table_9224v1[] = {
-	/* TODO: max_rings can populated by querying HW capabilities */
-	{ /* REO_DST */
-		.start_ring_id = HAL_SRNG_REO2SW1,
-		.max_rings = 8,
-		.entry_size = sizeof(struct reo_destination_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		.reg_start = {
-			HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
-				REO_REG_REG_BASE),
-			HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
-				REO_REG_REG_BASE)
-		},
-		.reg_size = {
-			HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
-				HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
-			HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
-				HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
-		},
-		.max_size =
-			HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
-			HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* REO_EXCEPTION */
-		/* Designating REO2SW0 ring as exception ring. This ring is
-		 * similar to other REO2SW rings though it is named as REO2SW0.
-		 * Any of theREO2SW rings can be used as exception ring.
-		 */
-		.start_ring_id = HAL_SRNG_REO2SW0,
-		.max_rings = 1,
-		.entry_size = sizeof(struct reo_destination_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		.reg_start = {
-			HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(
-				REO_REG_REG_BASE),
-			HWIO_REO_R2_REO2SW0_RING_HP_ADDR(
-				REO_REG_REG_BASE)
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {},
-		.max_size =
-			HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >>
-			HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* REO_REINJECT */
-		.start_ring_id = HAL_SRNG_SW2REO,
-		.max_rings = 4,
-		.entry_size = sizeof(struct reo_entrance_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-			HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
-				REO_REG_REG_BASE),
-			HWIO_REO_R2_SW2REO_RING_HP_ADDR(
-				REO_REG_REG_BASE)
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {
-			HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) -
-				HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0),
-			HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) -
-				HWIO_REO_R2_SW2REO_RING_HP_ADDR(0)
-		},
-		.max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
-				HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* REO_CMD */
-		.start_ring_id = HAL_SRNG_REO_CMD,
-		.max_rings = 1,
-		.entry_size = (sizeof(struct tlv_32_hdr) +
-			sizeof(struct reo_get_queue_stats)) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-			HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
-				REO_REG_REG_BASE),
-			HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
-				REO_REG_REG_BASE),
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {},
-		.max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
-			HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* REO_STATUS */
-		.start_ring_id = HAL_SRNG_REO_STATUS,
-		.max_rings = 1,
-		.entry_size = (sizeof(struct tlv_32_hdr) +
-			sizeof(struct reo_get_queue_stats_status)) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		.reg_start = {
-			HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
-				REO_REG_REG_BASE),
-			HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
-				REO_REG_REG_BASE),
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {},
-		.max_size =
-		HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
-			HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* TCL_DATA */
-		.start_ring_id = HAL_SRNG_SW2TCL1,
-		.max_rings = 6,
-		.entry_size = sizeof(struct tcl_data_cmd) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-			HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
-				MAC_TCL_REG_REG_BASE),
-			HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
-				MAC_TCL_REG_REG_BASE),
-		},
-		.reg_size = {
-			HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
-				HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
-			HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
-				HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
-		},
-		.max_size =
-			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
-			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* TCL_CMD/CREDIT */
-	  /* qca8074v2 and qcn9224 uses this ring for data commands */
-		.start_ring_id = HAL_SRNG_SW2TCL_CMD,
-		.max_rings = 1,
-		.entry_size = sizeof(struct tcl_data_cmd) >> 2,
-		.lmac_ring =  FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-			HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
-				MAC_TCL_REG_REG_BASE),
-			HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
-				MAC_TCL_REG_REG_BASE),
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {},
-		.max_size =
-		HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* TCL_STATUS */
-		.start_ring_id = HAL_SRNG_TCL_STATUS,
-		.max_rings = 1,
-		.entry_size = (sizeof(struct tlv_32_hdr) +
-			sizeof(struct tcl_status_ring)) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		.reg_start = {
-			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
-				MAC_TCL_REG_REG_BASE),
-			HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
-				MAC_TCL_REG_REG_BASE),
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {},
-		.max_size =
-			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
-			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* CE_SRC */
-		.start_ring_id = HAL_SRNG_CE_0_SRC,
-		.max_rings = 16,
-		.entry_size = sizeof(struct ce_src_desc) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-		HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(
-				WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
-		HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(
-				WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
-		},
-		.reg_size = {
-		WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
-		WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
-		WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
-		WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
-		},
-		.max_size =
-		HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* CE_DST */
-		.start_ring_id = HAL_SRNG_CE_0_DST,
-		.max_rings = 16,
-		.entry_size = 8 >> 2,
-		/*TODO: entry_size above should actually be
-		 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
-		 * of struct ce_dst_desc in HW header files
-		 */
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
-		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
-		HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
-		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
-		},
-		.reg_size = {
-		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
-		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
-		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
-		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
-		},
-		.max_size =
-		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* CE_DST_STATUS */
-		.start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
-		.max_rings = 16,
-		.entry_size = sizeof(struct ce_stat_desc) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		.reg_start = {
-		HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
-				WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
-		HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
-				WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
-		},
-		/* TODO: check destination status ring registers */
-		.reg_size = {
-		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
-		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
-		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
-		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
-		},
-		.max_size =
-	HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* WBM_IDLE_LINK */
-		.start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
-		.max_rings = 1,
-		.entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
-		HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE),
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {},
-		.max_size =
-		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* SW2WBM_RELEASE */
-		.start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
-		.max_rings = 2,
-		.entry_size = sizeof(struct wbm_release_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-		HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
-		HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
-		},
-		.reg_size = {
-		HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE) -
-		HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
-		HWIO_WBM_R2_SW1_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE) -
-		HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE)
-		},
-		.max_size =
-		HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* WBM2SW_RELEASE */
-		.start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
-		.max_rings = 8,
-		.entry_size = sizeof(struct wbm_release_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		.reg_start = {
-		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
-				WBM_REG_REG_BASE),
-		HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
-				WBM_REG_REG_BASE),
-		},
-		.reg_size = {
-		HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(
-				WBM_REG_REG_BASE) -
-		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
-				WBM_REG_REG_BASE),
-		HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(
-				WBM_REG_REG_BASE) -
-		HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
-				WBM_REG_REG_BASE),
-		},
-		.max_size =
-		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* RXDMA_BUF */
-		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
-#ifdef IPA_OFFLOAD
-		.max_rings = 3,
-#else
-		.max_rings = 3,
-#endif
-		.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE,
-	},
-	{ /* RXDMA_DST */
-		.start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
-		.max_rings = 0,
-		.entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/,
-		.lmac_ring =  TRUE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE,
-	},
-#ifdef QCA_MONITOR_2_0_SUPPORT
-	{ /* RXDMA_MONITOR_BUF */
-		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
-		.max_rings = 1,
-		.entry_size = sizeof(struct mon_ingress_ring) >> 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
-	},
-#else
-	{},
-#endif
-	{ /* RXDMA_MONITOR_STATUS */
-		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
-		.max_rings = 0,
-		.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE,
-	},
-#ifdef QCA_MONITOR_2_0_SUPPORT
-	{ /* RXDMA_MONITOR_DST */
-		.start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0,
-		.max_rings = 2,
-		.entry_size = sizeof(struct mon_destination_ring) >> 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
-	},
-#else
-	{},
-#endif
-	{ /* RXDMA_MONITOR_DESC */
-		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
-		.max_rings = 0,
-		.entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
-	},
-
-	{ /* DIR_BUF_RX_DMA_SRC */
-		.start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
-		/* one ring for spectral, one ring for cfr and
-		 * another one ring for txbf cv upload
-		 */
-		.max_rings = 3,
-		.entry_size = 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE,
-	},
-#ifdef WLAN_FEATURE_CIF_CFR
-	{ /* WIFI_POS_SRC */
-		.start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
-		.max_rings = 1,
-		.entry_size = sizeof(wmi_oem_dma_buf_release_entry)  >> 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
-	},
-#endif
-	{ /* REO2PPE */
-		.start_ring_id = HAL_SRNG_REO2PPE,
-		.max_rings = 1,
-		.entry_size = sizeof(struct reo_destination_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		.reg_start = {
-			HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(
-				REO_REG_REG_BASE),
-			HWIO_REO_R2_REO2PPE_RING_HP_ADDR(
-				REO_REG_REG_BASE),
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {},
-		.max_size =
-		HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK >>
-		HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT,
-	},
-	{ /* PPE2TCL */
-		.start_ring_id = HAL_SRNG_PPE2TCL1,
-		.max_rings = 1,
-		.entry_size = sizeof(struct tcl_entrance_from_ppe_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-			HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(
-				MAC_TCL_REG_REG_BASE),
-			HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(
-				MAC_TCL_REG_REG_BASE),
-		},
-		.reg_size = {},
-		.max_size =
-			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
-			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* PPE_RELEASE */
-		.start_ring_id = HAL_SRNG_WBM_PPE_RELEASE,
-		.max_rings = 1,
-		.entry_size = sizeof(struct wbm_release_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-		HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
-		HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
-		},
-		.reg_size = {},
-		.max_size =
-		HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-#ifdef QCA_MONITOR_2_0_SUPPORT
-	{ /* TX_MONITOR_BUF */
-		.start_ring_id = HAL_SRNG_SW2TXMON_BUF0,
-		.max_rings = 1,
-		.entry_size = sizeof(struct mon_ingress_ring) >> 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
-	},
-	{ /* TX_MONITOR_DST */
-		.start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0,
-		.max_rings = 2,
-		.entry_size = sizeof(struct mon_destination_ring) >> 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
-	},
-#else
-	{},
-	{},
-#endif
-	{ /* SW2RXDMA */
-		.start_ring_id = HAL_SRNG_SW2RXDMA_BUF0,
-		.max_rings = 3,
-		.entry_size = sizeof(struct reo_entrance_ring) >> 2,
-		.lmac_ring =  TRUE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
-		.dmac_cmn_ring = TRUE,
-	},
-};
-
-/**
- * hal_qcn9224v1_attach() - Attach 9224v1 target specific hal_soc ops,
- *			    offset and srng table
- * @hal_soc: HAL SoC context
- *
- * Return: void
- */
-void hal_qcn9224v1_attach(struct hal_soc *hal_soc)
-{
-	hal_soc->hw_srng_table = hw_srng_table_9224v1;
-
-	hal_srng_hw_reg_offset_init_generic(hal_soc);
-	hal_srng_hw_reg_offset_init_qcn9224(hal_soc);
-
-	hal_hw_txrx_default_ops_attach_be(hal_soc);
-	hal_hw_txrx_ops_attach_qcn9224(hal_soc);
-	if (hal_soc->static_window_map)
-		hal_write_window_register(hal_soc);
-	hal_soc->dmac_cmn_src_rxbuf_ring = true;
-}

hif/inc/hostdef.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2013-2016,2018-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -46,7 +46,6 @@ extern struct hostdef_s *QCA6018_HOSTDEF;
 extern struct hostdef_s *QCA5018_HOSTDEF;
 extern struct hostdef_s *QCN9000_HOSTDEF;
 extern struct hostdef_s *QCN6122_HOSTDEF;
-extern struct hostdef_s *QCN9224v1_HOSTDEF;
 extern struct hostdef_s *QCN9224_HOSTDEF;
 extern struct hostdef_s *QCA9574_HOSTDEF;
 extern struct hostdef_s *QCA5332_HOSTDEF;

hif/inc/targetdef.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2013-2016,2018-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -46,7 +46,6 @@ extern struct targetdef_s *QCA5018_TARGETDEF;
 extern struct targetdef_s *QCN9000_TARGETDEF;
 extern struct targetdef_s *QCN6122_TARGETDEF;
 extern struct targetdef_s *KIWI_TARGETdef;
-extern struct targetdef_s *QCN9224v1_TARGETDEF;
 extern struct targetdef_s *QCN9224_TARGETDEF;
 extern struct targetdef_s *QCA9574_TARGETDEF;
 extern struct targetdef_s *QCA5332_TARGETDEF;
@@ -72,7 +71,6 @@ extern struct ce_reg_def *QCA5018_CE_TARGETDEF;
 extern struct ce_reg_def *QCN9000_CE_TARGETDEF;
 extern struct ce_reg_def *QCN6122_CE_TARGETDEF;
 extern struct ce_reg_def *KIWI_CE_TARGETdef;
-extern struct ce_reg_def *QCN9224v1_CE_TARGETDEF;
 extern struct ce_reg_def *QCN9224_CE_TARGETDEF;
 extern struct ce_reg_def *QCA9574_CE_TARGETDEF;
 extern struct ce_reg_def *QCA5332_CE_TARGETDEF;

hif/src/qcn9224v1def.c

@@ -1,234 +0,0 @@
-/*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include "qdf_module.h"
-
-#if defined(QCN9224_HEADERS_DEF)
-
-#undef UMAC
-#define WLAN_HEADERS 1
-
-#include "wcss_version.h"
-#include "wcss_seq_hwiobase.h"
-#include "wfss_ce_reg_seq_hwioreg.h"
-
-#define MISSING 0
-
-#define SOC_RESET_CONTROL_OFFSET MISSING
-#define GPIO_PIN0_OFFSET                        MISSING
-#define GPIO_PIN1_OFFSET                        MISSING
-#define GPIO_PIN0_CONFIG_MASK                   MISSING
-#define GPIO_PIN1_CONFIG_MASK                   MISSING
-#define LOCAL_SCRATCH_OFFSET 0x18
-#define GPIO_PIN10_OFFSET MISSING
-#define GPIO_PIN11_OFFSET MISSING
-#define GPIO_PIN12_OFFSET MISSING
-#define GPIO_PIN13_OFFSET MISSING
-#define MBOX_BASE_ADDRESS MISSING
-#define INT_STATUS_ENABLE_ERROR_LSB MISSING
-#define INT_STATUS_ENABLE_ERROR_MASK MISSING
-#define INT_STATUS_ENABLE_CPU_LSB MISSING
-#define INT_STATUS_ENABLE_CPU_MASK MISSING
-#define INT_STATUS_ENABLE_COUNTER_LSB MISSING
-#define INT_STATUS_ENABLE_COUNTER_MASK MISSING
-#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
-#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
-#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
-#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
-#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
-#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
-#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
-#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
-#define INT_STATUS_ENABLE_ADDRESS MISSING
-#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
-#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
-#define HOST_INT_STATUS_ADDRESS MISSING
-#define CPU_INT_STATUS_ADDRESS MISSING
-#define ERROR_INT_STATUS_ADDRESS MISSING
-#define ERROR_INT_STATUS_WAKEUP_MASK MISSING
-#define ERROR_INT_STATUS_WAKEUP_LSB MISSING
-#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
-#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
-#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
-#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
-#define COUNT_DEC_ADDRESS MISSING
-#define HOST_INT_STATUS_CPU_MASK MISSING
-#define HOST_INT_STATUS_CPU_LSB MISSING
-#define HOST_INT_STATUS_ERROR_MASK MISSING
-#define HOST_INT_STATUS_ERROR_LSB MISSING
-#define HOST_INT_STATUS_COUNTER_MASK MISSING
-#define HOST_INT_STATUS_COUNTER_LSB MISSING
-#define RX_LOOKAHEAD_VALID_ADDRESS MISSING
-#define WINDOW_DATA_ADDRESS MISSING
-#define WINDOW_READ_ADDR_ADDRESS MISSING
-#define WINDOW_WRITE_ADDR_ADDRESS MISSING
-/* GPIO Register */
-#define GPIO_ENABLE_W1TS_LOW_ADDRESS            MISSING
-#define GPIO_PIN0_CONFIG_LSB                    MISSING
-#define GPIO_PIN0_PAD_PULL_LSB                  MISSING
-#define GPIO_PIN0_PAD_PULL_MASK                 MISSING
-/* SI reg */
-#define SI_CONFIG_ERR_INT_MASK                  MISSING
-#define SI_CONFIG_ERR_INT_LSB                   MISSING
-
-#define RTC_SOC_BASE_ADDRESS MISSING
-#define RTC_WMAC_BASE_ADDRESS MISSING
-#define SOC_CORE_BASE_ADDRESS MISSING
-#define WLAN_MAC_BASE_ADDRESS MISSING
-#define GPIO_BASE_ADDRESS MISSING
-#define ANALOG_INTF_BASE_ADDRESS MISSING
-#define CE0_BASE_ADDRESS MISSING
-#define CE1_BASE_ADDRESS MISSING
-#define CE_COUNT 16
-#define CE_WRAPPER_BASE_ADDRESS MISSING
-#define SI_BASE_ADDRESS MISSING
-#define DRAM_BASE_ADDRESS MISSING
-
-#define WLAN_SYSTEM_SLEEP_DISABLE_LSB MISSING
-#define WLAN_SYSTEM_SLEEP_DISABLE_MASK MISSING
-#define CLOCK_CONTROL_OFFSET MISSING
-#define CLOCK_CONTROL_SI0_CLK_MASK MISSING
-#define RESET_CONTROL_SI0_RST_MASK MISSING
-#define WLAN_RESET_CONTROL_OFFSET MISSING
-#define WLAN_RESET_CONTROL_COLD_RST_MASK MISSING
-#define WLAN_RESET_CONTROL_WARM_RST_MASK MISSING
-#define CPU_CLOCK_OFFSET MISSING
-
-#define CPU_CLOCK_STANDARD_LSB MISSING
-#define CPU_CLOCK_STANDARD_MASK MISSING
-#define LPO_CAL_ENABLE_LSB MISSING
-#define LPO_CAL_ENABLE_MASK MISSING
-#define WLAN_SYSTEM_SLEEP_OFFSET MISSING
-
-#define SOC_CHIP_ID_ADDRESS	  MISSING
-#define SOC_CHIP_ID_REVISION_MASK MISSING
-#define SOC_CHIP_ID_REVISION_LSB  MISSING
-#define SOC_CHIP_ID_REVISION_MSB  MISSING
-
-#define FW_IND_EVENT_PENDING MISSING
-#define FW_IND_INITIALIZED MISSING
-
-#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
-#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
-#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
-#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
-#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB  MISSING
-#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB  MISSING
-#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB  MISSING
-#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB  MISSING
-
-#define SR_WR_INDEX_ADDRESS MISSING
-#define DST_WATERMARK_ADDRESS MISSING
-
-#define DST_WR_INDEX_ADDRESS MISSING
-#define SRC_WATERMARK_ADDRESS MISSING
-#define SRC_WATERMARK_LOW_MASK MISSING
-#define SRC_WATERMARK_HIGH_MASK MISSING
-#define DST_WATERMARK_LOW_MASK MISSING
-#define DST_WATERMARK_HIGH_MASK MISSING
-#define CURRENT_SRRI_ADDRESS MISSING
-#define CURRENT_DRRI_ADDRESS MISSING
-#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK MISSING
-#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK MISSING
-#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK MISSING
-#define HOST_IS_DST_RING_LOW_WATERMARK_MASK MISSING
-#define HOST_IS_ADDRESS MISSING
-#define MISC_IS_ADDRESS MISSING
-#define HOST_IS_COPY_COMPLETE_MASK MISSING
-#define CE_WRAPPER_BASE_ADDRESS MISSING
-#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS MISSING
-#define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING
-#define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING
-
-#define HOST_IE_ADDRESS \
-	HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
-		WFSS_CE_COMMON_REG_REG_BASE)
-#define HOST_IE_REG1_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT
-#define HOST_IE_ADDRESS_2 \
-	HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(\
-		WFSS_CE_COMMON_REG_REG_BASE)
-#define HOST_IE_REG2_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT
-#define HOST_IE_ADDRESS_3 \
-	HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
-		WFSS_CE_COMMON_REG_REG_BASE)
-#define HOST_IE_REG3_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT
-
-#define HOST_IE_COPY_COMPLETE_MASK MISSING
-#define SR_BA_ADDRESS MISSING
-#define SR_BA_ADDRESS_HIGH MISSING
-#define SR_SIZE_ADDRESS MISSING
-#define CE_CTRL1_ADDRESS MISSING
-#define CE_CTRL1_DMAX_LENGTH_MASK MISSING
-#define DR_BA_ADDRESS MISSING
-#define DR_BA_ADDRESS_HIGH MISSING
-#define DR_SIZE_ADDRESS MISSING
-#define CE_CMD_REGISTER MISSING
-#define CE_MSI_ADDRESS MISSING
-#define CE_MSI_ADDRESS_HIGH MISSING
-#define CE_MSI_DATA MISSING
-#define CE_MSI_ENABLE_BIT MISSING
-#define MISC_IE_ADDRESS MISSING
-#define MISC_IS_AXI_ERR_MASK MISSING
-#define MISC_IS_DST_ADDR_ERR_MASK MISSING
-#define MISC_IS_SRC_LEN_ERR_MASK MISSING
-#define MISC_IS_DST_MAX_LEN_VIO_MASK MISSING
-#define MISC_IS_DST_RING_OVERFLOW_MASK MISSING
-#define MISC_IS_SRC_RING_OVERFLOW_MASK MISSING
-#define SRC_WATERMARK_LOW_LSB MISSING
-#define SRC_WATERMARK_HIGH_LSB MISSING
-#define DST_WATERMARK_LOW_LSB MISSING
-#define DST_WATERMARK_HIGH_LSB MISSING
-#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK MISSING
-#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB MISSING
-#define CE_CTRL1_DMAX_LENGTH_LSB MISSING
-#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK MISSING
-#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK MISSING
-#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB MISSING
-#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB MISSING
-#define CE_CTRL1_IDX_UPD_EN_MASK MISSING
-#define CE_WRAPPER_DEBUG_OFFSET MISSING
-#define CE_WRAPPER_DEBUG_SEL_MSB MISSING
-#define CE_WRAPPER_DEBUG_SEL_LSB MISSING
-#define CE_WRAPPER_DEBUG_SEL_MASK MISSING
-#define CE_DEBUG_OFFSET MISSING
-#define CE_DEBUG_SEL_MSB MISSING
-#define CE_DEBUG_SEL_LSB MISSING
-#define CE_DEBUG_SEL_MASK MISSING
-#define CE0_BASE_ADDRESS MISSING
-#define CE1_BASE_ADDRESS MISSING
-#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES MISSING
-#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS MISSING
-
-#define QCN9224v1_BOARD_DATA_SZ MISSING
-#define QCN9224v1_BOARD_EXT_DATA_SZ MISSING
-
-#define MY_TARGET_DEF QCN9224v1_TARGETDEF
-#define MY_HOST_DEF QCN9224v1_HOSTDEF
-#define MY_CEREG_DEF QCN9224v1_CE_TARGETDEF
-#define MY_TARGET_BOARD_DATA_SZ QCN9224v1_BOARD_DATA_SZ
-#define MY_TARGET_BOARD_EXT_DATA_SZ QCN9224v1_BOARD_EXT_DATA_SZ
-#include "targetdef.h"
-#include "hostdef.h"
-qdf_export_symbol(QCN9224v1_CE_TARGETDEF);
-#else
-#include "common_drv.h"
-#include "targetdef.h"
-#include "hostdef.h"
-struct targetdef_s *QCN9224v1_TARGETDEF;
-struct hostdef_s *QCN9224v1_HOSTDEF;
-#endif /*QCN9224_HEADERS_DEF */
-qdf_export_symbol(QCN9224v1_TARGETDEF);
-qdf_export_symbol(QCN9224v1_HOSTDEF);

hif/src/regtable.c

@@ -137,12 +137,6 @@ void hif_target_register_tbl_attach(struct hif_softc *scn, u32 target_type)
 
 #if defined(QCN9224_HEADERS_DEF)
 	case TARGET_TYPE_QCN9224:
-		if (scn->target_info.soc_version == 1) {
-			scn->targetdef = QCN9224v1_TARGETDEF;
-			scn->target_ce_def = QCN9224v1_CE_TARGETDEF;
-			hif_info("TARGET_TYPE_QCN9224v1");
-			break;
-		}
 		scn->targetdef = QCN9224_TARGETDEF;
 		scn->target_ce_def = QCN9224_CE_TARGETDEF;
 		hif_info("TARGET_TYPE_QCN9224");
@@ -321,10 +315,8 @@ void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type)
 #endif
 #if defined(QCN9224_HEADERS_DEF)
 	case HIF_TYPE_QCN9224:
-		if (scn->target_info.soc_version == 1) {
-			scn->hostdef = QCN9224v1_HOSTDEF;
-			break;
-		}
+		if (scn->target_info.soc_version == 1)
+			qdf_assert_always(0);
 		scn->hostdef = QCN9224_HOSTDEF;
 		break;
 #endif