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qcacmn: Enable HW cookie conversion feature

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Enable Hardware cookie conversion feature

Change-Id: I75299384ad7b795160b9cf04768326c74401b1ba
This commit is contained in:
Pavankumar Nandeshwar
2021-08-09 05:45:32 -07:00
committed by Madan Koyyalamudi
parent 60c442a689
commit 2228afc5b4
7 changed files with 89 additions and 6 deletions
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4
hal/wifi3.0/be/hal_be_api.h
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@@ -37,7 +37,9 @@ struct hal_hw_cc_config {
wbm2sw1_cc_en:1,
wbm2sw0_cc_en:1,
wbm2fw_cc_en:1,
reserved:4;
error_path_cookie_conv_en:1,
release_path_cookie_conv_en:1,
reserved:2;
};
#define HAL_RX_MSDU_EXT_DESC_INFO_GET(msdu_details_ptr) \

21
hal/wifi3.0/be/hal_be_generic_api.c
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@@ -824,6 +824,27 @@ void hal_cookie_conversion_reg_cfg_be(hal_soc_handle_t hal_soc_hdl,
cc_cfg->wbm2fw_cc_en);
HAL_REG_WRITE(soc, reg_addr, reg_val);
#ifdef HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK
reg_addr = HWIO_WBM_R0_WBM_CFG_2_ADDR(WBM_REG_REG_BASE);
reg_val = 0;
reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
COOKIE_DEBUG_SEL,
cc_cfg->cc_global_en);
reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
COOKIE_CONV_INDICATION_EN,
cc_cfg->cc_global_en);
reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
ERROR_PATH_COOKIE_CONV_EN,
cc_cfg->error_path_cookie_conv_en);
reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
RELEASE_PATH_COOKIE_CONV_EN,
cc_cfg->release_path_cookie_conv_en);
HAL_REG_WRITE(soc, reg_addr, reg_val);
#endif
#ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
/*
* To enable indication for HW cookie conversion done or not for

13
hal/wifi3.0/hal_api.h
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@@ -2950,12 +2950,15 @@ uint32_t hal_get_ring_usage(
*
* Return: None.
*/
static inline void hal_cmem_write(hal_soc_handle_t hal_soc_hdl,
uint32_t offset,
uint32_t value)
static inline void
hal_cmem_write(hal_soc_handle_t hal_soc_hdl, uint32_t offset,
uint32_t value)
{
struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
hal_write32_mb(hal, offset, value);
if (hal_soc->ops->hal_cmem_write)
hal_soc->ops->hal_cmem_write(hal_soc_hdl, offset, value);
return;
}
#endif /* _HAL_APIH_ */

4
hal/wifi3.0/hal_internal.h
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@@ -915,6 +915,10 @@ struct hal_hw_txrx_ops {
void (*hal_rx_flow_get_cmem_fse)(struct hal_soc *soc,
uint32_t fse_offset,
uint32_t *fse, qdf_size_t len);
void (*hal_cmem_write)(hal_soc_handle_t hal_soc_hdl, uint32_t offset,
uint32_t value);
void (*hal_rx_msdu_get_reo_destination_indication)(uint8_t *buf,
uint32_t *reo_destination_indication);
uint8_t (*hal_tx_get_num_tcl_banks)(void);

33
hal/wifi3.0/qcn9224/hal_9224.c
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@@ -121,16 +121,31 @@
#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
#ifdef CONFIG_WIFI_EMULATION_WIFI_3_0
#define CMEM_REG_BASE 0x0010e000
#define CMEM_WINDOW_ADDRESS_9224 \
((CMEM_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
#endif
#define CE_WINDOW_ADDRESS_9224 \
((CE_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
#define UMAC_WINDOW_ADDRESS_9224 \
((UMAC_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
#ifdef CONFIG_WIFI_EMULATION_WIFI_3_0
#define WINDOW_CONFIGURATION_VALUE_9224 \
((CE_WINDOW_ADDRESS_9224 << 6) |\
(UMAC_WINDOW_ADDRESS_9224 << 12) | \
CMEM_WINDOW_ADDRESS_9224 | \
WINDOW_ENABLE_BIT)
#else
#define WINDOW_CONFIGURATION_VALUE_9224 \
((CE_WINDOW_ADDRESS_9224 << 6) |\
(UMAC_WINDOW_ADDRESS_9224 << 12) | \
WINDOW_ENABLE_BIT)
#endif
/* For Berryllium sw2rxdma ring size increased to 20 bits */
#define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF
@@ -1230,6 +1245,23 @@ static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl,
#define HAL_NUM_TCL_BANKS_9224 48
/**
* hal_cmem_write_9224() - function for CMEM buffer writing
* @hal_soc_hdl: HAL SOC handle
* @offset: CMEM address
* @value: value to write
*
* Return: None.
*/
static void hal_cmem_write_9224(hal_soc_handle_t hal_soc_hdl,
uint32_t offset,
uint32_t value)
{
struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
pld_reg_write(hal->qdf_dev->dev, offset, value);
}
/**
* hal_tx_get_num_tcl_banks_9224() - Get number of banks in target
*
@@ -1247,6 +1279,7 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_get_window_address = hal_get_window_address_9224;
hal_soc->ops->hal_cmem_write = hal_cmem_write_9224;
/* tx */
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9224;

18
hal/wifi3.0/wcn7850/hal_7850.c
View File

@@ -1285,6 +1285,23 @@ static void hal_rx_reo_prev_pn_get_7850(void *ring_desc,
*prev_pn |= ((uint64_t)reo_desc->prev_pn_55_24 << 24);
}
/**
* hal_cmem_write_7850() - function for CMEM buffer writing
* @hal_soc_hdl: HAL SOC handle
* @offset: CMEM address
* @value: value to write
*
* Return: None.
*/
static inline void hal_cmem_write_7850(hal_soc_handle_t hal_soc_hdl,
uint32_t offset,
uint32_t value)
{
struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
hal_write32_mb(hal, offset, value);
}
static void hal_hw_txrx_ops_attach_wcn7850(struct hal_soc *hal_soc)
{
/* init and setup */
@@ -1450,6 +1467,7 @@ static void hal_hw_txrx_ops_attach_wcn7850(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_flow_setup_cmem_fse = NULL;
hal_soc->ops->hal_rx_flow_get_cmem_fse_ts = NULL;
hal_soc->ops->hal_rx_flow_get_cmem_fse = NULL;
hal_soc->ops->hal_cmem_write = hal_cmem_write_7850;
hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
hal_rx_msdu_get_reo_destination_indication_be;
hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_7850;