video: driver: reduce device_tree dependency for video

Only keep minimal entries in dtsi, which is essential for
other drivers usage. Move remaining all data into platform
resource file.

Remove device_tree dependency and maintain platform_data
to initialize resources like regulators, interconnects,
clocks, reset_clocks, subcaches and context_banks.

Read static data like freq_table, firmware_name, pas_id
also from platform_data instead of from dtsi.

Change-Id: I73a1df10b92c55e55b23e538aea62598a7250ab4
Signed-off-by: Govindaraj Rajagopal <quic_grajagop@quicinc.com>

driver/variant/common/src/msm_vidc_variant.c

@@ -9,8 +9,8 @@
 
 #include "msm_vidc_core.h"
 #include "msm_vidc_debug.h"
-#include "msm_vidc_dt.h"
 #include "msm_vidc_variant.h"
+#include "msm_vidc_platform.h"
 
 static void __fatal_error(bool fatal)
 {
@@ -35,7 +35,7 @@ int __write_register(struct msm_vidc_core *core, u32 reg, u32 value)
 	u8 *base_addr;
 	int rc = 0;
 
-	if (!core) {
+	if (!core || !core->resource) {
 		d_vpr_e("%s: invalid params\n", __func__);
 		return -EINVAL;
 	}
@@ -49,7 +49,7 @@ int __write_register(struct msm_vidc_core *core, u32 reg, u32 value)
 		return -EINVAL;
 	}
 
-	base_addr = core->register_base_addr;
+	base_addr = core->resource->register_base_addr;
 	d_vpr_l("regwrite(%pK + %#x) = %#x\n", base_addr, hwiosymaddr, value);
 	base_addr += hwiosymaddr;
 	writel_relaxed(value, base_addr);
@@ -74,7 +74,7 @@ int __write_register_masked(struct msm_vidc_core *core, u32 reg, u32 value,
 	u8 *base_addr;
 	int rc = 0;
 
-	if (!core) {
+	if (!core || !core->resource) {
 		d_vpr_e("%s: invalid params\n", __func__);
 		return -EINVAL;
 	}
@@ -89,7 +89,7 @@ int __write_register_masked(struct msm_vidc_core *core, u32 reg, u32 value,
 		return -EINVAL;
 	}
 
-	base_addr = core->register_base_addr;
+	base_addr = core->resource->register_base_addr;
 	base_addr += reg;
 
 	prev_val = readl_relaxed(base_addr);
@@ -116,7 +116,7 @@ int __read_register(struct msm_vidc_core *core, u32 reg, u32 *value)
 	int rc = 0;
 	u8 *base_addr;
 
-	if (!core || !value) {
+	if (!core || !core->resource || !value) {
 		d_vpr_e("%s: invalid params\n", __func__);
 		return -EINVAL;
 	}
@@ -126,7 +126,7 @@ int __read_register(struct msm_vidc_core *core, u32 reg, u32 *value)
 		return -EINVAL;
 	}
 
-	base_addr = core->register_base_addr;
+	base_addr = core->resource->register_base_addr;
 
 	*value = readl_relaxed(base_addr + reg);
 	/*
@@ -147,7 +147,7 @@ int __read_register_with_poll_timeout(struct msm_vidc_core *core, u32 reg,
 	u32 val = 0;
 	u8 *addr;
 
-	if (!core) {
+	if (!core || !core->resource) {
 		d_vpr_e("%s: invalid params\n", __func__);
 		return -EINVAL;
 	}
@@ -157,7 +157,7 @@ int __read_register_with_poll_timeout(struct msm_vidc_core *core, u32 reg,
 		return -EINVAL;
 	}
 
-	addr = (u8 *)core->register_base_addr + reg;
+	addr = (u8 *)core->resource->register_base_addr + reg;
 
 	rc = readl_relaxed_poll_timeout(addr, val, ((val & mask) == exp_val), sleep_us, timeout_us);
 	/*
@@ -167,7 +167,7 @@ int __read_register_with_poll_timeout(struct msm_vidc_core *core, u32 reg,
 	rmb();
 	d_vpr_l(
 		"regread(%pK + %#x) = %#x. rc %d, mask %#x, exp_val %#x, cond %u, sleep %u, timeout %u\n",
-		core->register_base_addr, reg, val, rc, mask, exp_val,
+		core->resource->register_base_addr, reg, val, rc, mask, exp_val,
 		((val & mask) == exp_val), sleep_us, timeout_us);
 
 	return rc;
@@ -175,19 +175,25 @@ int __read_register_with_poll_timeout(struct msm_vidc_core *core, u32 reg,
 
 int __set_registers(struct msm_vidc_core *core)
 {
-	struct reg_set *reg_set;
-	int i, rc = 0;
+	const struct reg_preset_table *reg_prst;
+	unsigned int prst_count;
+	int cnt, rc = 0;
 
-	if (!core || !core->dt) {
+	if (!core || !core->platform) {
 		d_vpr_e("core resources null, cannot set registers\n");
 		return -EINVAL;
 	}
 
-	reg_set = &core->dt->reg_set;
-	for (i = 0; i < reg_set->count; i++) {
-		rc = __write_register_masked(core, reg_set->reg_tbl[i].reg,
-					     reg_set->reg_tbl[i].value,
-					     reg_set->reg_tbl[i].mask);
+	reg_prst = core->platform->data.reg_prst_tbl;
+	prst_count = core->platform->data.reg_prst_tbl_size;
+
+	/* skip if there is no preset reg available */
+	if (!reg_prst || !prst_count)
+		return 0;
+
+	for (cnt = 0; cnt < prst_count; cnt++) {
+		rc = __write_register_masked(core, reg_prst->reg,
+					reg_prst->value, reg_prst->mask);
 		if (rc)
 			return rc;
 	}

driver/variant/iris3/src/msm_vidc_buffer_iris3.c

@@ -10,7 +10,6 @@
 #include "msm_vidc_buffer.h"
 #include "msm_vidc_inst.h"
 #include "msm_vidc_core.h"
-#include "msm_vidc_platform.h"
 #include "msm_vidc_driver.h"
 #include "msm_vidc_debug.h"
 #include "msm_media_info.h"

driver/variant/iris3/src/msm_vidc_iris3.c

@@ -12,7 +12,6 @@
 #include "msm_vidc_core.h"
 #include "msm_vidc_driver.h"
 #include "msm_vidc_control.h"
-#include "msm_vidc_dt.h"
 #include "msm_vidc_internal.h"
 #include "msm_vidc_buffer.h"
 #include "msm_vidc_debug.h"
@@ -487,7 +486,7 @@ static int __power_off_iris3(struct msm_vidc_core *core)
 		d_vpr_e("%s: failed to unvote buses\n", __func__);
 
 	if (!(core->intr_status & WRAPPER_INTR_STATUS_A2HWD_BMSK_IRIS3))
-		disable_irq_nosync(core->dt->irq);
+		disable_irq_nosync(core->resource->irq);
 	core->intr_status = 0;
 
 	core->power_enabled = false;
@@ -551,7 +550,7 @@ fail_regulator:
 static int __power_on_iris3(struct msm_vidc_core *core)
 {
 	const struct msm_vidc_resources_ops *res_ops = core->res_ops;
-	struct allowed_clock_rates_table *clk_tbl;
+	struct frequency_table *freq_tbl;
 	u32 freq = 0;
 	int rc = 0;
 
@@ -579,9 +578,9 @@ static int __power_on_iris3(struct msm_vidc_core *core)
 	/* video controller and hardware powered on successfully */
 	core->power_enabled = true;
 
-	clk_tbl = core->dt->allowed_clks_tbl;
+	freq_tbl = core->resource->freq_set.freq_tbl;
 	freq = core->power.clk_freq ? core->power.clk_freq :
-				      clk_tbl[0].clock_rate;
+				      freq_tbl[0].freq;
 
 	rc = res_ops->set_clks(core, freq);
 	if (rc) {
@@ -596,7 +595,7 @@ static int __power_on_iris3(struct msm_vidc_core *core)
 
 	__interrupt_init_iris3(core);
 	core->intr_status = 0;
-	enable_irq(core->dt->irq);
+	enable_irq(core->resource->irq);
 
 	return rc;
 

driver/variant/iris3/src/msm_vidc_power_iris3.c

@@ -9,7 +9,6 @@
 #include "msm_vidc_core.h"
 #include "msm_vidc_driver.h"
 #include "msm_vidc_debug.h"
-#include "msm_vidc_dt.h"
 
 u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
 {
@@ -27,9 +26,10 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
 		d_vpr_e("%s: invalid params\n", __func__);
 		return freq;
 	}
-
 	core = inst->core;
-	if (!core->dt || !core->dt->allowed_clks_tbl) {
+
+	if (!core->resource || !core->resource->freq_set.freq_tbl ||
+		!core->resource->freq_set.count) {
 		d_vpr_e("%s: invalid params\n", __func__);
 		return freq;
 	}
@@ -151,8 +151,8 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
 			u32 bitrate_2stage[2] = {130, 120};
 			u32 bitrate_1stage = 100;
 			u32 width, height;
-			u32 bitrate_entry, freq_entry, frequency_table_value;
-			struct allowed_clock_rates_table *allowed_clks_tbl;
+			u32 bitrate_entry, freq_entry, freq_tbl_value;
+			struct frequency_table *freq_tbl;
 			struct v4l2_format *out_f = &inst->fmts[OUTPUT_PORT];
 
 			width = out_f->fmt.pix_mp.width;
@@ -165,11 +165,11 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
 
 			freq_entry = bitrate_entry;
 
-			allowed_clks_tbl = core->dt->allowed_clks_tbl;
-			frequency_table_value = allowed_clks_tbl[freq_entry].clock_rate / 1000000;
+			freq_tbl = core->resource->freq_set.freq_tbl;
+			freq_tbl_value = freq_tbl[freq_entry].freq / 1000000;
 
 			input_bitrate_mbps = fps * data_size * 8 / (1024 * 1024);
-			vsp_hw_min_frequency = frequency_table_value * 1000 * input_bitrate_mbps;
+			vsp_hw_min_frequency = freq_tbl_value * 1000 * input_bitrate_mbps;
 
 			if (inst->capabilities->cap[STAGE].value == MSM_VIDC_STAGE_2) {
 				vsp_hw_min_frequency +=
@@ -233,9 +233,9 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
 		 * for non-AV1 codecs limit the frequency to NOM only
 		 * index 0 is TURBO, index 1 is NOM clock rate
 		 */
-		if (core->dt->allowed_clks_tbl_size >= 2 &&
-		    freq > core->dt->allowed_clks_tbl[1].clock_rate)
-			freq = core->dt->allowed_clks_tbl[1].clock_rate;
+		if (core->resource->freq_set.count >= 2 &&
+		    freq > core->resource->freq_set.freq_tbl[1].freq)
+			freq = core->resource->freq_set.freq_tbl[1].freq;
 	}
 
 	i_vpr_p(inst, "%s: filled len %d, required freq %llu, fps %u, mbpf %u\n",