disp: msm: sde: add support for hwfence profiling
This change adds hwfence input and output fence profiling registers and debugfs to enable them. To enable input hw fences timestamps: echo 0x1 > /d/dri/0/debug/hw_fence_status To enable output hw fences timestamps: echo 0x2 > /d/dri/0/debug/hw_fence_status To enable both, input and output hw fences timestamps: echo 0x3 > /d/dri/0/debug/hw_fence_status. Change-Id: I269a38f3843a01ec8c0816890e50bb7d847a4ed9 Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
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@@ -3801,22 +3801,23 @@ static bool _sde_crtc_wait_for_fences(struct drm_crtc *crtc)
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int num_hw_fences = 0;
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struct sde_hw_ctl *hw_ctl;
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bool input_hw_fences_enable;
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struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc);
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int ret;
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SDE_DEBUG("\n");
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if (!crtc || !crtc->state) {
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if (!crtc || !crtc->state || !sde_kms) {
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SDE_ERROR("invalid crtc/state %pK\n", crtc);
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return false;
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}
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hw_ctl = _sde_crtc_get_hw_ctl(crtc);
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SDE_ATRACE_BEGIN("plane_wait_input_fence");
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/* update ctl hw to wait for ipcc input signal before fetch */
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if (test_bit(HW_FENCE_IN_FENCES_ENABLE, sde_crtc->hwfence_features_mask) &&
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!sde_fence_update_input_hw_fence_signal(hw_ctl))
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!sde_fence_update_input_hw_fence_signal(hw_ctl, sde_kms->debugfs_hw_fence,
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sde_kms->hw_mdp))
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ipcc_input_signal_wait = true;
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/* avoid hw-fences in first frame after timing engine enable */
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@@ -4626,7 +4627,8 @@ void sde_crtc_commit_kickoff(struct drm_crtc *crtc,
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* condition between txq update and the hw signal during ctl-done for partial updates
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*/
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if (test_bit(HW_FENCE_OUT_FENCES_ENABLE, sde_crtc->hwfence_features_mask) && !is_vid)
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sde_fence_update_hw_fences_txq(sde_crtc->output_fence, false, 0);
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sde_fence_update_hw_fences_txq(sde_crtc->output_fence, false, 0,
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sde_kms->debugfs_hw_fence);
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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if (encoder->crtc != crtc)
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