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@@ -0,0 +1,196 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+/*
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+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+#include <linux/errno.h>
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+#include <linux/iopoll.h>
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+
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+#include "msm_vidc_core.h"
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+#include "msm_vidc_debug.h"
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+#include "msm_vidc_dt.h"
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+#include "msm_vidc_variant.h"
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+
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+static void __fatal_error(bool fatal)
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+{
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+ WARN_ON(fatal);
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+}
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+
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+static int __strict_check(struct msm_vidc_core *core, const char *function)
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+{
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+ bool fatal = !mutex_is_locked(&core->lock);
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+
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+ __fatal_error(fatal);
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+
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+ if (fatal)
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+ d_vpr_e("%s: strict check failed\n", function);
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+
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+ return fatal ? -EINVAL : 0;
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+}
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+
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+int __write_register(struct msm_vidc_core *core, u32 reg, u32 value)
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+{
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+ u32 hwiosymaddr = reg;
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+ u8 *base_addr;
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+ int rc = 0;
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+
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+ if (!core) {
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+ d_vpr_e("%s: invalid params\n", __func__);
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+ return -EINVAL;
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+ }
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+
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+ rc = __strict_check(core, __func__);
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+ if (rc)
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+ return rc;
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+
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+ if (!core->power_enabled) {
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+ d_vpr_e("HFI Write register failed : Power is OFF\n");
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+ return -EINVAL;
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+ }
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+
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+ base_addr = core->register_base_addr;
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+ d_vpr_l("regwrite(%pK + %#x) = %#x\n", base_addr, hwiosymaddr, value);
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+ base_addr += hwiosymaddr;
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+ writel_relaxed(value, base_addr);
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+
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+ /*
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+ * Memory barrier to make sure value is written into the register.
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+ */
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+ wmb();
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+
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+ return rc;
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+}
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+
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+/*
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+ * Argument mask is used to specify which bits to update. In case mask is 0x11,
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+ * only bits 0 & 4 will be updated with corresponding bits from value. To update
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+ * entire register with value, set mask = 0xFFFFFFFF.
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+ */
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+int __write_register_masked(struct msm_vidc_core *core, u32 reg, u32 value,
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+ u32 mask)
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+{
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+ u32 prev_val, new_val;
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+ u8 *base_addr;
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+ int rc = 0;
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+
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+ if (!core) {
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+ d_vpr_e("%s: invalid params\n", __func__);
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+ return -EINVAL;
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+ }
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+
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+ rc = __strict_check(core, __func__);
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+ if (rc)
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+ return rc;
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+
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+ if (!core->power_enabled) {
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+ d_vpr_e("%s: register write failed, power is off\n",
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+ __func__);
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+ return -EINVAL;
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+ }
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+
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+ base_addr = core->register_base_addr;
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+ base_addr += reg;
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+
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+ prev_val = readl_relaxed(base_addr);
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+ /*
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+ * Memory barrier to ensure register read is correct
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+ */
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+ rmb();
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+
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+ new_val = (prev_val & ~mask) | (value & mask);
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+ d_vpr_l(
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+ "Base addr: %pK, writing to: %#x, previous-value: %#x, value: %#x, mask: %#x, new-value: %#x...\n",
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+ base_addr, reg, prev_val, value, mask, new_val);
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+ writel_relaxed(new_val, base_addr);
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+ /*
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+ * Memory barrier to make sure value is written into the register.
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+ */
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+ wmb();
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+
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+ return rc;
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+}
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+
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+int __read_register(struct msm_vidc_core *core, u32 reg, u32 *value)
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+{
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+ int rc = 0;
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+ u8 *base_addr;
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+
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+ if (!core || !value) {
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+ d_vpr_e("%s: invalid params\n", __func__);
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+ return -EINVAL;
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+ }
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+
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+ if (!core->power_enabled) {
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+ d_vpr_e("HFI Read register failed : Power is OFF\n");
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+ return -EINVAL;
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+ }
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+
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+ base_addr = core->register_base_addr;
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+
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+ *value = readl_relaxed(base_addr + reg);
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+ /*
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+ * Memory barrier to make sure value is read correctly from the
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+ * register.
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+ */
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+ rmb();
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+ d_vpr_l("regread(%pK + %#x) = %#x\n", base_addr, reg, *value);
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+
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+ return rc;
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+}
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+
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+int __read_register_with_poll_timeout(struct msm_vidc_core *core, u32 reg,
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+ u32 mask, u32 exp_val, u32 sleep_us,
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+ u32 timeout_us)
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+{
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+ int rc = 0;
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+ u32 val = 0;
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+ u8 *addr;
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+
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+ if (!core) {
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+ d_vpr_e("%s: invalid params\n", __func__);
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+ return -EINVAL;
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+ }
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+
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+ if (!core->power_enabled) {
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+ d_vpr_e("%s failed: Power is OFF\n", __func__);
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+ return -EINVAL;
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+ }
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+
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+ addr = (u8 *)core->register_base_addr + reg;
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+
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+ rc = readl_relaxed_poll_timeout(addr, val, ((val & mask) == exp_val), sleep_us, timeout_us);
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+ /*
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+ * Memory barrier to make sure value is read correctly from the
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+ * register.
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+ */
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+ rmb();
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+ d_vpr_l(
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+ "regread(%pK + %#x) = %#x. rc %d, mask %#x, exp_val %#x, cond %u, sleep %u, timeout %u\n",
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+ core->register_base_addr, reg, val, rc, mask, exp_val,
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+ ((val & mask) == exp_val), sleep_us, timeout_us);
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+
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+ return rc;
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+}
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+
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+int __set_registers(struct msm_vidc_core *core)
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+{
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+ struct reg_set *reg_set;
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+ int i, rc = 0;
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+
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+ if (!core || !core->dt) {
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+ d_vpr_e("core resources null, cannot set registers\n");
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+ return -EINVAL;
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+ }
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+
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+ reg_set = &core->dt->reg_set;
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+ for (i = 0; i < reg_set->count; i++) {
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+ rc = __write_register_masked(core, reg_set->reg_tbl[i].reg,
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+ reg_set->reg_tbl[i].value,
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+ reg_set->reg_tbl[i].mask);
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+ if (rc)
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+ return rc;
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+ }
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+
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+ return rc;
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+}
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Stanimir Varbanov