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@@ -104,13 +104,20 @@ static int32_t cam_cci_validate_queue(struct cci_device *cci_dev,
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if ((read_val + len + 1) >
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cci_dev->cci_i2c_queue_info[master][queue].max_queue_size) {
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uint32_t reg_val = 0;
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- uint32_t report_val = CCI_I2C_REPORT_CMD | (1 << 8);
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+ uint32_t report_id =
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+ cci_dev->cci_i2c_queue_info[master][queue].report_id;
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+ uint32_t report_val = CCI_I2C_REPORT_CMD | (1 << 8) |
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+ (1 << 9) | (report_id << 4);
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CAM_DBG(CAM_CCI, "CCI_I2C_REPORT_CMD");
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cam_io_w_mb(report_val,
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base + CCI_I2C_M0_Q0_LOAD_DATA_ADDR +
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reg_offset);
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read_val++;
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+ cci_dev->cci_i2c_queue_info[master][queue].report_id++;
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+ if (cci_dev->cci_i2c_queue_info[master][queue].report_id == REPORT_IDSIZE)
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+ cci_dev->cci_i2c_queue_info[master][queue].report_id = 0;
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+
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CAM_DBG(CAM_CCI,
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"CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR %d, queue: %d",
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read_val, queue);
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@@ -305,14 +312,22 @@ static void cam_cci_load_report_cmd(struct cci_device *cci_dev,
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uint32_t reg_offset = master * 0x200 + queue * 0x100;
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uint32_t read_val = cam_io_r_mb(base +
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CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset);
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- uint32_t report_val = CCI_I2C_REPORT_CMD | (1 << 8);
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+ uint32_t report_id =
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+ cci_dev->cci_i2c_queue_info[master][queue].report_id;
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+ uint32_t report_val = CCI_I2C_REPORT_CMD | (1 << 8) |
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+ (1 << 9) | (report_id << 4);
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- CAM_DBG(CAM_CCI, "CCI_I2C_REPORT_CMD curr_w_cnt: %d", read_val);
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+ CAM_DBG(CAM_CCI, "CCI_I2C_REPORT_CMD curr_w_cnt: %d report_id %d",
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+ read_val, report_id);
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cam_io_w_mb(report_val,
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base + CCI_I2C_M0_Q0_LOAD_DATA_ADDR +
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reg_offset);
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read_val++;
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+ cci_dev->cci_i2c_queue_info[master][queue].report_id++;
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+ if (cci_dev->cci_i2c_queue_info[master][queue].report_id == REPORT_IDSIZE)
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+ cci_dev->cci_i2c_queue_info[master][queue].report_id = 0;
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+
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CAM_DBG(CAM_CCI, "CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR %d", read_val);
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cam_io_w_mb(read_val, base +
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CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR + reg_offset);
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