qcacmn: hif: Fix misspellings

Fix misspellings in hif/... Change-Id: I8eeefbf714bbb66f61886d9ceabe3f28607b045c CRs-Fixed: 3304686
2022-09-30 15:09:37 -07:00
--- a/hif/inc/hif.h
+++ b/hif/inc/hif.h
@@ -276,12 +276,12 @@ struct CE_state;
 * qca_napi_stat - stats structure for execution contexts
 * @napi_schedules - number of times the schedule function is called
 * @napi_polls - number of times the execution context runs
- * @napi_completes - number of times that the generating interrupt is reenabled
+ * @napi_completes - number of times that the generating interrupt is re-enabled
 * @napi_workdone - cumulative of all work done reported by handler
 * @cpu_corrected - incremented when execution context runs on a different core
 *			than the one that its irq is affined to.
 * @napi_budget_uses - histogram of work done per execution run
- * @time_limit_reache - count of yields due to time limit threshholds
+ * @time_limit_reache - count of yields due to time limit thresholds
 * @rxpkt_thresh_reached - count of yields due to a work limit
 * @poll_time_buckets - histogram of poll times for the napi
 *
@@ -375,7 +375,7 @@ struct qca_napi_cpu {
 * @lock: spinlock used in the event state machine
 * @state: state variable used in the napi stat machine
 * @ce_map: bit map indicating which ce's have napis running
- * @exec_map: bit map of instanciated exec contexts
+ * @exec_map: bit map of instantiated exec contexts
 * @user_cpu_affin_map: CPU affinity map from INI config.
 * @napi_cpu: cpu info for irq affinty
 * @lilcl_head:
@@ -909,7 +909,7 @@ static inline void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int ret)

 /*
 * Enable/disable CDC max performance workaround
- * For max-performace set this to 0
+ * For max-performance set this to 0
 * To allow SoC to enter sleep set this to 1
 */
 #define CONFIG_DISABLE_CDC_MAX_PERF_WAR 0
@@ -1172,7 +1172,7 @@ enum hif_ep_vote_type {
 /**
 * enum hif_ep_vote_access - hif ep vote access
 * HIF_EP_VOTE_ACCESS_ENABLE: Enable ep voting
- * HIF_EP_VOTE_INTERMEDIATE_ACCESS: allow during transistion
+ * HIF_EP_VOTE_INTERMEDIATE_ACCESS: allow during transition
 * HIF_EP_VOTE_ACCESS_DISABLE: disable ep voting
 */
 enum hif_ep_vote_access {
@@ -1214,7 +1214,7 @@ enum  hif_rtpm_client_id {
 * HIF_RTPM_GET_ASYNC: Increment usage count and when system is suspended
 *		      schedule resume process, return depends on pm state.
 * HIF_RTPM_GET_FORCE: Increment usage count and when system is suspended
- *		      shedule resume process, returns success irrespective of
+ *		      schedule resume process, returns success irrespective of
 *		      pm_state.
 * HIF_RTPM_GET_SYNC: Increment usage count and when system is suspended,
 *		     wait till process is resumed.
@@ -1414,7 +1414,7 @@ void hif_rtpm_set_monitor_wake_intr(int val);
 * hif_pre_runtime_suspend() - book keeping before beginning runtime suspend.
 * @hif_ctx: HIF context
 *
- * Makes sure that the pci link will be taken down by the suspend opperation.
+ * Makes sure that the pci link will be taken down by the suspend operation.
 * If the hif layer is configured to leave the bus on, runtime suspend will
 * not save any power.
 *
@@ -1807,7 +1807,7 @@ int32_t hif_get_int_ctx_irq_num(struct hif_opaque_softc *softc,
 				uint8_t id);

 /**
- * hif_configure_ext_group_interrupts() - Congigure ext group intrrupts
+ * hif_configure_ext_group_interrupts() - Configure ext group interrupts
 * @hif_ctx: hif opaque context
 *
 * Return: QDF_STATUS
@@ -1815,7 +1815,7 @@ int32_t hif_get_int_ctx_irq_num(struct hif_opaque_softc *softc,
 QDF_STATUS hif_configure_ext_group_interrupts(struct hif_opaque_softc *hif_ctx);

 /**
- * hif_deconfigure_ext_group_interrupts() - Deconfigure ext group intrrupts
+ * hif_deconfigure_ext_group_interrupts() - Deconfigure ext group interrupts
 * @hif_ctx: hif opaque context
 *
 * Return: None
--- a/hif/src/ce/ce_api.h
+++ b/hif/src/ce/ce_api.h
@@ -199,7 +199,7 @@ void ce_sendlist_init(struct ce_sendlist *sendlist);
 * ce_sendlist_buf_add() - Append a simple buffer (address/length) to a sendlist
 * @sendlist: Sendlist
 * @buffer: buffer
- * @nbytes: numer of bytes to append
+ * @nbytes: number of bytes to append
 * @flags: flags
 * @user_flags: user flags
 *
@@ -419,7 +419,7 @@ void ce_disable_any_copy_compl_intr_nolock(struct hif_softc *scn);
 void ce_enable_any_copy_compl_intr_nolock(struct hif_softc *scn);

 /* API to check if any of the copy engine pipes has
- * pending frames for prcoessing
+ * pending frames for processing
 */
 bool ce_get_rx_pending(struct hif_softc *scn);

@@ -501,7 +501,7 @@ void ce_ipa_get_resource(struct CE_handle *ce,
 * Micro controller needs
 *  - Copy engine source descriptor base address
 *  - Copy engine source descriptor size
- *  - PCI BAR address to access copy engine regiser
+ *  - PCI BAR address to access copy engine register
 *
 * Return: None
 */
--- a/hif/src/ce/ce_diag.c
+++ b/hif/src/ce/ce_diag.c
@@ -322,7 +322,7 @@ QDF_STATUS hif_diag_read_access(struct hif_opaque_softc *hif_ctx,
 * @hif_ctx: hif context
 * @address: soc virtual address
 * @data: data to copy into the soc address
- * @nbytes: number of bytes to coppy
+ * @nbytes: number of bytes to copy
 */
 QDF_STATUS hif_diag_write_mem(struct hif_opaque_softc *hif_ctx,
 			      uint32_t address, uint8_t *data, int nbytes)
--- a/hif/src/ce/ce_internal.h
+++ b/hif/src/ce/ce_internal.h
@@ -385,8 +385,8 @@ struct ce_srng_dest_status_desc {
 * union ce_desc - unified data type for ce descriptors
 *
 * Both src and destination descriptors follow the same format.
- * They use different data structures for different access symantics.
- * Here we provice a unifying data type.
+ * They use different data structures for different access semantics.
+ * Here we provide a unifying data type.
 */
 union ce_desc {
 	struct CE_src_desc src_desc;
@@ -420,7 +420,7 @@ union ce_srng_desc {
 *	index of the RX ring in fastpath
 * @FAST_TX_WRITE_INDEX_UPDATE: event recorded before updating the write index
 *	of the TX ring in fastpath
- * @FAST_TX_WRITE_INDEX_SOFTWARE_UPDATE: recored when dropping a write to
+ * @FAST_TX_WRITE_INDEX_SOFTWARE_UPDATE: recorded when dropping a write to
 *	the write index in fastpath
 * @FAST_TX_SOFTWARE_INDEX_UPDATE: event recorded before updating the software
 *	index of the RX ring in fastpath
@@ -432,7 +432,7 @@ union ce_srng_desc {
 * @HIF_CE_REAP_EXIT:  records when we process completion outside of a bh
 * @NAPI_SCHEDULE: records when napi is scheduled from the irq context
 * @NAPI_POLL_ENTER: records the start of the napi poll function
- * @NAPI_COMPLETE: records when interrupts are reenabled
+ * @NAPI_COMPLETE: records when interrupts are re-enabled
 * @NAPI_POLL_EXIT: records when the napi poll function returns
 * @HIF_RX_NBUF_ALLOC_FAILURE: record the packet when nbuf fails to allocate
 * @HIF_RX_NBUF_MAP_FAILURE: record the packet when dma map fails
--- a/hif/src/ce/ce_main.c
+++ b/hif/src/ce/ce_main.c
@@ -1536,7 +1536,7 @@ uint8_t hif_get_max_wmi_ep(struct hif_opaque_softc *hif_ctx)
 * @type: "src_ring" or "dest_ring" string for identifying the ring
 *
 * Warns on non-zero index values.
- * Causes a kernel panic if the ring is not empty durring initialization.
+ * Causes a kernel panic if the ring is not empty during initialization.
 */
 static void ce_ring_test_initial_indexes(int ce_id, struct CE_ring_state *ring,
 					 char *type)
@@ -2258,8 +2258,8 @@ void ce_disable_polling(void *cestate)
 * initialization. It may be that only one side or the other is
 * initialized by software/firmware.
 *
- * This should be called durring the initialization sequence before
- * interupts are enabled, so we don't have to worry about thread safety.
+ * This should be called during the initialization sequence before
+ * interrupts are enabled, so we don't have to worry about thread safety.
 */
 struct CE_handle *ce_init(struct hif_softc *scn,
 			  unsigned int CE_id, struct CE_attr *attr)
@@ -2519,7 +2519,7 @@ static int hif_get_pktlog_ce_num(struct hif_softc *scn)
 *
 * For use in data path
 *
- * Retrun: void
+ * Return: void
 */
 void hif_enable_fastpath(struct hif_opaque_softc *hif_ctx)
 {
@@ -2574,7 +2574,7 @@ qdf_export_symbol(hif_get_ce_handle);
 *
 * This is called while dismantling CE structures. No other thread
 * should be using these structures while dismantling is occurring
- * therfore no locking is needed.
+ * therefore no locking is needed.
 *
 * Return: none
 */
@@ -2899,7 +2899,7 @@ void hif_send_complete_check(struct hif_opaque_softc *hif_ctx, uint8_t pipe,
 #if defined(CE_TASKLET_SCHEDULE_ON_FULL) && defined(CE_TASKLET_DEBUG_ENABLE)
 #define CE_RING_FULL_THRESHOLD_TIME 3000000
 #define CE_RING_FULL_THRESHOLD 1024
-/* Ths function is called from htc_send path. If there is no resourse to send
+/* This function is called from htc_send path. If there is no resourse to send
 * packet via HTC, then check if interrupts are not processed from that
 * CE for last 3 seconds. If so, schedule a tasklet to reap available entries.
 * Also if Queue has reached 1024 entries within 3 seconds, then also schedule
--- a/hif/src/ce/ce_main.h
+++ b/hif/src/ce/ce_main.h
@@ -36,8 +36,8 @@
 /*
 * Number of times to check for any pending tx/rx completion on
 * a copy engine, this count should be big enough. Once we hit
- * this threashold we'll not check for any Tx/Rx comlpetion in same
- * interrupt handling. Note that this threashold is only used for
+ * this threshold we'll not check for any Tx/Rx completion in same
+ * interrupt handling. Note that this threshold is only used for
 * Rx interrupt processing, this can be used tor Tx as well if we
 * suspect any infinite loop in checking for pending Tx completion.
 */
@@ -119,7 +119,7 @@ struct HIF_CE_pipe_info {
 	/* Handle of underlying Copy Engine */
 	struct CE_handle *ce_hdl;

-	/* Our pipe number; facilitiates use of pipe_info ptrs. */
+	/* Our pipe number; facilitates use of pipe_info ptrs. */
 	uint8_t pipe_num;

 	/* Convenience back pointer to HIF_CE_state. */
--- a/hif/src/ce/ce_reg.h
+++ b/hif/src/ce/ce_reg.h
@@ -554,7 +554,7 @@ u32 shadow_dst_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr);
 	A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS, (n))
 #endif

-/* The write index read is only needed durring initialization because
+/* The write index read is only needed during initialization because
 * we keep track of the index that was last written.  Thus the register
 * is the only hardware supported location to read the initial value from.
 */
--- a/hif/src/ce/ce_service.c
+++ b/hif/src/ce/ce_service.c
@@ -346,8 +346,8 @@ bool hif_ce_service_should_yield(struct hif_softc *scn,
 	bool yield =  hif_max_num_receives_reached(scn, ce_state->receive_count);

 	/* Setting receive_count to MAX_NUM_OF_RECEIVES when this count goes
-	 * beyond MAX_NUM_OF_RECEIVES for NAPI backet calulation issue. This
-	 * can happen in fast path handling as processing is happenning in
+	 * beyond MAX_NUM_OF_RECEIVES for NAPI backet calculation issue. This
+	 * can happen in fast path handling as processing is happening in
 	 * batches.
 	 */
 	if (yield)
@@ -376,8 +376,8 @@ bool hif_ce_service_should_yield(struct hif_softc *scn,
 					(scn, ce_state->receive_count);

 	/* Setting receive_count to MAX_NUM_OF_RECEIVES when this count goes
-	 * beyond MAX_NUM_OF_RECEIVES for NAPI backet calulation issue. This
-	 * can happen in fast path handling as processing is happenning in
+	 * beyond MAX_NUM_OF_RECEIVES for NAPI backet calculation issue. This
+	 * can happen in fast path handling as processing is happening in
 	 * batches.
 	 */
 	if (rxpkt_thresh_reached)
@@ -905,7 +905,7 @@ ce_completed_send_next(struct CE_handle *copyeng,
 * does receive and reaping of completed descriptor ,
 * This function only handles reaping of Tx complete descriptor.
 * The Function is called from threshold reap  poll routine
- * hif_send_complete_check so should not countain receive functionality
+ * hif_send_complete_check so should not contain receive functionality
 * within it .
 */

@@ -1283,7 +1283,7 @@ qdf_export_symbol(ce_per_engine_service);
 /*
 * Handler for per-engine interrupts on ALL active CEs.
 * This is used in cases where the system is sharing a
- * single interrput for all CEs
+ * single interrupt for all CEs
 */

 void ce_per_engine_service_any(int irq, struct hif_softc *scn)
@@ -1377,7 +1377,7 @@ void ce_enable_any_copy_compl_intr_nolock(struct hif_softc *scn)
 * ce_send_cb_register(): register completion handler
 * @copyeng: CE_state representing the ce we are adding the behavior to
 * @fn_ptr: callback that the ce should use when processing tx completions
- * @disable_interrupts: if the interupts should be enabled or not.
+ * @disable_interrupts: if the interrupts should be enabled or not.
 *
 * Caller should guarantee that no transactions are in progress before
 * switching the callback function.
@@ -1417,7 +1417,7 @@ qdf_export_symbol(ce_send_cb_register);
 * ce_recv_cb_register(): register completion handler
 * @copyeng: CE_state representing the ce we are adding the behavior to
 * @fn_ptr: callback that the ce should use when processing rx completions
- * @disable_interrupts: if the interupts should be enabled or not.
+ * @disable_interrupts: if the interrupts should be enabled or not.
 *
 * Registers the send context before the fn pointer so that if the cb is valid
 * the context should be valid.
@@ -1539,7 +1539,7 @@ static qdf_dma_addr_t ce_ipa_get_wr_index_addr(struct CE_state *CE_state)
 * Micro controller needs
 *  - Copy engine source descriptor base address
 *  - Copy engine source descriptor size
- *  - PCI BAR address to access copy engine regiser
+ *  - PCI BAR address to access copy engine register
 *
 * Return: None
 */
--- a/hif/src/ce/ce_service_legacy.c
+++ b/hif/src/ce/ce_service_legacy.c
@@ -606,7 +606,7 @@ ce_send_nolock_legacy(struct CE_handle *copyeng,
 		}

 		/* src_ring->write index hasn't been updated event though
-		 * the register has allready been written to.
+		 * the register has already been written to.
 		 */
 		hif_record_ce_desc_event(scn, CE_state->id, event_type,
 			(union ce_desc *)shadow_src_desc, per_transfer_context,
--- a/hif/src/ce/ce_service_srng.c
+++ b/hif/src/ce/ce_service_srng.c
@@ -225,7 +225,7 @@ ce_send_nolock_srng(struct CE_handle *copyeng,
 		hal_srng_access_end(scn->hal_soc, src_ring->srng_ctx);

 		/* src_ring->write index hasn't been updated event though
-		 * the register has allready been written to.
+		 * the register has already been written to.
 		 */
 		hif_record_ce_srng_desc_event(scn, CE_state->id, event_type,
 					      (union ce_srng_desc *)src_desc,
@@ -835,7 +835,7 @@ static inline bool ce_is_status_ring_timer_thresh_war_needed(void)
 * @ring_params: pointer to initialized parameters
 *
 * For Napier & Hawkeye v1, the status ring timer interrupts do not work
- * As a work arround host configures the destination rings to be a proxy for
+ * As a workaround host configures the destination rings to be a proxy for
 * work needing to be done.
 *
 * The interrupts are setup such that if the destination ring is less than fully
@@ -844,7 +844,7 @@ static inline bool ce_is_status_ring_timer_thresh_war_needed(void)
 *
 * There is a timing bug in srng based copy engines such that a fully posted
 * srng based copy engine has 2 empty entries instead of just one.  The copy
- * engine data sturctures work with 1 empty entry, but the software frequently
+ * engine data structures work with 1 empty entry, but the software frequently
 * fails to post the last entry due to the race condition.
 */
 static void ce_srng_initialize_dest_timer_interrupt_war(
@@ -1017,7 +1017,7 @@ static void ce_prepare_shadow_register_v2_cfg_srng(struct hif_softc *scn,
 			      num_shadow_registers_configured);

 	if (*num_shadow_registers_configured != 0) {
-		hif_err("hal shadow register configuration allready constructed");
+		hif_err("hal shadow register configuration already constructed");

 		/* return with original configuration*/
 		return;
@@ -1045,7 +1045,7 @@ static void ce_prepare_shadow_register_v3_cfg_srng(struct hif_softc *scn,
 				 num_shadow_registers_configured);

 	if (*num_shadow_registers_configured != 0) {
-		hif_err("hal shadow register configuration allready constructed");
+		hif_err("hal shadow register configuration already constructed");

 		/* return with original configuration*/
 		return;
--- a/hif/src/ce/ce_tasklet.c
+++ b/hif/src/ce/ce_tasklet.c
@@ -566,7 +566,7 @@ static void ce_tasklet_entry_dump(struct HIF_CE_state *hif_ce_state)
 * hif_drain_tasklets(): wait until no tasklet is pending
 * @scn: hif context
 *
- * Let running tasklets clear pending trafic.
+ * Let running tasklets clear pending traffic.
 *
 * Return: 0 if no bottom half is in progress when it returns.
 *   -EFAULT if it times out.
@@ -959,7 +959,7 @@ const char *ce_name[CE_COUNT_MAX] = {
 /**
 * ce_unregister_irq() - ce_unregister_irq
 * @hif_ce_state: hif_ce_state copy engine device handle
- * @mask: which coppy engines to unregister for.
+ * @mask: which copy engines to unregister for.
 *
 * Unregisters copy engine irqs matching mask.  If a 1 is set at bit x,
 * unregister for copy engine x.
@@ -1007,7 +1007,7 @@ QDF_STATUS ce_unregister_irq(struct HIF_CE_state *hif_ce_state, uint32_t mask)
 /**
 * ce_register_irq() - ce_register_irq
 * @hif_ce_state: hif_ce_state
- * @mask: which coppy engines to unregister for.
+ * @mask: which copy engines to unregister for.
 *
 * Registers copy engine irqs matching mask.  If a 1 is set at bit x,
 * Register for copy engine x.
--- a/hif/src/dispatcher/ipci_api.h
+++ b/hif/src/dispatcher/ipci_api.h
@@ -62,7 +62,7 @@ int hif_ipci_bus_suspend(struct hif_softc *scn);
 * @scn: hif context
 *
 * Ensure that if we received the wakeup message before the irq
- * was disabled that the message is pocessed before suspending.
+ * was disabled that the message is processed before suspending.
 *
 * Return: -EBUSY if we fail to flush the tasklets.
 */
@@ -81,7 +81,7 @@ int hif_ipci_bus_resume(struct hif_softc *scn);
 * @scn: hif context
 *
 * Ensure that if we received the wakeup message before the irq
- * was disabled that the message is pocessed before suspending.
+ * was disabled that the message is processed before suspending.
 *
 * Return: -EBUSY if we fail to flush the tasklets.
 */
--- a/hif/src/dispatcher/multibus.c
+++ b/hif/src/dispatcher/multibus.c
@@ -188,7 +188,7 @@ void hif_bus_close(struct hif_softc *hif_sc)
 * @hif_ctx: hif context
 * @flag: true = keep bus alive false = let bus go to sleep
 *
- * Keeps the bus awake durring suspend.
+ * Keeps the bus awake during suspend.
 */
 void hif_bus_prevent_linkdown(struct hif_softc *hif_sc, bool flag)
 {
--- a/hif/src/hif_exec.c
+++ b/hif/src/hif_exec.c
@@ -927,7 +927,7 @@ hif_check_and_trigger_sys_resume(struct hif_softc *scn, int irq)
 * @irq: irq number of the interrupt
 * @context: the associated hif_exec_group context
 *
- * This callback function takes care of dissabling the associated interrupts
+ * This callback function takes care of disabling the associated interrupts
 * and scheduling the expected bottom half for the exec_context.
 * This callback function also helps keep track of the count running contexts.
 */
--- a/hif/src/hif_exec.h
+++ b/hif/src/hif_exec.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -58,14 +58,14 @@ struct hif_execution_ops {
 * @context_name: a pointer to a const string for debugging.
 *		this should help whenever there could be ambiguity
 *		in what type of context the void* context points to
- * @irq: irq handle coresponding to hw block
- * @os_irq: irq handle for irq_afinity
+ * @irq: irq handle corresponding to hw block
+ * @os_irq: irq handle for irq_affinity
 * @cpu: the cpu this context should be affined to
 * @work_complete: Function call called when leaving the execution context to
 *	determine if this context should reschedule or wait for an interrupt.
 *	This function may be used as a hook for post processing.
 *
- * @sched_latency_stats: schdule latency stats for different latency buckets
+ * @sched_latency_stats: schedule latency stats for different latency buckets
 * @tstamp: timestamp when napi poll happens
 * @irq_disable: called before scheduling the context.
 * @irq_enable: called when the context leaves polling mode
--- a/hif/src/hif_irq_affinity.c
+++ b/hif/src/hif_irq_affinity.c
@@ -18,9 +18,9 @@
 */

 /**
- * DOC: hif_irq_afinity.c
+ * DOC: hif_irq_affinity.c
 *
- * This irq afinity implementation is os dependent, so this can be treated as
+ * This irq affinity implementation is os dependent, so this can be treated as
 * an abstraction layer...  Should this be moved into a /linux folder?
 */

@@ -286,7 +286,7 @@ static int hncm_exec_migrate_to(struct qca_napi_data *napid, uint8_t ctx_id,
 * @napid: pointer to NAPI block
 * @act  : RELOCATE | COLLAPSE | DISPERSE
 *
- * Finds the designated destionation for the next IRQ.
+ * Finds the designated destination for the next IRQ.
 * RELOCATE: translated to either COLLAPSE or DISPERSE based
 *           on napid->napi_mode (throughput state)
 * COLLAPSE: All have the same destination: the first online CPU in lilcl
--- a/hif/src/hif_main.c
+++ b/hif/src/hif_main.c
@@ -143,7 +143,7 @@ void hif_vote_link_down(struct hif_opaque_softc *hif_ctx)
 * hif_vote_link_up(): vote to prevent bus from suspending
 *
 * Makes hif guarantee that fw can message the host normally
- * durring suspend.
+ * during suspend.
 *
 * SYNCHRONIZE WITH hif_vote_link_up by only calling in MC thread
 * and initialization deinitialization sequencences.
@@ -171,7 +171,7 @@ void hif_vote_link_up(struct hif_opaque_softc *hif_ctx)
 * we don't need extra locking to ensure votes dont change while
 * we are in the process of suspending or resuming.
 *
- * Return: false if hif will guarantee link up durring suspend.
+ * Return: false if hif will guarantee link up during suspend.
 */
 bool hif_can_suspend_link(struct hif_opaque_softc *hif_ctx)
 {
@@ -857,12 +857,12 @@ static void hif_latency_detect_timeout_handler(void *arg)
 				    BIT(HIF_DETECT_TASKLET) |
 				    BIT(HIF_DETECT_CREDIT));

-	/* it need to make sure timer start on a differnt cpu,
+	/* it need to make sure timer start on a different cpu,
 	 * so it can detect the tasklet schedule stall, but there
 	 * is still chance that, after timer has been started, then
 	 * irq/tasklet happens on the same cpu, then tasklet will
 	 * execute before softirq timer, if this tasklet stall, the
-	 * timer can't detect it, we can accept this as a limition,
+	 * timer can't detect it, we can accept this as a limitation,
 	 * if tasklet stall, anyway other place will detect it, just
 	 * a little later.
 	 */
@@ -2085,7 +2085,7 @@ void hif_mem_free_consistent_unaligned(struct hif_softc *scn,
 * @osc: HIF Context
 * @msdu : list of msdus to be sent
 * @transfer_id : transfer id
- * @len : donwloaded length
+ * @len : downloaded length
 *
 * Return: list of msds not sent
 */
--- a/hif/src/hif_napi.c
+++ b/hif/src/hif_napi.c
@@ -1243,7 +1243,7 @@ static void hnc_cpu_online_cb(void *context, uint32_t cpu)
 * @context: the associated HIF context
 * @cpu: the CPU Id of the CPU the event happened on
 *
- * On transtion to offline, we act on PREP events, because we may need to move
+ * On transition to offline, we act on PREP events, because we may need to move
 * the irqs/NAPIs to another CPU before it is actually off-lined.
 *
 * Return: None
@@ -1488,7 +1488,7 @@ static int hncm_migrate_to(struct qca_napi_data *napid,
 * @napid: pointer to NAPI block
 * @act  : RELOCATE | COLLAPSE | DISPERSE
 *
- * Finds the designated destionation for the next IRQ.
+ * Finds the designated destination for the next IRQ.
 * RELOCATE: translated to either COLLAPSE or DISPERSE based
 *           on napid->napi_mode (throughput state)
 * COLLAPSE: All have the same destination: the first online CPU in lilcl
@@ -1542,7 +1542,7 @@ retry_disperse:
 			}
 			i = napid->napi_cpu[i].cluster_nxt;
 		}
-		/* Check if matches with user sepecified CPU mask */
+		/* Check if matches with user specified CPU mask */
 		smallidx = ((1 << smallidx) & napid->user_cpu_affin_mask) ?
 								smallidx : -1;

--- a/hif/src/hif_runtime_pm.c
+++ b/hif/src/hif_runtime_pm.c
@@ -226,7 +226,7 @@ static void hif_rtpm_debugfs_remove(void)
 /**
 * hif_rtpm_init() - Initialize Runtime PM
 * @dev: device structure
- * @delay: delay to be confgured for auto suspend
+ * @delay: delay to be configured for auto suspend
 *
 * This function will init all the Runtime PM config.
 *
--- a/hif/src/pcie/hif_io32_pci.h
+++ b/hif/src/pcie/hif_io32_pci.h
@@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -46,7 +47,7 @@
 * PCI-E L1 ASPPM sub-states
 * To enable clock gating in L1 state, set this to 1.
 * (less power, slightly more wakeup latency)
- * To disable clock gating in L1 state, set this to 0. (slighly more power)
+ * To disable clock gating in L1 state, set this to 0. (slightly more power)
 */
 #define CONFIG_PCIE_ENABLE_L1_CLOCK_GATE 1

--- a/hif/src/pcie/if_pci.c
+++ b/hif/src/pcie/if_pci.c
@@ -314,7 +314,7 @@ irqreturn_t hif_pci_legacy_ce_interrupt_handler(int irq, void *arg)
 		}

 		/* Clear Legacy PCI line interrupts
-		 * IMPORTANT: INTR_CLR regiser has to be set
+		 * IMPORTANT: INTR_CLR register has to be set
 		 * after INTR_ENABLE is set to 0,
 		 * otherwise interrupt can not be really cleared
 		 */
@@ -442,7 +442,7 @@ int hif_get_irq_num(struct hif_opaque_softc *scn, int *irq, uint32_t size)


 /**
- * hif_pci_cancel_deferred_target_sleep() - cancels the defered target sleep
+ * hif_pci_cancel_deferred_target_sleep() - cancels the deferred target sleep
 * @scn: hif_softc
 *
 * Return: void
@@ -582,7 +582,7 @@ static void hif_pci_device_reset(struct hif_pci_softc *sc)
 /* CPU warm reset function
 * Steps:
 * 1. Disable all pending interrupts - so no pending interrupts on WARM reset
- * 2. Clear the FW_INDICATOR_ADDRESS -so Traget CPU initializes FW
+ * 2. Clear the FW_INDICATOR_ADDRESS -so Target CPU initializes FW
 *    correctly on WARM reset
 * 3. Clear TARGET CPU LF timer interrupt
 * 4. Reset all CEs to clear any pending CE tarnsactions
@@ -755,14 +755,14 @@ int hif_check_soc_status(struct hif_opaque_softc *hif_ctx)
 			   RTC_STATE_ADDRESS);
 	hif_debug("RTC_STATE_ADDRESS is %08x", val);

-	/* Try to wake up taget if it sleeps */
+	/* Try to wake up target if it sleeps */
 	hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS +
 		PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_V_MASK);
 	hif_debug("PCIE_SOC_WAKE_ADDRESS is %08x",
 		hif_read32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS +
 		PCIE_SOC_WAKE_ADDRESS));

-	/* Check if taget can be woken up */
+	/* Check if target can be woken up */
 	while (!hif_targ_is_awake(scn, sc->mem)) {
 		if (timeout_count >= PCIE_WAKE_TIMEOUT) {
 			hif_err("wake up timeout, %08x, %08x",
@@ -795,7 +795,7 @@ int hif_check_soc_status(struct hif_opaque_softc *hif_ctx)
 * __hif_pci_dump_registers(): dump other PCI debug registers
 * @scn: struct hif_softc
 *
- * This function dumps pci debug registers.  The parrent function
+ * This function dumps pci debug registers.  The parent function
 * dumps the copy engine registers before calling this function.
 *
 * Return: void
@@ -1189,7 +1189,7 @@ static void hif_wake_target_cpu(struct hif_softc *scn)
 * @scn: hif_softc
 *
 * Clear the force wake register.  This is done by
- * hif_sleep_entry and cancel defered timer sleep.
+ * hif_sleep_entry and cancel deferred timer sleep.
 */
 static void soc_wake_reset(struct hif_softc *scn)
 {
@@ -1836,7 +1836,7 @@ static int hif_enable_pci_nopld(struct hif_pci_softc *sc,
 		hif_err(
 		   "dev id mismatch, config id = 0x%x, probing id = 0x%x",
 		   device_id, id->device);
-		/* pci link is down, so returing with error code */
+		/* pci link is down, so returning with error code */
 		return -EIO;
 	}

@@ -2498,7 +2498,7 @@ int hif_pci_bus_resume(struct hif_softc *scn)
 * @scn: hif context
 *
 * Ensure that if we received the wakeup message before the irq
- * was disabled that the message is pocessed before suspending.
+ * was disabled that the message is processed before suspending.
 *
 * Return: -EBUSY if we fail to flush the tasklets.
 */
@@ -2515,7 +2515,7 @@ int hif_pci_bus_suspend_noirq(struct hif_softc *scn)
 * @scn: hif context
 *
 * Ensure that if we received the wakeup message before the irq
- * was disabled that the message is pocessed before suspending.
+ * was disabled that the message is processed before suspending.
 *
 * Return: -EBUSY if we fail to flush the tasklets.
 */
@@ -3596,7 +3596,7 @@ static void hif_trigger_timer_irq(struct hif_softc *scn)
 * hif_target_sync() : ensure the target is ready
 * @scn: hif control structure
 *
- * Informs fw that we plan to use legacy interupts so that
+ * Informs fw that we plan to use legacy interrupts so that
 * it can begin booting. Ensures that the fw finishes booting
 * before continuing. Should be called before trying to write
 * to the targets other registers for the first time.
--- a/hif/src/sdio/hif_sdio.c
+++ b/hif/src/sdio/hif_sdio.c
@@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -127,7 +128,7 @@ QDF_STATUS hif_send_head(struct hif_opaque_softc *hif_ctx, uint8_t pipe,
 /**
 * hif_map_service_to_pipe() - maps ul/dl pipe to service id.
 * @hif_ctx: HIF hdl
- * @ServiceId: sevice index
+ * @ServiceId: service index
 * @ul_pipe: uplink pipe id
 * @dl_pipe: down-linklink pipe id
 * @ul_is_polled: if ul is polling based
--- a/hif/src/sdio/if_sdio.c
+++ b/hif/src/sdio/if_sdio.c
@@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -231,7 +232,7 @@ void hif_sdio_claim_device(struct hif_softc *hif_sc)
 }

 /**
- * hif_sdio_mask_interrupt_call() - disbale hif device irq
+ * hif_sdio_mask_interrupt_call() - disable hif device irq
 * @scn: pointr to softc structure
 *
 * Return: None
--- a/hif/src/sdio/native_sdio/src/dev_quirks.c
+++ b/hif/src/sdio/native_sdio/src/dev_quirks.c
@@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -329,7 +330,7 @@ int hif_sdio_quirk_mod_strength(struct hif_softc *ol_sc, struct sdio_func *func)
 	struct hif_sdio_dev *device = get_hif_device(ol_sc, func);
 	uint16_t  manfid = device->id->device & MANUFACTURER_ID_AR6K_BASE_MASK;

-	if (!modstrength) /* TODO: Dont set this : scn is not popolated yet */
+	if (!modstrength) /* TODO: Dont set this : scn is not populated yet */
 		return 0;

 	if (!scn) {
--- a/hif/src/sdio/native_sdio/src/hif.c
+++ b/hif/src/sdio/native_sdio/src/hif.c
@@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -156,7 +157,7 @@ ATH_DEBUG_INSTANTIATE_MODULE_VAR(hif,
 #endif

 /**
- * add_to_async_list() - add bus reqest to async task list
+ * add_to_async_list() - add bus request to async task list
 * @device: pointer to hif device
 * @busrequest: pointer to type of bus request
 *
@@ -876,7 +877,7 @@ int hif_device_resume(struct hif_softc *ol_sc, struct device *dev)

 /**
 * hif_sdio_remove() - remove sdio device
- * @conext: sdio device context
+ * @context: sdio device context
 * @hif_handle: pointer to sdio function
 *
 * Return: 0 for success and non-zero for failure
--- a/hif/src/sdio/transfer/adma.c
+++ b/hif/src/sdio/transfer/adma.c
@@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -99,7 +100,7 @@ QDF_STATUS hif_dev_dsr_handler(void *context)
 /**
 * hif_dev_map_service_to_pipe() - maps ul/dl pipe to service id.
 * @pDev: SDIO HIF object
- * @ServiceId: sevice index
+ * @ServiceId: service index
 * @ULPipe: uplink pipe id
 * @DLPipe: down-linklink pipe id
 *
@@ -706,7 +707,7 @@ void ul_xfer_cb(struct sdio_al_channel_handle *ch_handle,
 */
 /* Use the asynchronous method of transfer. This will help in
 * completing READ in the transfer done callback later which
- * runs in sdio al thread context. If we do the syncronous
+ * runs in sdio al thread context. If we do the synchronous
 * transfer here, the thread context won't be available and
 * perhaps a new thread may be required here.
 */
--- a/hif/src/sdio/transfer/mailbox.c
+++ b/hif/src/sdio/transfer/mailbox.c
@@ -276,7 +276,7 @@ void hif_dev_get_block_size(void *config)
 /**
 * hif_dev_map_service_to_pipe() - maps ul/dl pipe to service id.
 * @pDev: SDIO HIF object
- * @ServiceId: sevice index
+ * @ServiceId: service index
 * @ULPipe: uplink pipe id
 * @DLPipe: down-linklink pipe id
 *
@@ -618,7 +618,7 @@ void hif_fixup_write_param(struct hif_sdio_dev *pdev, uint32_t req,
 }

 /**
- * hif_dev_recv_packet() - Receieve HTC packet/packet information from device
+ * hif_dev_recv_packet() - Receive HTC packet/packet information from device
 * @pdev : HIF device object
 * @packet : The HTC packet pointer
 * @recv_length : The length of information to be received
@@ -1362,7 +1362,7 @@ QDF_STATUS hif_dev_process_pending_irqs(struct hif_sdio_device *pdev,
 	} while (false);

 	/* an optimization to bypass reading the IRQ status registers
-	 * unecessarily which can re-wake the target, if upper layers
+	 * unnecessarily which can re-wake the target, if upper layers
 	 * determine that we are in a low-throughput mode, we can
 	 * rely on taking another interrupt rather than re-checking
 	 * the status registers which can re-wake the target.
--- a/hif/src/snoc/if_ahb.c
+++ b/hif/src/snoc/if_ahb.c
@@ -440,7 +440,7 @@ void hif_ahb_disable_bus(struct hif_softc *scn)
 * @type: bus type
 *
 * This function enables the radio bus by enabling necessary
- * clocks and waits for the target to get ready to proceed futher
+ * clocks and waits for the target to get ready to proceed further
 *
 * Return: QDF_STATUS
 */
--- a/hif/src/snoc/if_snoc.c
+++ b/hif/src/snoc/if_snoc.c
@@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2015-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -19,7 +20,7 @@
 /**
 * DOC: if_snoc.c
 *
- * c file for snoc specif implementations.
+ * c file for snoc specific implementations.
 */

 #include "hif.h"
@@ -298,7 +299,7 @@ QDF_STATUS hif_snoc_enable_bus(struct hif_softc *ol_sc,
 	hif_register_tbl_attach(ol_sc, hif_type);
 	hif_target_register_tbl_attach(ol_sc, target_type);

-	/* the bus should remain on durring suspend for snoc */
+	/* the bus should remain on during suspend for snoc */
 	hif_vote_link_up(GET_HIF_OPAQUE_HDL(ol_sc));

 	hif_debug("X - hif_type = 0x%x, target_type = 0x%x",
@@ -420,7 +421,7 @@ int hif_snoc_bus_suspend(struct hif_softc *scn)
 * @scn: hif context
 *
 * Clear wakeup interrupt configuration.
- * Reenable ce interrupts
+ * Re-enable ce interrupts
 *
 * Return: 0 on success
 */
@@ -437,7 +438,7 @@ int hif_snoc_bus_resume(struct hif_softc *scn)
 * @scn: hif context
 *
 * Ensure that if we received the wakeup message before the irq
- * was disabled that the message is pocessed before suspending.
+ * was disabled that the message is processed before suspending.
 *
 * Return: -EBUSY if we fail to flush the tasklets.
 */
--- a/hif/src/usb/hif_usb.c
+++ b/hif/src/usb/hif_usb.c
@@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -484,7 +485,7 @@ void hif_get_default_pipe(struct hif_opaque_softc *scn, uint8_t *ul_pipe,
 /**
 * hif_map_service_to_pipe() - maps ul/dl pipe to service id.
 * @scn: HIF context
- * @svc_id: sevice index
+ * @svc_id: service index
 * @ul_pipe: pointer to uplink pipe id
 * @dl_pipe: pointer to down-linklink pipe id
 * @ul_is_polled: if ul is polling based
@@ -539,7 +540,7 @@ int hif_map_service_to_pipe(struct hif_opaque_softc *scn, uint16_t svc_id,
 /**
 * hif_map_service_to_pipe() - maps ul/dl pipe to service id.
 * @scn: HIF context
- * @svc_id: sevice index
+ * @svc_id: service index
 * @ul_pipe: pointer to uplink pipe id
 * @dl_pipe: pointer to down-linklink pipe id
 * @ul_is_polled: if ul is polling based
@@ -904,7 +905,7 @@ void hif_send_complete_check(struct hif_opaque_softc *scn,
 	/* NO-OP*/
 }

-/* diagnostic command defnitions */
+/* diagnostic command definitions */
 #define USB_CTRL_DIAG_CC_READ       0
 #define USB_CTRL_DIAG_CC_WRITE      1
 #define USB_CTRL_DIAG_CC_WARM_RESET 2
--- a/hif/src/usb/usbdrv.c
+++ b/hif/src/usb/usbdrv.c
@@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -228,7 +229,7 @@ static void usb_hif_free_pipe_resources(struct HIF_USB_PIPE *pipe)

 #ifdef QCN7605_SUPPORT
 /**
- * usb_hif_get_logical_pipe_num() - get pipe number for a particular enpoint
+ * usb_hif_get_logical_pipe_num() - get pipe number for a particular endpoint
 * @device: pointer to HIF_DEVICE_USB structure
 * @ep_address: endpoint address
 * @urb_count: number of urb resources to be allocated to the pipe
@@ -268,7 +269,7 @@ static uint8_t usb_hif_get_logical_pipe_num(struct HIF_DEVICE_USB *device,
 }
 #else
 /**
- * usb_hif_get_logical_pipe_num() - get pipe number for a particular enpoint
+ * usb_hif_get_logical_pipe_num() - get pipe number for a particular endpoint
 * @device: pointer to HIF_DEVICE_USB structure
 * @ep_address: endpoint address
 * @urb_count: number of urb resources to be allocated to the pipe
@@ -341,7 +342,7 @@ QDF_STATUS usb_hif_setup_pipe_resources(struct HIF_DEVICE_USB *device)
 	struct HIF_USB_PIPE *pipe;
 	uint8_t pipe_num;

-	/* walk decriptors and setup pipes */
+	/* walk descriptors and setup pipes */
 	for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) {
 		endpoint = &iface_desc->endpoint[i].desc;

@@ -1168,7 +1169,7 @@ QDF_STATUS usb_hif_submit_ctrl_out(struct HIF_DEVICE_USB *device,
 }

 /**
- * usb_hif_submit_ctrl_in() - recv a resonse to the ctrl message sent out
+ * usb_hif_submit_ctrl_in() - recv a response to the ctrl message sent out
 * @device: HIF device for which urb needs to be received
 * @req: request value for the ctrl message
 * @value: USB message value