msm: camera: icp: Improve ICP debug infrastructure
On FW timeouts, dump ICP status registers and HFI queue indices. CRs-Fixed: 3110947 Change-Id: I74561ce943c027e51b6f8b61e7ebb68d2a89982d Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
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Camera Software Integration

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@@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _HFI_INTF_H_
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@@ -182,8 +183,10 @@ int cam_hfi_resume(struct hfi_mem_info *hfi_mem);
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/**
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* cam_hfi_queue_dump() - utility function to dump hfi queues
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* @dump_queue_data: if set dumps queue contents
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*
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*/
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void cam_hfi_queue_dump(void);
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void cam_hfi_queue_dump(bool dump_queue_data);
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/**
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* cam_hfi_mini_dump() - utility function for mini dump
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@@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/io.h>
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@@ -121,7 +122,7 @@ void cam_hfi_mini_dump(struct hfi_mini_dump_info *dst)
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dst->cmd_q_state = g_hfi->cmd_q_state;
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}
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void cam_hfi_queue_dump(void)
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void cam_hfi_queue_dump(bool dump_queue_data)
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{
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struct hfi_mem_info *hfi_mem = &g_hfi->map;
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struct hfi_qtbl *qtbl;
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@@ -135,7 +136,7 @@ void cam_hfi_queue_dump(void)
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}
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qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva;
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CAM_DBG(CAM_HFI,
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CAM_INFO(CAM_HFI,
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"qtbl header: version=0x%08x tbl_size=%u numq=%u qhdr_size=%u",
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qtbl->q_tbl_hdr.qtbl_version,
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qtbl->q_tbl_hdr.qtbl_size,
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@@ -143,7 +144,7 @@ void cam_hfi_queue_dump(void)
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qtbl->q_tbl_hdr.qtbl_qhdr_size);
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q_hdr = &qtbl->q_hdr[Q_CMD];
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CAM_DBG(CAM_HFI,
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CAM_INFO(CAM_HFI,
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"cmd_q: addr=0x%08x size=%u read_idx=%u write_idx=%u",
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hfi_mem->cmd_q.iova,
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q_hdr->qhdr_q_size,
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@@ -153,10 +154,11 @@ void cam_hfi_queue_dump(void)
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dwords = (uint32_t *)hfi_mem->cmd_q.kva;
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num_dwords = ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
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if (dump_queue_data)
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hfi_queue_dump(dwords, num_dwords);
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q_hdr = &qtbl->q_hdr[Q_MSG];
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CAM_DBG(CAM_HFI,
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CAM_INFO(CAM_HFI,
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"msg_q: addr=0x%08x size=%u read_idx=%u write_idx=%u",
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hfi_mem->msg_q.iova,
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q_hdr->qhdr_q_size,
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@@ -166,6 +168,7 @@ void cam_hfi_queue_dump(void)
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dwords = (uint32_t *)hfi_mem->msg_q.kva;
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num_dwords = ICP_MSG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
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if (dump_queue_data)
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hfi_queue_dump(dwords, num_dwords);
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}
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@@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/slab.h>
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@@ -746,6 +747,10 @@ int cam_a5_process_cmd(void *device_priv, uint32_t cmd_type,
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rc = cam_a5_fw_mini_dump(dump_args, core_info);
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break;
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}
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case CAM_ICP_CMD_HW_REG_DUMP: {
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/* reg dump not supported */
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break;
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}
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default:
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break;
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}
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@@ -126,6 +126,19 @@ static const char *cam_icp_dev_type_to_name(
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}
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}
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static inline void cam_icp_dump_debug_info(bool skip_dump)
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{
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struct cam_hw_intf *icp_dev_intf = icp_hw_mgr.icp_dev_intf;
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if (skip_dump)
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return;
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cam_icp_mgr_process_dbg_buf(icp_hw_mgr.icp_dbg_lvl);
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cam_hfi_queue_dump(false);
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icp_dev_intf->hw_ops.process_cmd(
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icp_dev_intf->hw_priv, CAM_ICP_CMD_HW_REG_DUMP, NULL, 0x0);
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}
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static int cam_icp_send_ubwc_cfg(struct cam_icp_hw_mgr *hw_mgr)
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{
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struct cam_hw_intf *icp_dev_intf = hw_mgr->icp_dev_intf;
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@@ -2122,6 +2135,7 @@ static int cam_icp_mgr_cleanup_ctx(struct cam_icp_hw_ctx_data *ctx_data)
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ctx_data->hfi_frame_process.in_free_resource[i] = 0;
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}
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ctx_data->abort_timed_out = false;
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return 0;
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}
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@@ -2605,6 +2619,7 @@ static int cam_icp_mgr_trigger_recovery(struct cam_icp_hw_mgr *hw_mgr)
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sfr_buffer = (struct sfr_buf *)icp_hw_mgr.hfi_mem.sfr_buf.kva;
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CAM_WARN(CAM_ICP, "SFR:%s", sfr_buffer->msg);
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cam_icp_dump_debug_info(false);
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cam_icp_mgr_ipe_bps_get_gdsc_control(hw_mgr);
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cam_icp_ipebps_reset(hw_mgr);
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@@ -2639,7 +2654,6 @@ static int cam_icp_mgr_process_fatal_error(
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BUG();
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}
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rc = cam_icp_mgr_trigger_recovery(hw_mgr);
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cam_icp_mgr_process_dbg_buf(icp_hw_mgr.icp_dbg_lvl);
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}
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return rc;
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@@ -3743,8 +3757,8 @@ static int cam_icp_mgr_abort_handle(
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CAM_ERR(CAM_ICP,
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"FW timeout/err in abort handle command ctx: %u",
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ctx_data->ctx_id);
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cam_icp_mgr_process_dbg_buf(icp_hw_mgr.icp_dbg_lvl);
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cam_hfi_queue_dump();
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cam_icp_dump_debug_info(false);
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ctx_data->abort_timed_out = true;
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}
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}
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@@ -3800,8 +3814,7 @@ static int cam_icp_mgr_destroy_handle(
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rc = -ETIMEDOUT;
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CAM_ERR(CAM_ICP, "FW response timeout: %d for %u",
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rc, ctx_data->ctx_id);
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cam_icp_mgr_process_dbg_buf(icp_hw_mgr.icp_dbg_lvl);
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cam_hfi_queue_dump();
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cam_icp_dump_debug_info(ctx_data->abort_timed_out);
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}
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kfree(destroy_cmd);
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return rc;
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@@ -4206,8 +4219,7 @@ static int cam_icp_mgr_send_fw_init(struct cam_icp_hw_mgr *hw_mgr)
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if (!rem_jiffies) {
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rc = -ETIMEDOUT;
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CAM_ERR(CAM_ICP, "FW response timed out %d", rc);
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cam_icp_mgr_process_dbg_buf(icp_hw_mgr.icp_dbg_lvl);
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cam_hfi_queue_dump();
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cam_icp_dump_debug_info(false);
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}
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CAM_DBG(CAM_ICP, "Done Waiting for INIT DONE Message");
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@@ -4512,8 +4524,7 @@ static int cam_icp_mgr_send_config_io(struct cam_icp_hw_ctx_data *ctx_data,
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ctx_data->ctx_id, ctx_data->acquire_dev_cmd.dev_handle,
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ctx_data->acquire_dev_cmd.session_handle,
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ctx_data->icp_dev_acquire_info->dev_type);
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cam_icp_mgr_process_dbg_buf(icp_hw_mgr.icp_dbg_lvl);
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cam_hfi_queue_dump();
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cam_icp_dump_debug_info(false);
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}
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return rc;
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@@ -4977,7 +4988,7 @@ static int cam_icp_process_stream_settings(
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if (!rem_jiffies) {
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rc = -ETIMEDOUT;
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CAM_ERR(CAM_ICP, "FW response timed out %d", rc);
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cam_hfi_queue_dump();
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cam_icp_dump_debug_info(false);
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}
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end:
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@@ -5750,8 +5761,8 @@ static int cam_icp_mgr_enqueue_abort(
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CAM_ERR(CAM_ICP,
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"FW timeout/err in abort handle command ctx: %u",
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ctx_data->ctx_id);
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cam_icp_mgr_process_dbg_buf(icp_hw_mgr.icp_dbg_lvl);
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cam_hfi_queue_dump();
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cam_icp_dump_debug_info(false);
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ctx_data->abort_timed_out = true;
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return rc;
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}
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}
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@@ -6078,8 +6089,7 @@ static int cam_icp_mgr_create_handle(uint32_t dev_type,
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if (!rem_jiffies) {
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rc = -ETIMEDOUT;
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CAM_ERR(CAM_ICP, "FW response timed out %d", rc);
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cam_icp_mgr_process_dbg_buf(icp_hw_mgr.icp_dbg_lvl);
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cam_hfi_queue_dump();
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cam_icp_dump_debug_info(false);
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}
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if (ctx_data->fw_handle == 0) {
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@@ -6126,8 +6136,7 @@ static int cam_icp_mgr_send_ping(struct cam_icp_hw_ctx_data *ctx_data)
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if (!rem_jiffies) {
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rc = -ETIMEDOUT;
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CAM_ERR(CAM_ICP, "FW response timed out %d", rc);
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cam_icp_mgr_process_dbg_buf(icp_hw_mgr.icp_dbg_lvl);
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cam_hfi_queue_dump();
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cam_icp_dump_debug_info(false);
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}
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return rc;
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@@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef CAM_ICP_HW_MGR_H
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@@ -270,6 +271,7 @@ struct cam_ctx_clk_info {
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* @watch_dog_reset_counter: Counter for watch dog reset
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* @icp_dev_io_info: io config resource
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* @last_flush_req: last flush req for this ctx
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* @abort_timed_out: Indicates if abort timed out
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*/
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struct cam_icp_hw_ctx_data {
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void *context_priv;
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@@ -293,6 +295,7 @@ struct cam_icp_hw_ctx_data {
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struct cam_icp_acquire_dev_info icp_dev_io_info;
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uint64_t last_flush_req;
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char ctx_id_string[128];
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bool abort_timed_out;
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};
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/**
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@@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef CAM_ICP_HW_INTF_H
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@@ -43,6 +44,7 @@ enum cam_icp_cmd_type {
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CAM_ICP_CMD_CLK_UPDATE,
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CAM_ICP_CMD_HW_DUMP,
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CAM_ICP_CMD_HW_MINI_DUMP,
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CAM_ICP_CMD_HW_REG_DUMP,
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CAM_ICP_CMD_MAX,
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};
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@@ -27,8 +27,6 @@
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#define TZ_STATE_SUSPEND 0
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#define TZ_STATE_RESUME 1
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#define LX7_GEN_PURPOSE_REG_OFFSET 0x20
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#define ICP_FW_NAME_MAX_SIZE 32
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#define PC_POLL_DELAY_US 100
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@@ -702,6 +700,21 @@ static int cam_lx7_shutdown(struct cam_hw_info *lx7_info)
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return rc;
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}
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static inline void __cam_lx7_core_reg_dump(
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struct cam_hw_info *lx7_info)
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{
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void __iomem *cirq_base = lx7_info->soc_info.reg_map[LX7_CIRQ_BASE].mem_base;
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void __iomem *csr_base = lx7_info->soc_info.reg_map[LX7_CSR_BASE].mem_base;
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CAM_INFO(CAM_ICP,
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"CIRQ IB_status0:0x%x IB_Status1:0x%x PFault:0x%x CSR debug_status:0x%x debug_ctrl:0x%x",
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cam_io_r_mb(cirq_base + ICP_LX7_CIRQ_IB_STATUS0),
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cam_io_r_mb(cirq_base + ICP_LX7_CIRQ_IB_STATUS1),
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cam_io_r_mb(cirq_base + ICP_LX7_CIRQ_PFAULT_INFO),
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cam_io_r_mb(csr_base + LX7_CSR_DBG_STATUS_REG_OFFSET),
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cam_io_r_mb(csr_base + LX7_CSR_DBG_CTRL_REG_OFFSET));
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}
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/* API controls collapse/resume of ICP */
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static int cam_lx7_core_control(
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struct cam_hw_info *lx7_info,
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@@ -713,16 +726,12 @@ static int cam_lx7_core_control(
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if (core_info->use_sec_pil) {
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rc = qcom_scm_set_remote_state(state, CAM_FW_PAS_ID);
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if (rc)
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if (rc) {
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CAM_ERR(CAM_ICP,
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"remote state set to %s failed rc=%d IB_status0=0x%x IB_Status1=0x%x PFault=0x%x",
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state == TZ_STATE_RESUME ? "resume" : "suspend", rc,
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cam_io_r_mb(lx7_info->soc_info.reg_map[LX7_CIRQ_BASE].mem_base +
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ICP_LX7_CIRQ_IB_STATUS0),
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cam_io_r_mb(lx7_info->soc_info.reg_map[LX7_CIRQ_BASE].mem_base +
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ICP_LX7_CIRQ_IB_STATUS1),
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cam_io_r_mb(lx7_info->soc_info.reg_map[LX7_CIRQ_BASE].mem_base +
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ICP_LX7_CIRQ_PFAULT_INFO));
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"remote state set to %s failed rc=%d",
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(state == TZ_STATE_RESUME ? "resume" : "suspend"), rc);
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__cam_lx7_core_reg_dump(lx7_info);
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}
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} else {
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if (state == TZ_STATE_RESUME) {
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rc = __cam_lx7_power_resume(lx7_info);
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@@ -886,6 +895,11 @@ int cam_lx7_process_cmd(void *priv, uint32_t cmd_type,
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rc = __cam_lx7_fw_mini_dump(lx7_info->core_info, args);
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break;
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}
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case CAM_ICP_CMD_HW_REG_DUMP: {
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__cam_lx7_core_reg_dump(lx7_info);
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rc = 0;
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break;
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}
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default:
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CAM_ERR(CAM_ICP, "invalid command type=%u", cmd_type);
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break;
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@@ -7,6 +7,11 @@
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#ifndef _CAM_LX7_REG_H_
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#define _CAM_LX7_REG_H_
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/* ICP CSR info */
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#define LX7_GEN_PURPOSE_REG_OFFSET 0x20
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#define LX7_CSR_DBG_STATUS_REG_OFFSET 0xC0
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#define LX7_CSR_DBG_CTRL_REG_OFFSET 0xC4
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/* ICP_SYS - Protected reg space defined in AC policy */
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#define ICP_LX7_SYS_RESET 0x0
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#define ICP_LX7_SYS_CONTROL 0x4
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