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@@ -0,0 +1,1440 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+/*
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+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+#ifndef _CAM_IFE_CSID_880_H_
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+#define _CAM_IFE_CSID_880_H_
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+
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+#include <linux/module.h>
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+#include "cam_ife_csid_dev.h"
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+#include "camera_main.h"
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+#include "cam_ife_csid_common.h"
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+#include "cam_ife_csid_hw_ver2.h"
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+#include "cam_irq_controller.h"
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+#include "cam_isp_hw_mgr_intf.h"
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+
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+#define CAM_CSID_VERSION_V880 0x80080000
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+
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+static const struct cam_ife_csid_irq_desc cam_ife_csid_880_rx_irq_desc[] = {
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+ {
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+ .bitmask = BIT(0),
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+ .desc = "DL0_EOT",
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+ },
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+ {
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+ .bitmask = BIT(1),
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+ .desc = "DL1_EOT",
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+ },
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+ {
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+ .bitmask = BIT(2),
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+ .desc = "DL2_EOT",
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+ },
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+ {
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+ .bitmask = BIT(3),
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+ .desc = "DL3_EOT",
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+ },
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+ {
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+ .bitmask = BIT(4),
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+ .desc = "DL0_SOT",
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+ },
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+ {
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+ .bitmask = BIT(5),
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+ .desc = "DL1_SOT",
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+ },
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+ {
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+ .bitmask = BIT(6),
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+ .desc = "DL2_SOT",
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+ },
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+ {
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+ .bitmask = BIT(7),
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+ .desc = "DL3_SOT",
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+ },
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+ {
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+ .bitmask = BIT(8),
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+ .desc = "LONG_PKT",
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+ },
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+ {
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+ .bitmask = BIT(9),
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+ .desc = "SHORT_PKT",
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+ },
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+ {
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+ .bitmask = BIT(10),
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+ .desc = "CPHY_PKT_HDR",
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+ },
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+ {
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+ .bitmask = BIT(11),
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+ .desc = "ERROR_CPHY_EOT_RECEPTION",
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+ },
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+ {
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+ .bitmask = BIT(12),
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+ .desc = "ERROR_CPHY_SOT_RECEPTION",
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+ },
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+ {
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+ .bitmask = BIT(13),
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+ .desc = "ERROR_CPHY_PH_CRC",
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+ },
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+ {
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+ .bitmask = BIT(14),
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+ .desc = "WARNING_ECC",
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+ },
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+ {
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+ .bitmask = BIT(15),
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+ .desc = "ERROR_LANE0_FIFO_OVERFLOW",
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+ },
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+ {
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+ .bitmask = BIT(16),
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+ .desc = "ERROR_LANE1_FIFO_OVERFLOW",
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+ },
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+ {
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+ .bitmask = BIT(17),
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+ .desc = "ERROR_LANE2_FIFO_OVERFLOW",
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+ },
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+ {
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+ .bitmask = BIT(18),
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+ .desc = "ERROR_LANE3_FIFO_OVERFLOW",
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+ },
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+ {
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+ .bitmask = BIT(19),
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+ .desc = "ERROR_CRC",
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+ },
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+ {
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+ .bitmask = BIT(20),
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+ .desc = "ERROR_ECC",
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+ },
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+ {
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+ .bitmask = BIT(21),
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+ .desc = "ERROR_MMAPPED_VC_DT",
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+ },
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+ {
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+ .bitmask = BIT(22),
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+ .desc = "ERROR_UNMAPPED_VC_DT",
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+ },
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+ {
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+ .bitmask = BIT(23),
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+ .desc = "ERROR_STREAM_UNDERFLOW",
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+ },
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+ {
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+ .bitmask = BIT(24),
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+ .desc = "ERROR_UNBOUNDED_FRAME",
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+ },
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+ {
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+ .bitmask = BIT(25),
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+ .desc = "ERROR_ILLEGAL_PROGRAMMING_IRQ",
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+ },
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+ {
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+ .bitmask = BIT(26),
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+ .desc = "INFO_SENSOR_MODE_ID_CHANGE_IRQ",
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+ },
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+};
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+
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+static const struct cam_ife_csid_irq_desc cam_ife_csid_880_path_irq_desc[] = {
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+ {
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+ .bitmask = BIT(0),
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+ .err_type = CAM_ISP_HW_ERROR_CSID_FATAL,
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+ .desc = "ILLEGAL_PROGRAMMING",
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+ .err_handler = cam_ife_csid_ver2_print_illegal_programming_irq_status,
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+ },
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+ {
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+ .bitmask = BIT(1),
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+ .desc = "EROOR_MSG_FIFO_OVERFLOW",
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+ },
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+ {
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+ .bitmask = BIT(2),
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+ .desc = "ERROR_FIFO_OVERFLOW",
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+ },
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+ {
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+ .bitmask = BIT(3),
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+ .desc = "CAMIF_EOF",
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+ },
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+ {
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+ .bitmask = BIT(4),
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+ .desc = "CAMIF_SOF",
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+ },
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+ {
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+ .bitmask = BIT(5),
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+ .desc = "FRAME_DROP_EOF",
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+ },
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+ {
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+ .bitmask = BIT(6),
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+ .desc = "FRAME_DROP_EOL",
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+ },
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+ {
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+ .bitmask = BIT(7),
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+ .desc = "FRAME_DROP_SOL",
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+ },
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+ {
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+ .bitmask = BIT(8),
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+ .desc = "FRAME_DROP_SOF",
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+ },
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+ {
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+ .bitmask = BIT(9),
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+ .desc = "INFO_INPUT_EOF",
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+ },
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+ {
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+ .bitmask = BIT(10),
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+ .desc = "INFO_INPUT_EOL",
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+ },
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+ {
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+ .bitmask = BIT(11),
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+ .desc = "INFO_INPUT_SOL",
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+ },
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+ {
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+ .bitmask = BIT(12),
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+ .desc = "INFO_INPUT_SOF",
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+ },
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+ {
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+ .bitmask = BIT(13),
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+ .err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE,
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+ .desc = "ERROR_PIX_COUNT",
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+ .err_handler = cam_ife_csid_ver2_print_format_measure_info,
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+ },
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+ {
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+ .bitmask = BIT(14),
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+ .err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE,
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+ .desc = "ERROR_LINE_COUNT",
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+ .err_handler = cam_ife_csid_ver2_print_format_measure_info,
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+ },
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+ {
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+ .bitmask = BIT(15),
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+ .desc = "VCDT_GRP0_SEL",
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+ },
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+ {
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+ .bitmask = BIT(16),
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+ .desc = "VCDT_GRP1_SEL",
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+ },
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+ {
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+ .bitmask = BIT(17),
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+ .desc = "VCDT_GRP_CHANGE",
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+ },
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+ {
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+ .bitmask = BIT(18),
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+ .desc = "FRAME_DROP",
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+ },
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+ {
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+ .bitmask = BIT(19),
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+ .err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
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+ .desc = "OVERFLOW_RECOVERY: Back pressure/output fifo ovrfl",
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+ },
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+ {
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+ .bitmask = BIT(20),
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+ .desc = "ERROR_REC_CCIF_VIOLATION From Camif",
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+ },
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+ {
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+ .bitmask = BIT(21),
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+ .desc = "CAMIF_EPOCH0",
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+ },
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+ {
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+ .bitmask = BIT(22),
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+ .desc = "CAMIF_EPOCH1",
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+ },
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+ {
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+ .bitmask = BIT(23),
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+ .desc = "RUP_DONE",
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+ },
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+ {
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+ .bitmask = BIT(24),
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+ .desc = "ILLEGAL_BATCH_ID",
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+ },
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+ {
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+ .bitmask = BIT(25),
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+ .desc = "BATCH_END_MISSING_VIOLATION",
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+ },
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+ {
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+ .bitmask = BIT(26),
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+ .desc = "HEIGHT_VIOLATION",
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+ },
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+ {
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+ .bitmask = BIT(27),
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+ .desc = "WIDTH_VIOLATION",
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+ },
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+ {
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+ .bitmask = BIT(28),
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+ .desc = "SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP",
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+ .err_handler = cam_ife_csid_hw_ver2_mup_mismatch_handler,
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+ },
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+ {
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+ .bitmask = BIT(29),
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+ .desc = "CCIF_VIOLATION: Bad frame timings",
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+ },
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+};
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+
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+static const struct cam_ife_csid_top_irq_desc cam_ife_csid_880_top_irq_desc[] = {
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+ {
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+ .bitmask = BIT(1),
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+ .err_type = CAM_ISP_HW_ERROR_CSID_SENSOR_SWITCH_ERROR,
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+ .err_name = "FATAL_SENSOR_SWITCHING_IRQ",
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+ .desc = "Fatal Error duirng dynamically switching between 2 sensors",
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+ },
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+ {
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+ .bitmask = BIT(18),
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+ .err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
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+ .err_name = "ERROR_NO_VOTE_DN",
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+ .desc = "vote_up is asserted before IDLE is encountered in a frame",
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+ },
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+ {
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+ .bitmask = BIT(19),
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+ .err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
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+ .err_name = "ERROR_VOTE_UP_LATE",
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+ .desc = "vote_up is asserted at the same time as an SOF",
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+ },
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+ {
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+ .bitmask = BIT(20),
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+ .err_type = CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW,
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+ .err_name = "ERROR_RDI_LINE_BUFFER_CONFLICT",
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+ .desc = "Two or more RDIs programmed to access the shared line buffer",
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+ .err_handler = cam_ife_csid_hw_ver2_rdi_line_buffer_conflict_handler,
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+ },
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+};
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+
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+static struct cam_irq_register_set cam_ife_csid_880_irq_reg_set[9] = {
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+ /* Top */
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+ {
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+ .mask_reg_offset = 0x00001080,
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+ .clear_reg_offset = 0x00001084,
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+ .status_reg_offset = 0x0000107C,
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+ .set_reg_offset = 0x00001088,
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+ .test_set_val = BIT(0),
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+ .test_sub_val = BIT(0),
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+ },
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+ /* RX */
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+ {
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+ .mask_reg_offset = 0x000010A0,
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+ .clear_reg_offset = 0x000010A4,
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+ .status_reg_offset = 0x0000109C,
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+ },
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+ /* RDI0 */
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+ {
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+ .mask_reg_offset = 0x000010F0,
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+ .clear_reg_offset = 0x000010F4,
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+ .status_reg_offset = 0x000010EC,
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+ },
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+ /* RDI1 */
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+ {
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+ .mask_reg_offset = 0x00001100,
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+ .clear_reg_offset = 0x00001104,
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+ .status_reg_offset = 0x000010FC,
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+ },
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+ /* RDI2 */
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+ {
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+ .mask_reg_offset = 0x00001110,
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+ .clear_reg_offset = 0x00001114,
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+ .status_reg_offset = 0x0000110C,
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+ },
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+ /* RDI3 */
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+ {
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+ .mask_reg_offset = 0x00001120,
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+ .clear_reg_offset = 0x00001124,
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+ .status_reg_offset = 0x0000111C,
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+ },
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+ /* RDI4 */
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+ {
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+ .mask_reg_offset = 0x00001130,
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+ .clear_reg_offset = 0x00001134,
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+ .status_reg_offset = 0x0000112C,
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+ },
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+ /* IPP */
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+ {
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+ .mask_reg_offset = 0x000010B0,
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+ .clear_reg_offset = 0x000010B4,
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+ .status_reg_offset = 0x000010AC,
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+ },
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+ /* PPP */
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+ {
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+ .mask_reg_offset = 0x000010D0,
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+ .clear_reg_offset = 0x000010D4,
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+ .status_reg_offset = 0x000010CC,
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+ },
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+};
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+
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+static struct cam_irq_controller_reg_info cam_ife_csid_880_top_irq_reg_info = {
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+ .num_registers = 1,
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+ .irq_reg_set = &cam_ife_csid_880_irq_reg_set[CAM_IFE_CSID_IRQ_REG_TOP],
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+ .global_irq_cmd_offset = 0x00001014,
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+ .global_clear_bitmask = 0x00000001,
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+ .global_set_bitmask = 0x00000010,
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+ .clear_all_bitmask = 0xFFFFFFFF,
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+};
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+
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+static struct cam_irq_controller_reg_info cam_ife_csid_880_rx_irq_reg_info = {
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+ .num_registers = 1,
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+ .irq_reg_set = &cam_ife_csid_880_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RX],
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+ .global_irq_cmd_offset = 0, /* intentionally set to zero */
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+};
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+
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+static struct cam_irq_controller_reg_info cam_ife_csid_880_path_irq_reg_info[7] = {
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+ {
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+ .num_registers = 1,
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+ .irq_reg_set = &cam_ife_csid_880_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_0],
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+ .global_irq_cmd_offset = 0, /* intentionally set to zero */
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+ },
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+ {
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+ .num_registers = 1,
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+ .irq_reg_set = &cam_ife_csid_880_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_1],
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+ .global_irq_cmd_offset = 0, /* intentionally set to zero */
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+ },
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+ {
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+ .num_registers = 1,
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+ .irq_reg_set = &cam_ife_csid_880_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_2],
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+ .global_irq_cmd_offset = 0, /* intentionally set to zero */
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+ },
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+ {
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+ .num_registers = 1,
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+ .irq_reg_set = &cam_ife_csid_880_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_3],
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+ .global_irq_cmd_offset = 0, /* intentionally set to zero */
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+ },
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+ {
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+ .num_registers = 1,
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+ .irq_reg_set = &cam_ife_csid_880_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_4],
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+ .global_irq_cmd_offset = 0, /* intentionally set to zero */
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+ },
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+ {
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+ .num_registers = 1,
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+ .irq_reg_set = &cam_ife_csid_880_irq_reg_set[CAM_IFE_CSID_IRQ_REG_IPP],
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+ .global_irq_cmd_offset = 0, /* intentionally set to zero */
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+ },
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+ {
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+ .num_registers = 1,
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+ .irq_reg_set = &cam_ife_csid_880_irq_reg_set[CAM_IFE_CSID_IRQ_REG_PPP],
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+ .global_irq_cmd_offset = 0, /* intentionally set to zero */
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+ },
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+};
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+
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+static struct cam_irq_register_set cam_ife_csid_880_buf_done_irq_reg_set[1] = {
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+ {
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+ .mask_reg_offset = 0x00001090,
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+ .clear_reg_offset = 0x00001094,
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|
|
+ .status_reg_offset = 0x0000108C,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct cam_irq_controller_reg_info
|
|
|
+ cam_ife_csid_880_buf_done_irq_reg_info = {
|
|
|
+ .num_registers = 1,
|
|
|
+ .irq_reg_set = cam_ife_csid_880_buf_done_irq_reg_set,
|
|
|
+ .global_irq_cmd_offset = 0, /* intentionally set to zero */
|
|
|
+};
|
|
|
+
|
|
|
+static struct cam_ife_csid_ver2_path_reg_info
|
|
|
+ cam_ife_csid_880_ipp_reg_info = {
|
|
|
+ .irq_status_addr = 0x10AC,
|
|
|
+ .irq_mask_addr = 0x10B0,
|
|
|
+ .irq_clear_addr = 0x10B4,
|
|
|
+ .irq_set_addr = 0x10B8,
|
|
|
+ .cfg0_addr = 0x1300,
|
|
|
+ .ctrl_addr = 0x1304,
|
|
|
+ .debug_clr_cmd_addr = 0x1308,
|
|
|
+ .multi_vcdt_cfg0_addr = 0x130C,
|
|
|
+ .cfg1_addr = 0x1310,
|
|
|
+ .err_recovery_cfg0_addr = 0x1318,
|
|
|
+ .err_recovery_cfg1_addr = 0x131C,
|
|
|
+ .err_recovery_cfg2_addr = 0x1320,
|
|
|
+ .bin_pd_detect_cfg0_addr = 0x1324,
|
|
|
+ .bin_pd_detect_cfg1_addr = 0x1328,
|
|
|
+ .bin_pd_detect_cfg2_addr = 0x132C,
|
|
|
+ .camif_frame_cfg_addr = 0x1330,
|
|
|
+ .epoch_irq_cfg_addr = 0x1334,
|
|
|
+ .epoch0_subsample_ptrn_addr = 0x1338,
|
|
|
+ .epoch1_subsample_ptrn_addr = 0x133C,
|
|
|
+ .debug_camif_1_addr = 0x1340,
|
|
|
+ .debug_camif_0_addr = 0x1344,
|
|
|
+ .debug_halt_status_addr = 0x1348,
|
|
|
+ .debug_misr_val0_addr = 0x134C,
|
|
|
+ .debug_misr_val1_addr = 0x1350,
|
|
|
+ .debug_misr_val2_addr = 0x1354,
|
|
|
+ .debug_misr_val3_addr = 0x1358,
|
|
|
+ .hcrop_addr = 0x135c,
|
|
|
+ .vcrop_addr = 0x1360,
|
|
|
+ .pix_drop_pattern_addr = 0x1364,
|
|
|
+ .pix_drop_period_addr = 0x1368,
|
|
|
+ .line_drop_pattern_addr = 0x136C,
|
|
|
+ .line_drop_period_addr = 0x1370,
|
|
|
+ .frm_drop_pattern_addr = 0x1374,
|
|
|
+ .frm_drop_period_addr = 0x1378,
|
|
|
+ .irq_subsample_pattern_addr = 0x137C,
|
|
|
+ .irq_subsample_period_addr = 0x1380,
|
|
|
+ .format_measure_cfg0_addr = 0x1384,
|
|
|
+ .format_measure_cfg1_addr = 0x1388,
|
|
|
+ .format_measure0_addr = 0x138C,
|
|
|
+ .format_measure1_addr = 0x1390,
|
|
|
+ .format_measure2_addr = 0x1394,
|
|
|
+ .timestamp_curr0_sof_addr = 0x1398,
|
|
|
+ .timestamp_curr1_sof_addr = 0x139C,
|
|
|
+ .timestamp_perv0_sof_addr = 0x13A0,
|
|
|
+ .timestamp_perv1_sof_addr = 0x13A4,
|
|
|
+ .timestamp_curr0_eof_addr = 0x13A8,
|
|
|
+ .timestamp_curr1_eof_addr = 0x13AC,
|
|
|
+ .timestamp_perv0_eof_addr = 0x13B0,
|
|
|
+ .timestamp_perv1_eof_addr = 0x13B4,
|
|
|
+ .lut_bank_cfg_addr = 0x13B8,
|
|
|
+ .batch_id_cfg0_addr = 0x13BC,
|
|
|
+ .batch_id_cfg1_addr = 0x13C0,
|
|
|
+ .batch_period_cfg_addr = 0x13C4,
|
|
|
+ .batch_stream_id_cfg_addr = 0x13C8,
|
|
|
+ .epoch0_cfg_batch_id0_addr = 0x13CC,
|
|
|
+ .epoch1_cfg_batch_id0_addr = 0x13D0,
|
|
|
+ .epoch0_cfg_batch_id1_addr = 0x13D4,
|
|
|
+ .epoch1_cfg_batch_id1_addr = 0x13D8,
|
|
|
+ .epoch0_cfg_batch_id2_addr = 0x13DC,
|
|
|
+ .epoch1_cfg_batch_id2_addr = 0x13E0,
|
|
|
+ .epoch0_cfg_batch_id3_addr = 0x13E4,
|
|
|
+ .epoch1_cfg_batch_id3_addr = 0x13E8,
|
|
|
+ .epoch0_cfg_batch_id4_addr = 0x13EC,
|
|
|
+ .epoch1_cfg_batch_id4_addr = 0x13F0,
|
|
|
+ .epoch0_cfg_batch_id5_addr = 0x13F4,
|
|
|
+ .epoch1_cfg_batch_id5_addr = 0x13F8,
|
|
|
+ .secure_mask_cfg0 = 0x10,
|
|
|
+ .path_batch_status = 0x13FC,
|
|
|
+ .path_frame_id = 0x1400,
|
|
|
+
|
|
|
+ /* configurations */
|
|
|
+ .resume_frame_boundary = 1,
|
|
|
+ .binning_supported = 0x7,
|
|
|
+ .capabilities = CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
|
|
|
+ .start_mode_internal = 0x0,
|
|
|
+ .start_mode_global = 0x1,
|
|
|
+ .start_mode_master = 0x2,
|
|
|
+ .start_mode_slave = 0x3,
|
|
|
+ .sof_retiming_dis_shift = 5,
|
|
|
+ .start_mode_shift = 2,
|
|
|
+ .start_master_sel_val = 0,
|
|
|
+ .start_master_sel_shift = 4,
|
|
|
+ .crop_v_en_shift_val = 13,
|
|
|
+ .crop_h_en_shift_val = 12,
|
|
|
+ .drop_v_en_shift_val = 11,
|
|
|
+ .drop_h_en_shift_val = 10,
|
|
|
+ .pix_store_en_shift_val = 14,
|
|
|
+ .early_eof_en_shift_val = 16,
|
|
|
+ .bin_h_en_shift_val = 20,
|
|
|
+ .bin_v_en_shift_val = 21,
|
|
|
+ .bin_en_shift_val = 18,
|
|
|
+ .bin_qcfa_en_shift_val = 19,
|
|
|
+ .format_measure_en_shift_val = 8,
|
|
|
+ .timestamp_en_shift_val = 6,
|
|
|
+ .overflow_ctrl_en = 1,
|
|
|
+ .overflow_ctrl_mode_val = 0x8,
|
|
|
+ .min_hbi_shift_val = 4,
|
|
|
+ .start_master_sel_shift_val = 4,
|
|
|
+ .bin_pd_en_shift_val = 0,
|
|
|
+ .bin_pd_blk_w_shift_val = 8,
|
|
|
+ .bin_pd_blk_h_shift_val = 24,
|
|
|
+ .bin_pd_detect_x_offset_shift_val = 0,
|
|
|
+ .bin_pd_detect_x_end_shift_val = 16,
|
|
|
+ .bin_pd_detect_y_offset_shift_val = 0,
|
|
|
+ .bin_pd_detect_y_end_shift_val = 16,
|
|
|
+ .lut_bank_0_sel_val = 0,
|
|
|
+ .lut_bank_1_sel_val = 1,
|
|
|
+ .fatal_err_mask = 0x186007,
|
|
|
+ .non_fatal_err_mask = 0x10000000,
|
|
|
+ .sof_irq_mask = 0x10,
|
|
|
+ .rup_irq_mask = 0x800000,
|
|
|
+ .epoch0_irq_mask = 0x200000,
|
|
|
+ .epoch1_irq_mask = 0x400000,
|
|
|
+ .eof_irq_mask = 0x8,
|
|
|
+ .rup_aup_mask = 0x10001,
|
|
|
+ .top_irq_mask = 0x10,
|
|
|
+ .epoch0_shift_val = 16,
|
|
|
+ .epoch1_shift_val = 0,
|
|
|
+};
|
|
|
+
|
|
|
+static struct cam_ife_csid_ver2_path_reg_info
|
|
|
+ cam_ife_csid_880_ppp_reg_info = {
|
|
|
+ .irq_status_addr = 0x10CC,
|
|
|
+ .irq_mask_addr = 0x10D0,
|
|
|
+ .irq_clear_addr = 0x10D4,
|
|
|
+ .irq_set_addr = 0x10D8,
|
|
|
+ .cfg0_addr = 0x1B00,
|
|
|
+ .ctrl_addr = 0x1B04,
|
|
|
+ .debug_clr_cmd_addr = 0x1B08,
|
|
|
+ .multi_vcdt_cfg0_addr = 0x1B0C,
|
|
|
+ .cfg1_addr = 0x1B10,
|
|
|
+ .sparse_pd_extractor_cfg_addr = 0x1B14,
|
|
|
+ .err_recovery_cfg0_addr = 0x1B18,
|
|
|
+ .err_recovery_cfg1_addr = 0x1B1C,
|
|
|
+ .err_recovery_cfg2_addr = 0x1B20,
|
|
|
+ .camif_frame_cfg_addr = 0x1B30,
|
|
|
+ .epoch_irq_cfg_addr = 0x1B34,
|
|
|
+ .epoch0_subsample_ptrn_addr = 0x1B38,
|
|
|
+ .epoch1_subsample_ptrn_addr = 0x1B3C,
|
|
|
+ .debug_camif_1_addr = 0x1B40,
|
|
|
+ .debug_camif_0_addr = 0x1B44,
|
|
|
+ .debug_halt_status_addr = 0x1B48,
|
|
|
+ .debug_misr_val0_addr = 0x1B4C,
|
|
|
+ .debug_misr_val1_addr = 0x1B50,
|
|
|
+ .debug_misr_val2_addr = 0x1B54,
|
|
|
+ .debug_misr_val3_addr = 0x1B58,
|
|
|
+ .hcrop_addr = 0x1B5c,
|
|
|
+ .vcrop_addr = 0x1B60,
|
|
|
+ .pix_drop_pattern_addr = 0x1B64,
|
|
|
+ .pix_drop_period_addr = 0x1B68,
|
|
|
+ .line_drop_pattern_addr = 0x1B6C,
|
|
|
+ .line_drop_period_addr = 0x1B70,
|
|
|
+ .frm_drop_pattern_addr = 0x1B74,
|
|
|
+ .frm_drop_period_addr = 0x1B78,
|
|
|
+ .irq_subsample_pattern_addr = 0x1B7C,
|
|
|
+ .irq_subsample_period_addr = 0x1B80,
|
|
|
+ .format_measure_cfg0_addr = 0x1B84,
|
|
|
+ .format_measure_cfg1_addr = 0x1B88,
|
|
|
+ .format_measure0_addr = 0x1B8C,
|
|
|
+ .format_measure1_addr = 0x1B90,
|
|
|
+ .format_measure2_addr = 0x1B94,
|
|
|
+ .timestamp_curr0_sof_addr = 0x1B98,
|
|
|
+ .timestamp_curr1_sof_addr = 0x1B9C,
|
|
|
+ .timestamp_perv0_sof_addr = 0x1BA0,
|
|
|
+ .timestamp_perv1_sof_addr = 0x1BA4,
|
|
|
+ .timestamp_curr0_eof_addr = 0x1BA8,
|
|
|
+ .timestamp_curr1_eof_addr = 0x1BAC,
|
|
|
+ .timestamp_perv0_eof_addr = 0x1BB0,
|
|
|
+ .timestamp_perv1_eof_addr = 0x1BB4,
|
|
|
+ .lut_bank_cfg_addr = 0x1BB8,
|
|
|
+ .batch_id_cfg0_addr = 0x1BBC,
|
|
|
+ .batch_id_cfg1_addr = 0x1BC0,
|
|
|
+ .batch_period_cfg_addr = 0x1BC4,
|
|
|
+ .batch_stream_id_cfg_addr = 0x1BC8,
|
|
|
+ .epoch0_cfg_batch_id0_addr = 0x1BCC,
|
|
|
+ .epoch1_cfg_batch_id0_addr = 0x1BD0,
|
|
|
+ .epoch0_cfg_batch_id1_addr = 0x1BD4,
|
|
|
+ .epoch1_cfg_batch_id1_addr = 0x1BD8,
|
|
|
+ .epoch0_cfg_batch_id2_addr = 0x1BDC,
|
|
|
+ .epoch1_cfg_batch_id2_addr = 0x1BE0,
|
|
|
+ .epoch0_cfg_batch_id3_addr = 0x1BE4,
|
|
|
+ .epoch1_cfg_batch_id3_addr = 0x1BE8,
|
|
|
+ .epoch0_cfg_batch_id4_addr = 0x1BEC,
|
|
|
+ .epoch1_cfg_batch_id4_addr = 0x1BF0,
|
|
|
+ .epoch0_cfg_batch_id5_addr = 0x1BF4,
|
|
|
+ .epoch1_cfg_batch_id5_addr = 0x1BF8,
|
|
|
+ .secure_mask_cfg0 = 0x14,
|
|
|
+ .path_batch_status = 0x1BFC,
|
|
|
+ .path_frame_id = 0x1C00,
|
|
|
+
|
|
|
+ /* configurations */
|
|
|
+ .capabilities = CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
|
|
|
+ .resume_frame_boundary = 1,
|
|
|
+ .start_mode_shift = 2,
|
|
|
+ .start_mode_internal = 0x0,
|
|
|
+ .start_mode_global = 0x1,
|
|
|
+ .start_mode_master = 0x2,
|
|
|
+ .start_mode_slave = 0x3,
|
|
|
+ .start_master_sel_val = 3,
|
|
|
+ .start_master_sel_shift = 4,
|
|
|
+ .binning_supported = 0x1,
|
|
|
+ .bin_h_en_shift_val = 18,
|
|
|
+ .bin_en_shift_val = 18,
|
|
|
+ .early_eof_en_shift_val = 16,
|
|
|
+ .pix_store_en_shift_val = 14,
|
|
|
+ .crop_v_en_shift_val = 13,
|
|
|
+ .crop_h_en_shift_val = 12,
|
|
|
+ .drop_v_en_shift_val = 11,
|
|
|
+ .drop_h_en_shift_val = 10,
|
|
|
+ .format_measure_en_shift_val = 8,
|
|
|
+ .timestamp_en_shift_val = 6,
|
|
|
+ .overflow_ctrl_en = 1,
|
|
|
+ .overflow_ctrl_mode_val = 0x8,
|
|
|
+ .min_hbi_shift_val = 4,
|
|
|
+ .start_master_sel_shift_val = 4,
|
|
|
+ .lut_bank_0_sel_val = 0,
|
|
|
+ .lut_bank_1_sel_val = 1,
|
|
|
+ .fatal_err_mask = 0x186007,
|
|
|
+ .non_fatal_err_mask = 0x10000000,
|
|
|
+ .rup_aup_mask = 0x40004,
|
|
|
+ .top_irq_mask = 0x40,
|
|
|
+ .epoch0_shift_val = 16,
|
|
|
+ .epoch1_shift_val = 0,
|
|
|
+ .sof_retiming_dis_shift = 5,
|
|
|
+};
|
|
|
+
|
|
|
+static struct cam_ife_csid_ver2_path_reg_info
|
|
|
+ cam_ife_csid_880_rdi_0_reg_info = {
|
|
|
+ .irq_status_addr = 0x10EC,
|
|
|
+ .irq_mask_addr = 0x10F0,
|
|
|
+ .irq_clear_addr = 0x10F4,
|
|
|
+ .irq_set_addr = 0x10F8,
|
|
|
+ .cfg0_addr = 0x1500,
|
|
|
+ .ctrl_addr = 0x1504,
|
|
|
+ .debug_clr_cmd_addr = 0x1508,
|
|
|
+ .multi_vcdt_cfg0_addr = 0x150C,
|
|
|
+ .cfg1_addr = 0x1510,
|
|
|
+ .err_recovery_cfg0_addr = 0x1514,
|
|
|
+ .err_recovery_cfg1_addr = 0x1518,
|
|
|
+ .err_recovery_cfg2_addr = 0x151C,
|
|
|
+ .debug_byte_cntr_ping_addr = 0x1520,
|
|
|
+ .debug_byte_cntr_pong_addr = 0x1524,
|
|
|
+ .camif_frame_cfg_addr = 0x1528,
|
|
|
+ .epoch_irq_cfg_addr = 0x152C,
|
|
|
+ .epoch0_subsample_ptrn_addr = 0x1530,
|
|
|
+ .epoch1_subsample_ptrn_addr = 0x1534,
|
|
|
+ .debug_camif_1_addr = 0x1538,
|
|
|
+ .debug_camif_0_addr = 0x153C,
|
|
|
+ .frm_drop_pattern_addr = 0x1540,
|
|
|
+ .frm_drop_period_addr = 0x1544,
|
|
|
+ .irq_subsample_pattern_addr = 0x1548,
|
|
|
+ .irq_subsample_period_addr = 0x154C,
|
|
|
+ .hcrop_addr = 0x1550,
|
|
|
+ .vcrop_addr = 0x1554,
|
|
|
+ .pix_drop_pattern_addr = 0x1558,
|
|
|
+ .pix_drop_period_addr = 0x155C,
|
|
|
+ .line_drop_pattern_addr = 0x1560,
|
|
|
+ .line_drop_period_addr = 0x1564,
|
|
|
+ .debug_halt_status_addr = 0x1568,
|
|
|
+ .debug_misr_val0_addr = 0x1570,
|
|
|
+ .debug_misr_val1_addr = 0x1574,
|
|
|
+ .debug_misr_val2_addr = 0x1578,
|
|
|
+ .debug_misr_val3_addr = 0x157C,
|
|
|
+ .format_measure_cfg0_addr = 0x1580,
|
|
|
+ .format_measure_cfg1_addr = 0x1584,
|
|
|
+ .format_measure0_addr = 0x1588,
|
|
|
+ .format_measure1_addr = 0x158C,
|
|
|
+ .format_measure2_addr = 0x1590,
|
|
|
+ .timestamp_curr0_sof_addr = 0x1594,
|
|
|
+ .timestamp_curr1_sof_addr = 0x1598,
|
|
|
+ .timestamp_perv0_sof_addr = 0x159C,
|
|
|
+ .timestamp_perv1_sof_addr = 0x15A0,
|
|
|
+ .timestamp_curr0_eof_addr = 0x15A4,
|
|
|
+ .timestamp_curr1_eof_addr = 0x15A8,
|
|
|
+ .timestamp_perv0_eof_addr = 0x15AC,
|
|
|
+ .timestamp_perv1_eof_addr = 0x15B0,
|
|
|
+ .batch_id_cfg0_addr = 0x15B4,
|
|
|
+ .batch_id_cfg1_addr = 0x15B8,
|
|
|
+ .batch_period_cfg_addr = 0x15BC,
|
|
|
+ .batch_stream_id_cfg_addr = 0x15C0,
|
|
|
+ .epoch0_cfg_batch_id0_addr = 0x15C4,
|
|
|
+ .epoch1_cfg_batch_id0_addr = 0x15C8,
|
|
|
+ .epoch0_cfg_batch_id1_addr = 0x15CC,
|
|
|
+ .epoch1_cfg_batch_id1_addr = 0x15D0,
|
|
|
+ .epoch0_cfg_batch_id2_addr = 0x15D4,
|
|
|
+ .epoch1_cfg_batch_id2_addr = 0x15D8,
|
|
|
+ .epoch0_cfg_batch_id3_addr = 0x15DC,
|
|
|
+ .epoch1_cfg_batch_id3_addr = 0x15E0,
|
|
|
+ .epoch0_cfg_batch_id4_addr = 0x15E4,
|
|
|
+ .epoch1_cfg_batch_id4_addr = 0x15E8,
|
|
|
+ .epoch0_cfg_batch_id5_addr = 0x15EC,
|
|
|
+ .epoch1_cfg_batch_id5_addr = 0x15F0,
|
|
|
+ .path_batch_status = 0x15F4,
|
|
|
+ .path_frame_id = 0x15F8,
|
|
|
+
|
|
|
+ /* configurations */
|
|
|
+ .resume_frame_boundary = 1,
|
|
|
+ .overflow_ctrl_en = 1,
|
|
|
+ .capabilities = CAM_IFE_CSID_CAP_INPUT_LCR |
|
|
|
+ CAM_IFE_CSID_CAP_RDI_UNPACK_MSB |
|
|
|
+ CAM_IFE_CSID_CAP_LINE_SMOOTHING_IN_RDI |
|
|
|
+ CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
|
|
|
+ .overflow_ctrl_mode_val = 0x8,
|
|
|
+ .offline_mode_supported = 1,
|
|
|
+ .mipi_pack_supported = 1,
|
|
|
+ .packing_fmt_shift_val = 15,
|
|
|
+ .plain_alignment_shift_val = 11,
|
|
|
+ .plain_fmt_shift_val = 12,
|
|
|
+ .crop_v_en_shift_val = 8,
|
|
|
+ .crop_h_en_shift_val = 7,
|
|
|
+ .drop_v_en_shift_val = 6,
|
|
|
+ .drop_h_en_shift_val = 5,
|
|
|
+ .early_eof_en_shift_val = 14,
|
|
|
+ .format_measure_en_shift_val = 3,
|
|
|
+ .timestamp_en_shift_val = 6,
|
|
|
+ .debug_byte_cntr_rst_shift_val = 2,
|
|
|
+ .offline_mode_en_shift_val = 2,
|
|
|
+ .ccif_violation_en = 1,
|
|
|
+ .fatal_err_mask = 0x186005,
|
|
|
+ .non_fatal_err_mask = 0x10000000,
|
|
|
+ .sof_irq_mask = 0x10,
|
|
|
+ .rup_irq_mask = 0x800000,
|
|
|
+ .epoch0_irq_mask = 0x200000,
|
|
|
+ .epoch1_irq_mask = 0x400000,
|
|
|
+ .eof_irq_mask = 0x8,
|
|
|
+ .rup_aup_mask = 0x100010,
|
|
|
+ .top_irq_mask = 0x100,
|
|
|
+ .epoch0_shift_val = 16,
|
|
|
+ .epoch1_shift_val = 0,
|
|
|
+ .pix_store_en_shift_val = 10,
|
|
|
+ .sof_retiming_dis_shift = 5,
|
|
|
+ .default_out_format = CAM_FORMAT_PLAIN16_16,
|
|
|
+};
|
|
|
+
|
|
|
+static struct cam_ife_csid_ver2_path_reg_info
|
|
|
+ cam_ife_csid_880_rdi_1_reg_info = {
|
|
|
+ .irq_status_addr = 0x10FC,
|
|
|
+ .irq_mask_addr = 0x1100,
|
|
|
+ .irq_clear_addr = 0x1104,
|
|
|
+ .irq_set_addr = 0x1108,
|
|
|
+ .cfg0_addr = 0x1600,
|
|
|
+ .ctrl_addr = 0x1604,
|
|
|
+ .debug_clr_cmd_addr = 0x1608,
|
|
|
+ .multi_vcdt_cfg0_addr = 0x160C,
|
|
|
+ .cfg1_addr = 0x1610,
|
|
|
+ .err_recovery_cfg0_addr = 0x1614,
|
|
|
+ .err_recovery_cfg1_addr = 0x1618,
|
|
|
+ .err_recovery_cfg2_addr = 0x161C,
|
|
|
+ .debug_byte_cntr_ping_addr = 0x1620,
|
|
|
+ .debug_byte_cntr_pong_addr = 0x1624,
|
|
|
+ .camif_frame_cfg_addr = 0x1628,
|
|
|
+ .epoch_irq_cfg_addr = 0x162C,
|
|
|
+ .epoch0_subsample_ptrn_addr = 0x1630,
|
|
|
+ .epoch1_subsample_ptrn_addr = 0x1634,
|
|
|
+ .debug_camif_1_addr = 0x1638,
|
|
|
+ .debug_camif_0_addr = 0x163C,
|
|
|
+ .frm_drop_pattern_addr = 0x1640,
|
|
|
+ .frm_drop_period_addr = 0x1644,
|
|
|
+ .irq_subsample_pattern_addr = 0x1648,
|
|
|
+ .irq_subsample_period_addr = 0x164C,
|
|
|
+ .hcrop_addr = 0x1650,
|
|
|
+ .vcrop_addr = 0x1654,
|
|
|
+ .pix_drop_pattern_addr = 0x1658,
|
|
|
+ .pix_drop_period_addr = 0x165C,
|
|
|
+ .line_drop_pattern_addr = 0x1660,
|
|
|
+ .line_drop_period_addr = 0x1664,
|
|
|
+ .debug_halt_status_addr = 0x166C,
|
|
|
+ .debug_misr_val0_addr = 0x1670,
|
|
|
+ .debug_misr_val1_addr = 0x1674,
|
|
|
+ .debug_misr_val2_addr = 0x1678,
|
|
|
+ .debug_misr_val3_addr = 0x167C,
|
|
|
+ .format_measure_cfg0_addr = 0x1680,
|
|
|
+ .format_measure_cfg1_addr = 0x1684,
|
|
|
+ .format_measure0_addr = 0x1688,
|
|
|
+ .format_measure1_addr = 0x168C,
|
|
|
+ .format_measure2_addr = 0x1690,
|
|
|
+ .timestamp_curr0_sof_addr = 0x1694,
|
|
|
+ .timestamp_curr1_sof_addr = 0x1698,
|
|
|
+ .timestamp_perv0_sof_addr = 0x169C,
|
|
|
+ .timestamp_perv1_sof_addr = 0x16A0,
|
|
|
+ .timestamp_curr0_eof_addr = 0x16A4,
|
|
|
+ .timestamp_curr1_eof_addr = 0x16A8,
|
|
|
+ .timestamp_perv0_eof_addr = 0x16AC,
|
|
|
+ .timestamp_perv1_eof_addr = 0x16B0,
|
|
|
+ .batch_id_cfg0_addr = 0x16B4,
|
|
|
+ .batch_id_cfg1_addr = 0x16B8,
|
|
|
+ .batch_period_cfg_addr = 0x16BC,
|
|
|
+ .batch_stream_id_cfg_addr = 0x16C0,
|
|
|
+ .epoch0_cfg_batch_id0_addr = 0x16C4,
|
|
|
+ .epoch1_cfg_batch_id0_addr = 0x16C8,
|
|
|
+ .epoch0_cfg_batch_id1_addr = 0x16CC,
|
|
|
+ .epoch1_cfg_batch_id1_addr = 0x16D0,
|
|
|
+ .epoch0_cfg_batch_id2_addr = 0x16D4,
|
|
|
+ .epoch1_cfg_batch_id2_addr = 0x16D8,
|
|
|
+ .epoch0_cfg_batch_id3_addr = 0x16DC,
|
|
|
+ .epoch1_cfg_batch_id3_addr = 0x16E0,
|
|
|
+ .epoch0_cfg_batch_id4_addr = 0x16E4,
|
|
|
+ .epoch1_cfg_batch_id4_addr = 0x16E8,
|
|
|
+ .epoch0_cfg_batch_id5_addr = 0x16EC,
|
|
|
+ .epoch1_cfg_batch_id5_addr = 0x16F0,
|
|
|
+ .secure_mask_cfg0 = 0x1C,
|
|
|
+ .path_batch_status = 0x16F4,
|
|
|
+ .path_frame_id = 0x16F8,
|
|
|
+
|
|
|
+ /* configurations */
|
|
|
+ .resume_frame_boundary = 1,
|
|
|
+ .overflow_ctrl_en = 1,
|
|
|
+ .capabilities = CAM_IFE_CSID_CAP_INPUT_LCR |
|
|
|
+ CAM_IFE_CSID_CAP_RDI_UNPACK_MSB |
|
|
|
+ CAM_IFE_CSID_CAP_LINE_SMOOTHING_IN_RDI |
|
|
|
+ CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
|
|
|
+ .overflow_ctrl_mode_val = 0x8,
|
|
|
+ .mipi_pack_supported = 1,
|
|
|
+ .offline_mode_supported = 1,
|
|
|
+ .packing_fmt_shift_val = 15,
|
|
|
+ .plain_alignment_shift_val = 11,
|
|
|
+ .plain_fmt_shift_val = 12,
|
|
|
+ .crop_v_en_shift_val = 8,
|
|
|
+ .crop_h_en_shift_val = 7,
|
|
|
+ .drop_v_en_shift_val = 6,
|
|
|
+ .drop_h_en_shift_val = 5,
|
|
|
+ .early_eof_en_shift_val = 14,
|
|
|
+ .format_measure_en_shift_val = 3,
|
|
|
+ .timestamp_en_shift_val = 6,
|
|
|
+ .debug_byte_cntr_rst_shift_val = 2,
|
|
|
+ .offline_mode_en_shift_val = 2,
|
|
|
+ .ccif_violation_en = 1,
|
|
|
+ .fatal_err_mask = 0x186005,
|
|
|
+ .non_fatal_err_mask = 0x10000000,
|
|
|
+ .sof_irq_mask = 0x10,
|
|
|
+ .rup_irq_mask = 0x800000,
|
|
|
+ .epoch0_irq_mask = 0x200000,
|
|
|
+ .epoch1_irq_mask = 0x400000,
|
|
|
+ .eof_irq_mask = 0x8,
|
|
|
+ .rup_aup_mask = 0x200020,
|
|
|
+ .top_irq_mask = 0x200,
|
|
|
+ .epoch0_shift_val = 16,
|
|
|
+ .epoch1_shift_val = 0,
|
|
|
+ .pix_store_en_shift_val = 10,
|
|
|
+ .sof_retiming_dis_shift = 5,
|
|
|
+};
|
|
|
+
|
|
|
+static struct cam_ife_csid_ver2_path_reg_info
|
|
|
+ cam_ife_csid_880_rdi_2_reg_info = {
|
|
|
+ .irq_status_addr = 0x110C,
|
|
|
+ .irq_mask_addr = 0x1110,
|
|
|
+ .irq_clear_addr = 0x1114,
|
|
|
+ .irq_set_addr = 0x1118,
|
|
|
+ .cfg0_addr = 0x1700,
|
|
|
+ .ctrl_addr = 0x1704,
|
|
|
+ .debug_clr_cmd_addr = 0x1708,
|
|
|
+ .multi_vcdt_cfg0_addr = 0x170C,
|
|
|
+ .cfg1_addr = 0x1710,
|
|
|
+ .err_recovery_cfg0_addr = 0x1714,
|
|
|
+ .err_recovery_cfg1_addr = 0x1718,
|
|
|
+ .err_recovery_cfg2_addr = 0x171C,
|
|
|
+ .debug_byte_cntr_ping_addr = 0x1720,
|
|
|
+ .debug_byte_cntr_pong_addr = 0x1724,
|
|
|
+ .camif_frame_cfg_addr = 0x1728,
|
|
|
+ .epoch_irq_cfg_addr = 0x172C,
|
|
|
+ .epoch0_subsample_ptrn_addr = 0x1730,
|
|
|
+ .epoch1_subsample_ptrn_addr = 0x1734,
|
|
|
+ .debug_camif_1_addr = 0x1738,
|
|
|
+ .debug_camif_0_addr = 0x173C,
|
|
|
+ .frm_drop_pattern_addr = 0x1740,
|
|
|
+ .frm_drop_period_addr = 0x1744,
|
|
|
+ .irq_subsample_pattern_addr = 0x1748,
|
|
|
+ .irq_subsample_period_addr = 0x174C,
|
|
|
+ .hcrop_addr = 0x1750,
|
|
|
+ .vcrop_addr = 0x1754,
|
|
|
+ .pix_drop_pattern_addr = 0x1758,
|
|
|
+ .pix_drop_period_addr = 0x175C,
|
|
|
+ .line_drop_pattern_addr = 0x1760,
|
|
|
+ .line_drop_period_addr = 0x1764,
|
|
|
+ .debug_halt_status_addr = 0x176C,
|
|
|
+ .debug_misr_val0_addr = 0x1770,
|
|
|
+ .debug_misr_val1_addr = 0x1774,
|
|
|
+ .debug_misr_val2_addr = 0x1778,
|
|
|
+ .debug_misr_val3_addr = 0x177C,
|
|
|
+ .format_measure_cfg0_addr = 0x1880,
|
|
|
+ .format_measure_cfg1_addr = 0x1784,
|
|
|
+ .format_measure0_addr = 0x1788,
|
|
|
+ .format_measure1_addr = 0x178C,
|
|
|
+ .format_measure2_addr = 0x1790,
|
|
|
+ .timestamp_curr0_sof_addr = 0x1794,
|
|
|
+ .timestamp_curr1_sof_addr = 0x1798,
|
|
|
+ .timestamp_perv0_sof_addr = 0x179C,
|
|
|
+ .timestamp_perv1_sof_addr = 0x17A0,
|
|
|
+ .timestamp_curr0_eof_addr = 0x17A4,
|
|
|
+ .timestamp_curr1_eof_addr = 0x17A8,
|
|
|
+ .timestamp_perv0_eof_addr = 0x17AC,
|
|
|
+ .timestamp_perv1_eof_addr = 0x17B0,
|
|
|
+ .batch_id_cfg0_addr = 0x17B4,
|
|
|
+ .batch_id_cfg1_addr = 0x17B8,
|
|
|
+ .batch_period_cfg_addr = 0x17BC,
|
|
|
+ .batch_stream_id_cfg_addr = 0x17C0,
|
|
|
+ .epoch0_cfg_batch_id0_addr = 0x17C4,
|
|
|
+ .epoch1_cfg_batch_id0_addr = 0x17C8,
|
|
|
+ .epoch0_cfg_batch_id1_addr = 0x17CC,
|
|
|
+ .epoch1_cfg_batch_id1_addr = 0x17D0,
|
|
|
+ .epoch0_cfg_batch_id2_addr = 0x17D4,
|
|
|
+ .epoch1_cfg_batch_id2_addr = 0x17D8,
|
|
|
+ .epoch0_cfg_batch_id3_addr = 0x17DC,
|
|
|
+ .epoch1_cfg_batch_id3_addr = 0x17E0,
|
|
|
+ .epoch0_cfg_batch_id4_addr = 0x17E4,
|
|
|
+ .epoch1_cfg_batch_id4_addr = 0x17E8,
|
|
|
+ .epoch0_cfg_batch_id5_addr = 0x17EC,
|
|
|
+ .epoch1_cfg_batch_id5_addr = 0x17F0,
|
|
|
+ .secure_mask_cfg0 = 0x20,
|
|
|
+ .path_batch_status = 0x17F4,
|
|
|
+ .path_frame_id = 0x17F8,
|
|
|
+
|
|
|
+ /* configurations */
|
|
|
+ .resume_frame_boundary = 1,
|
|
|
+ .overflow_ctrl_en = 1,
|
|
|
+ .capabilities = CAM_IFE_CSID_CAP_INPUT_LCR |
|
|
|
+ CAM_IFE_CSID_CAP_RDI_UNPACK_MSB |
|
|
|
+ CAM_IFE_CSID_CAP_LINE_SMOOTHING_IN_RDI |
|
|
|
+ CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
|
|
|
+ .overflow_ctrl_mode_val = 0x8,
|
|
|
+ .mipi_pack_supported = 1,
|
|
|
+ .offline_mode_supported = 1,
|
|
|
+ .packing_fmt_shift_val = 15,
|
|
|
+ .plain_alignment_shift_val = 11,
|
|
|
+ .plain_fmt_shift_val = 12,
|
|
|
+ .crop_v_en_shift_val = 8,
|
|
|
+ .crop_h_en_shift_val = 7,
|
|
|
+ .drop_v_en_shift_val = 6,
|
|
|
+ .drop_h_en_shift_val = 5,
|
|
|
+ .early_eof_en_shift_val = 14,
|
|
|
+ .format_measure_en_shift_val = 3,
|
|
|
+ .timestamp_en_shift_val = 6,
|
|
|
+ .debug_byte_cntr_rst_shift_val = 2,
|
|
|
+ .offline_mode_en_shift_val = 2,
|
|
|
+ .ccif_violation_en = 1,
|
|
|
+ .fatal_err_mask = 0x186005,
|
|
|
+ .non_fatal_err_mask = 0x10000000,
|
|
|
+ .sof_irq_mask = 0x10,
|
|
|
+ .rup_irq_mask = 0x800000,
|
|
|
+ .epoch0_irq_mask = 0x200000,
|
|
|
+ .epoch1_irq_mask = 0x400000,
|
|
|
+ .eof_irq_mask = 0x8,
|
|
|
+ .rup_aup_mask = 0x400040,
|
|
|
+ .top_irq_mask = 0x400,
|
|
|
+ .epoch0_shift_val = 16,
|
|
|
+ .epoch1_shift_val = 0,
|
|
|
+ .pix_store_en_shift_val = 10,
|
|
|
+ .sof_retiming_dis_shift = 5,
|
|
|
+};
|
|
|
+
|
|
|
+static struct cam_ife_csid_ver2_path_reg_info
|
|
|
+ cam_ife_csid_880_rdi_3_reg_info = {
|
|
|
+ .irq_status_addr = 0x111C,
|
|
|
+ .irq_mask_addr = 0x1120,
|
|
|
+ .irq_clear_addr = 0x1124,
|
|
|
+ .irq_set_addr = 0x1128,
|
|
|
+ .cfg0_addr = 0x1800,
|
|
|
+ .ctrl_addr = 0x1804,
|
|
|
+ .debug_clr_cmd_addr = 0x1808,
|
|
|
+ .multi_vcdt_cfg0_addr = 0x180C,
|
|
|
+ .cfg1_addr = 0x1810,
|
|
|
+ .err_recovery_cfg0_addr = 0x1814,
|
|
|
+ .err_recovery_cfg1_addr = 0x1818,
|
|
|
+ .err_recovery_cfg2_addr = 0x181C,
|
|
|
+ .debug_byte_cntr_ping_addr = 0x1820,
|
|
|
+ .debug_byte_cntr_pong_addr = 0x1824,
|
|
|
+ .camif_frame_cfg_addr = 0x1828,
|
|
|
+ .epoch_irq_cfg_addr = 0x182C,
|
|
|
+ .epoch0_subsample_ptrn_addr = 0x1830,
|
|
|
+ .epoch1_subsample_ptrn_addr = 0x1834,
|
|
|
+ .debug_camif_1_addr = 0x1838,
|
|
|
+ .debug_camif_0_addr = 0x183C,
|
|
|
+ .frm_drop_pattern_addr = 0x1840,
|
|
|
+ .frm_drop_period_addr = 0x1840,
|
|
|
+ .irq_subsample_pattern_addr = 0x1848,
|
|
|
+ .irq_subsample_period_addr = 0x184C,
|
|
|
+ .hcrop_addr = 0x1850,
|
|
|
+ .vcrop_addr = 0x1854,
|
|
|
+ .pix_drop_pattern_addr = 0x1858,
|
|
|
+ .pix_drop_period_addr = 0x185C,
|
|
|
+ .line_drop_pattern_addr = 0x1860,
|
|
|
+ .line_drop_period_addr = 0x1864,
|
|
|
+ .debug_halt_status_addr = 0x1868,
|
|
|
+ .debug_misr_val0_addr = 0x1870,
|
|
|
+ .debug_misr_val1_addr = 0x1874,
|
|
|
+ .debug_misr_val2_addr = 0x1878,
|
|
|
+ .debug_misr_val3_addr = 0x187C,
|
|
|
+ .format_measure_cfg0_addr = 0x1880,
|
|
|
+ .format_measure_cfg1_addr = 0x1884,
|
|
|
+ .format_measure0_addr = 0x1888,
|
|
|
+ .format_measure1_addr = 0x188C,
|
|
|
+ .format_measure2_addr = 0x1890,
|
|
|
+ .timestamp_curr0_sof_addr = 0x1894,
|
|
|
+ .timestamp_curr1_sof_addr = 0x1898,
|
|
|
+ .timestamp_perv0_sof_addr = 0x189C,
|
|
|
+ .timestamp_perv1_sof_addr = 0x18A0,
|
|
|
+ .timestamp_curr0_eof_addr = 0x18A4,
|
|
|
+ .timestamp_curr1_eof_addr = 0x18A8,
|
|
|
+ .timestamp_perv0_eof_addr = 0x18AC,
|
|
|
+ .timestamp_perv1_eof_addr = 0x18B0,
|
|
|
+ .batch_id_cfg0_addr = 0x18B4,
|
|
|
+ .batch_id_cfg1_addr = 0x18B8,
|
|
|
+ .batch_period_cfg_addr = 0x18BC,
|
|
|
+ .batch_stream_id_cfg_addr = 0x18C0,
|
|
|
+ .epoch0_cfg_batch_id0_addr = 0x18C4,
|
|
|
+ .epoch1_cfg_batch_id0_addr = 0x18C8,
|
|
|
+ .epoch0_cfg_batch_id1_addr = 0x18CC,
|
|
|
+ .epoch1_cfg_batch_id1_addr = 0x18D0,
|
|
|
+ .epoch0_cfg_batch_id2_addr = 0x18D4,
|
|
|
+ .epoch1_cfg_batch_id2_addr = 0x18D8,
|
|
|
+ .epoch0_cfg_batch_id3_addr = 0x18DC,
|
|
|
+ .epoch1_cfg_batch_id3_addr = 0x18E0,
|
|
|
+ .epoch0_cfg_batch_id4_addr = 0x18E4,
|
|
|
+ .epoch1_cfg_batch_id4_addr = 0x18E8,
|
|
|
+ .epoch0_cfg_batch_id5_addr = 0x18EC,
|
|
|
+ .epoch1_cfg_batch_id5_addr = 0x18F0,
|
|
|
+ .secure_mask_cfg0 = 0x24,
|
|
|
+ .path_batch_status = 0x18F4,
|
|
|
+ .path_frame_id = 0x18F8,
|
|
|
+
|
|
|
+ /* configurations */
|
|
|
+ .capabilities = CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
|
|
|
+ .resume_frame_boundary = 1,
|
|
|
+ .overflow_ctrl_en = 1,
|
|
|
+ .capabilities = 0,
|
|
|
+ .overflow_ctrl_mode_val = 0x8,
|
|
|
+ .offline_mode_supported = 1,
|
|
|
+ .mipi_pack_supported = 1,
|
|
|
+ .packing_fmt_shift_val = 15,
|
|
|
+ .plain_alignment_shift_val = 11,
|
|
|
+ .plain_fmt_shift_val = 12,
|
|
|
+ .crop_v_en_shift_val = 8,
|
|
|
+ .crop_h_en_shift_val = 7,
|
|
|
+ .drop_v_en_shift_val = 6,
|
|
|
+ .drop_h_en_shift_val = 5,
|
|
|
+ .early_eof_en_shift_val = 14,
|
|
|
+ .format_measure_en_shift_val = 3,
|
|
|
+ .timestamp_en_shift_val = 6,
|
|
|
+ .debug_byte_cntr_rst_shift_val = 2,
|
|
|
+ .offline_mode_en_shift_val = 2,
|
|
|
+ .ccif_violation_en = 1,
|
|
|
+ .fatal_err_mask = 0x186005,
|
|
|
+ .non_fatal_err_mask = 0x10000000,
|
|
|
+ .sof_irq_mask = 0x10,
|
|
|
+ .rup_irq_mask = 0x800000,
|
|
|
+ .epoch0_irq_mask = 0x200000,
|
|
|
+ .epoch1_irq_mask = 0x400000,
|
|
|
+ .eof_irq_mask = 0x8,
|
|
|
+ .rup_aup_mask = 0x800080,
|
|
|
+ .top_irq_mask = 0x800,
|
|
|
+ .epoch0_shift_val = 16,
|
|
|
+ .epoch1_shift_val = 0,
|
|
|
+ .sof_retiming_dis_shift = 5,
|
|
|
+};
|
|
|
+
|
|
|
+static struct cam_ife_csid_ver2_path_reg_info
|
|
|
+ cam_ife_csid_880_rdi_4_reg_info = {
|
|
|
+ .irq_status_addr = 0x112C,
|
|
|
+ .irq_mask_addr = 0x1130,
|
|
|
+ .irq_clear_addr = 0x1134,
|
|
|
+ .irq_set_addr = 0x1138,
|
|
|
+ .cfg0_addr = 0x1900,
|
|
|
+ .ctrl_addr = 0x1904,
|
|
|
+ .debug_clr_cmd_addr = 0x1908,
|
|
|
+ .multi_vcdt_cfg0_addr = 0x190C,
|
|
|
+ .cfg1_addr = 0x1910,
|
|
|
+ .err_recovery_cfg0_addr = 0x1914,
|
|
|
+ .err_recovery_cfg1_addr = 0x1918,
|
|
|
+ .err_recovery_cfg2_addr = 0x191C,
|
|
|
+ .debug_byte_cntr_ping_addr = 0x1920,
|
|
|
+ .debug_byte_cntr_pong_addr = 0x1924,
|
|
|
+ .camif_frame_cfg_addr = 0x1928,
|
|
|
+ .epoch_irq_cfg_addr = 0x192C,
|
|
|
+ .epoch0_subsample_ptrn_addr = 0x1930,
|
|
|
+ .epoch1_subsample_ptrn_addr = 0x1934,
|
|
|
+ .debug_camif_1_addr = 0x1938,
|
|
|
+ .debug_camif_0_addr = 0x193C,
|
|
|
+ .frm_drop_pattern_addr = 0x1940,
|
|
|
+ .frm_drop_period_addr = 0x1944,
|
|
|
+ .irq_subsample_pattern_addr = 0x1948,
|
|
|
+ .irq_subsample_period_addr = 0x194C,
|
|
|
+ .hcrop_addr = 0x1950,
|
|
|
+ .vcrop_addr = 0x1954,
|
|
|
+ .pix_drop_pattern_addr = 0x1958,
|
|
|
+ .pix_drop_period_addr = 0x195C,
|
|
|
+ .line_drop_pattern_addr = 0x1960,
|
|
|
+ .line_drop_period_addr = 0x1964,
|
|
|
+ .debug_halt_status_addr = 0x1968,
|
|
|
+ .debug_misr_val0_addr = 0x1970,
|
|
|
+ .debug_misr_val1_addr = 0x1974,
|
|
|
+ .debug_misr_val2_addr = 0x1978,
|
|
|
+ .debug_misr_val3_addr = 0x197C,
|
|
|
+ .format_measure_cfg0_addr = 0x1980,
|
|
|
+ .format_measure_cfg1_addr = 0x1984,
|
|
|
+ .format_measure0_addr = 0x1988,
|
|
|
+ .format_measure1_addr = 0x198C,
|
|
|
+ .format_measure2_addr = 0x1990,
|
|
|
+ .timestamp_curr0_sof_addr = 0x1994,
|
|
|
+ .timestamp_curr1_sof_addr = 0x1998,
|
|
|
+ .timestamp_perv0_sof_addr = 0x199C,
|
|
|
+ .timestamp_perv1_sof_addr = 0x19A0,
|
|
|
+ .timestamp_curr0_eof_addr = 0x19A4,
|
|
|
+ .timestamp_curr1_eof_addr = 0x19A8,
|
|
|
+ .timestamp_perv0_eof_addr = 0x19AC,
|
|
|
+ .timestamp_perv1_eof_addr = 0x19B0,
|
|
|
+ .batch_id_cfg0_addr = 0x19B4,
|
|
|
+ .batch_id_cfg1_addr = 0x19B8,
|
|
|
+ .batch_period_cfg_addr = 0x19BC,
|
|
|
+ .batch_stream_id_cfg_addr = 0x19C0,
|
|
|
+ .epoch0_cfg_batch_id0_addr = 0x19C4,
|
|
|
+ .epoch1_cfg_batch_id0_addr = 0x19C8,
|
|
|
+ .epoch0_cfg_batch_id1_addr = 0x19CC,
|
|
|
+ .epoch1_cfg_batch_id1_addr = 0x19D0,
|
|
|
+ .epoch0_cfg_batch_id2_addr = 0x19D4,
|
|
|
+ .epoch1_cfg_batch_id2_addr = 0x19D8,
|
|
|
+ .epoch0_cfg_batch_id3_addr = 0x19DC,
|
|
|
+ .epoch1_cfg_batch_id3_addr = 0x19E0,
|
|
|
+ .epoch0_cfg_batch_id4_addr = 0x19E4,
|
|
|
+ .epoch1_cfg_batch_id4_addr = 0x19E8,
|
|
|
+ .epoch0_cfg_batch_id5_addr = 0x19EC,
|
|
|
+ .epoch1_cfg_batch_id5_addr = 0x19F0,
|
|
|
+ .secure_mask_cfg0 = 0x28,
|
|
|
+ .path_batch_status = 0x19F4,
|
|
|
+ .path_frame_id = 0x19F8,
|
|
|
+
|
|
|
+ /* configurations */
|
|
|
+ .capabilities = CAM_IFE_CSID_CAP_SOF_RETIME_DIS,
|
|
|
+ .resume_frame_boundary = 1,
|
|
|
+ .overflow_ctrl_en = 1,
|
|
|
+ .capabilities = 0,
|
|
|
+ .overflow_ctrl_mode_val = 0x8,
|
|
|
+ .offline_mode_supported = 1,
|
|
|
+ .mipi_pack_supported = 1,
|
|
|
+ .packing_fmt_shift_val = 15,
|
|
|
+ .early_eof_en_shift_val = 14,
|
|
|
+ .plain_fmt_shift_val = 12,
|
|
|
+ .plain_alignment_shift_val = 11,
|
|
|
+ .crop_v_en_shift_val = 8,
|
|
|
+ .crop_h_en_shift_val = 7,
|
|
|
+ .drop_v_en_shift_val = 6,
|
|
|
+ .drop_h_en_shift_val = 5,
|
|
|
+ .timestamp_en_shift_val = 6,
|
|
|
+ .format_measure_en_shift_val = 3,
|
|
|
+ .debug_byte_cntr_rst_shift_val = 2,
|
|
|
+ .offline_mode_en_shift_val = 2,
|
|
|
+ .ccif_violation_en = 1,
|
|
|
+ .fatal_err_mask = 0x186005,
|
|
|
+ .non_fatal_err_mask = 0x10000000,
|
|
|
+ .sof_irq_mask = 0x10,
|
|
|
+ .rup_irq_mask = 0x800000,
|
|
|
+ .epoch0_irq_mask = 0x200000,
|
|
|
+ .epoch1_irq_mask = 0x400000,
|
|
|
+ .eof_irq_mask = 0x8,
|
|
|
+ .rup_aup_mask = 0x1000100,
|
|
|
+ .top_irq_mask = 0x1000,
|
|
|
+ .epoch0_shift_val = 16,
|
|
|
+ .epoch1_shift_val = 0,
|
|
|
+ .sof_retiming_dis_shift = 5,
|
|
|
+};
|
|
|
+
|
|
|
+static struct cam_ife_csid_csi2_rx_reg_info
|
|
|
+ cam_ife_csid_880_csi2_reg_info = {
|
|
|
+ .irq_status_addr = 0x109C,
|
|
|
+ .irq_mask_addr = 0x10A0,
|
|
|
+ .irq_clear_addr = 0x10A4,
|
|
|
+ .irq_set_addr = 0x10A8,
|
|
|
+ /*CSI2 rx control */
|
|
|
+ .cfg0_addr = 0x1200,
|
|
|
+ .cfg1_addr = 0x1204,
|
|
|
+ .capture_ctrl_addr = 0x1208,
|
|
|
+ .rst_strobes_addr = 0x120C,
|
|
|
+ .cap_unmap_long_pkt_hdr_0_addr = 0x1210,
|
|
|
+ .cap_unmap_long_pkt_hdr_1_addr = 0x1214,
|
|
|
+ .captured_short_pkt_0_addr = 0x1218,
|
|
|
+ .captured_short_pkt_1_addr = 0x121c,
|
|
|
+ .captured_long_pkt_0_addr = 0x1220,
|
|
|
+ .captured_long_pkt_1_addr = 0x1224,
|
|
|
+ .captured_long_pkt_ftr_addr = 0x1228,
|
|
|
+ .captured_cphy_pkt_hdr_addr = 0x122c,
|
|
|
+ .lane0_misr_addr = 0x1230,
|
|
|
+ .lane1_misr_addr = 0x1234,
|
|
|
+ .lane2_misr_addr = 0x1238,
|
|
|
+ .lane3_misr_addr = 0x123c,
|
|
|
+ .total_pkts_rcvd_addr = 0x1240,
|
|
|
+ .stats_ecc_addr = 0x1244,
|
|
|
+ .total_crc_err_addr = 0x1248,
|
|
|
+ .de_scramble_type3_cfg0_addr = 0x124C,
|
|
|
+ .de_scramble_type3_cfg1_addr = 0x1250,
|
|
|
+ .de_scramble_type2_cfg0_addr = 0x1254,
|
|
|
+ .de_scramble_type2_cfg1_addr = 0x1258,
|
|
|
+ .de_scramble_type1_cfg0_addr = 0x125C,
|
|
|
+ .de_scramble_type1_cfg1_addr = 0x1260,
|
|
|
+ .de_scramble_type0_cfg0_addr = 0x1264,
|
|
|
+ .de_scramble_type0_cfg1_addr = 0x1268,
|
|
|
+ .secure_cfg0 = 0x8,
|
|
|
+ .secure_mask_cfg0 = 0xC,
|
|
|
+
|
|
|
+ .rst_done_shift_val = 27,
|
|
|
+ .irq_mask_all = 0xFFFFFFF,
|
|
|
+ .misr_enable_shift_val = 6,
|
|
|
+ .vc_mode_shift_val = 2,
|
|
|
+ .capture_long_pkt_en_shift = 0,
|
|
|
+ .capture_short_pkt_en_shift = 1,
|
|
|
+ .capture_cphy_pkt_en_shift = 2,
|
|
|
+ .capture_long_pkt_dt_shift = 4,
|
|
|
+ .capture_long_pkt_vc_shift = 10,
|
|
|
+ .capture_short_pkt_vc_shift = 15,
|
|
|
+ .capture_cphy_pkt_dt_shift = 20,
|
|
|
+ .capture_cphy_pkt_vc_shift = 26,
|
|
|
+ .phy_num_mask = 0xf,
|
|
|
+ .vc_mask = 0x7C00000,
|
|
|
+ .dt_mask = 0x3f0000,
|
|
|
+ .wc_mask = 0xffff,
|
|
|
+ .vc_shift = 0x16,
|
|
|
+ .dt_shift = 0x10,
|
|
|
+ .wc_shift = 0,
|
|
|
+ .calc_crc_mask = 0xffff,
|
|
|
+ .expected_crc_mask = 0xffff,
|
|
|
+ .calc_crc_shift = 0x10,
|
|
|
+ .ecc_correction_shift_en = 0,
|
|
|
+ .lane_num_shift = 0,
|
|
|
+ .lane_cfg_shift = 4,
|
|
|
+ .phy_type_shift = 24,
|
|
|
+ .phy_num_shift = 20,
|
|
|
+ .tpg_mux_en_shift = 27,
|
|
|
+ .tpg_num_sel_shift = 28,
|
|
|
+ .phy_bist_shift_en = 7,
|
|
|
+ .epd_mode_shift_en = 8,
|
|
|
+ .eotp_shift_en = 9,
|
|
|
+ .dyn_sensor_switch_shift_en = 10,
|
|
|
+ .long_pkt_strobe_rst_shift = 0,
|
|
|
+ .short_pkt_strobe_rst_shift = 1,
|
|
|
+ .cphy_pkt_strobe_rst_shift = 2,
|
|
|
+ .unmapped_pkt_strobe_rst_shift = 3,
|
|
|
+ .fatal_err_mask = 0x19FA800,
|
|
|
+ .part_fatal_err_mask = 0x0001000,
|
|
|
+ .non_fatal_err_mask = 0x0200000,
|
|
|
+ .top_irq_mask = 0x4,
|
|
|
+};
|
|
|
+
|
|
|
+static struct cam_ife_csid_ver2_common_reg_info
|
|
|
+ cam_ife_csid_880_cmn_reg_info = {
|
|
|
+ .hw_version_addr = 0x1000,
|
|
|
+ .cfg0_addr = 0x1004,
|
|
|
+ .global_cmd_addr = 0x1008,
|
|
|
+ .reset_cfg_addr = 0x100c,
|
|
|
+ .reset_cmd_addr = 0x1010,
|
|
|
+ .irq_cmd_addr = 0x1014,
|
|
|
+ .rup_aup_cmd_addr = 0x1018,
|
|
|
+ .offline_cmd_addr = 0x101C,
|
|
|
+ .shdr_master_slave_cfg_addr = 0x1020,
|
|
|
+ .top_irq_status_addr = 0x107C,
|
|
|
+ .top_irq_mask_addr = 0x1080,
|
|
|
+ .top_irq_clear_addr = 0x1084,
|
|
|
+ .top_irq_set_addr = 0x1088,
|
|
|
+ .buf_done_irq_status_addr = 0x108C,
|
|
|
+ .buf_done_irq_mask_addr = 0x1090,
|
|
|
+ .buf_done_irq_clear_addr = 0x1094,
|
|
|
+ .buf_done_irq_set_addr = 0x1098,
|
|
|
+ .test_bus_ctrl = 0x11E8,
|
|
|
+ .test_bus_debug = 0x11EC,
|
|
|
+ .path_domain_id_cfg0 = 0x0,
|
|
|
+ .path_domain_id_cfg1 = 0x4,
|
|
|
+
|
|
|
+ /*configurations */
|
|
|
+ .major_version = 6,
|
|
|
+ .minor_version = 8,
|
|
|
+ .version_incr = 0,
|
|
|
+ .num_rdis = 5,
|
|
|
+ .num_pix = 1,
|
|
|
+ .num_ppp = 1,
|
|
|
+ .rst_done_shift_val = 1,
|
|
|
+ .path_en_shift_val = 31,
|
|
|
+ .dt_id_shift_val = 27,
|
|
|
+ .vc_shift_val = 22,
|
|
|
+ .vc_mask = 0x1F,
|
|
|
+ .dt_shift_val = 16,
|
|
|
+ .dt_mask = 0x3F,
|
|
|
+ .crop_shift_val = 16,
|
|
|
+ .decode_format_shift_val = 12,
|
|
|
+ .decode_format1_shift_val = 16,
|
|
|
+ .decode_format1_supported = true,
|
|
|
+ .decode_format_mask = 0xF,
|
|
|
+ .frame_id_decode_en_shift_val = 1,
|
|
|
+ .multi_vcdt_vc1_shift_val = 2,
|
|
|
+ .multi_vcdt_dt1_shift_val = 7,
|
|
|
+ .multi_vcdt_en_shift_val = 0,
|
|
|
+ .timestamp_stb_sel_shift_val = 8,
|
|
|
+ .vfr_en_shift_val = 0,
|
|
|
+ .mup_shift_val = 28,
|
|
|
+ .shdr_slave_ppp_shift = 20,
|
|
|
+ .shdr_slave_rdi2_shift = 22,
|
|
|
+ .shdr_slave_rdi1_shift = 21,
|
|
|
+ .shdr_master_rdi0_shift = 5,
|
|
|
+ .shdr_master_slave_en_shift = 0,
|
|
|
+ .early_eof_supported = 1,
|
|
|
+ .vfr_supported = 1,
|
|
|
+ .multi_vcdt_supported = 1,
|
|
|
+ .frame_id_dec_supported = 1,
|
|
|
+ .measure_en_hbi_vbi_cnt_mask = 0xc,
|
|
|
+ .measure_pixel_line_en_mask = 0x3,
|
|
|
+ .crop_pix_start_mask = 0x3fff,
|
|
|
+ .crop_pix_end_mask = 0xffff,
|
|
|
+ .crop_line_start_mask = 0x3fff,
|
|
|
+ .crop_line_end_mask = 0xffff,
|
|
|
+ .drop_supported = 1,
|
|
|
+ .ipp_irq_mask_all = 0x7FFF,
|
|
|
+ .rdi_irq_mask_all = 0x7FFF,
|
|
|
+ .ppp_irq_mask_all = 0xFFFF,
|
|
|
+ .top_err_irq_mask = 0x1C0002,
|
|
|
+ .rst_loc_path_only_val = 0x0,
|
|
|
+ .rst_loc_complete_csid_val = 0x1,
|
|
|
+ .rst_mode_frame_boundary_val = 0x0,
|
|
|
+ .rst_mode_immediate_val = 0x1,
|
|
|
+ .rst_cmd_hw_reset_complete_val = 0x1,
|
|
|
+ .rst_cmd_sw_reset_complete_val = 0x2,
|
|
|
+ .rst_cmd_irq_ctrl_only_val = 0x4,
|
|
|
+ .timestamp_strobe_val = 0x2,
|
|
|
+ .top_reset_irq_mask = 0x1,
|
|
|
+ .rst_location_shift_val = 4,
|
|
|
+ .rst_mode_shift_val = 0,
|
|
|
+ .epoch_factor = 50,
|
|
|
+ .global_reset = 1,
|
|
|
+ .rup_supported = 1,
|
|
|
+ .only_master_rup = 1,
|
|
|
+ .format_measure_height_mask_val = 0xFFFF,
|
|
|
+ .format_measure_height_shift_val = 0x10,
|
|
|
+ .format_measure_width_mask_val = 0xFFFF,
|
|
|
+ .format_measure_width_shift_val = 0x0,
|
|
|
+ .top_buf_done_irq_mask = 0x2000,
|
|
|
+ .decode_format_payload_only = 0xF,
|
|
|
+ .timestamp_enabled_in_cfg0 = true,
|
|
|
+ .sfe_ipp_input_rdi_res = BIT(CAM_IFE_PIX_PATH_RES_RDI_0),
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+ .camif_irq_support = true,
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+};
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+
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+static struct cam_ife_csid_ver2_top_reg_info
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+ cam_ife_csid_880_top_reg_info = {
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+ .io_path_cfg0_addr = {
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+ 0x0,
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+ 0x4,
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+ 0x8,
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+ },
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+ .dual_csid_cfg0_addr = {
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+ 0xC,
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+ 0x10,
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+ 0x14,
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+ },
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+ .input_core_type_shift_val = 0,
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+ .sfe_offline_en_shift_val = 12,
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+ .out_ife_en_shift_val = 8,
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+ .dual_sync_sel_shift_val = 8,
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+ .dual_en_shift_val = 0,
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+ .master_slave_sel_shift_val = 1,
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+ .rdi_lcr_shift_val = 16,
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+ .master_sel_val = 0,
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+ .slave_sel_val = 1,
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+ .io_path_cfg_rst_val = 1,
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+ .dual_cfg_rst_val = 0,
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+};
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+
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+static struct cam_ife_csid_ver2_reg_info cam_ife_csid_880_reg_info = {
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+ .top_irq_reg_info = &cam_ife_csid_880_top_irq_reg_info,
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+ .rx_irq_reg_info = &cam_ife_csid_880_rx_irq_reg_info,
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+ .path_irq_reg_info = {
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+ &cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_0],
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+ &cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_1],
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+ &cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_2],
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+ &cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_3],
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+ &cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_4],
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+ &cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_IPP],
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+ &cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_PPP],
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|
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+ },
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+ .buf_done_irq_reg_info = &cam_ife_csid_880_buf_done_irq_reg_info,
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+ .cmn_reg = &cam_ife_csid_880_cmn_reg_info,
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+ .csi2_reg = &cam_ife_csid_880_csi2_reg_info,
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+ .path_reg[CAM_IFE_PIX_PATH_RES_IPP] = &cam_ife_csid_880_ipp_reg_info,
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+ .path_reg[CAM_IFE_PIX_PATH_RES_PPP] = &cam_ife_csid_880_ppp_reg_info,
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+ .path_reg[CAM_IFE_PIX_PATH_RES_RDI_0] = &cam_ife_csid_880_rdi_0_reg_info,
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+ .path_reg[CAM_IFE_PIX_PATH_RES_RDI_1] = &cam_ife_csid_880_rdi_1_reg_info,
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+ .path_reg[CAM_IFE_PIX_PATH_RES_RDI_2] = &cam_ife_csid_880_rdi_2_reg_info,
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+ .path_reg[CAM_IFE_PIX_PATH_RES_RDI_3] = &cam_ife_csid_880_rdi_3_reg_info,
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+ .path_reg[CAM_IFE_PIX_PATH_RES_RDI_4] = &cam_ife_csid_880_rdi_4_reg_info,
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|
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+ .top_reg = &cam_ife_csid_880_top_reg_info,
|
|
|
+ .input_core_sel = {
|
|
|
+ {
|
|
|
+ 0x0,
|
|
|
+ 0x1,
|
|
|
+ 0x2,
|
|
|
+ 0x3,
|
|
|
+ 0x8,
|
|
|
+ -1,
|
|
|
+ -1,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ 0x0,
|
|
|
+ 0x1,
|
|
|
+ 0x2,
|
|
|
+ 0x3,
|
|
|
+ -1,
|
|
|
+ -1,
|
|
|
+ -1,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ 0x0,
|
|
|
+ 0x1,
|
|
|
+ 0x2,
|
|
|
+ 0x3,
|
|
|
+ -1,
|
|
|
+ 0x9,
|
|
|
+ -1,
|
|
|
+ },
|
|
|
+ },
|
|
|
+ .need_top_cfg = 0x1,
|
|
|
+ .csid_cust_node_map = {0x1, 0x0, 0x2},
|
|
|
+ .rx_irq_desc = cam_ife_csid_880_rx_irq_desc,
|
|
|
+ .path_irq_desc = cam_ife_csid_880_path_irq_desc,
|
|
|
+ .top_irq_desc = cam_ife_csid_880_top_irq_desc,
|
|
|
+ .num_top_err_irqs = ARRAY_SIZE(cam_ife_csid_880_top_irq_desc),
|
|
|
+};
|
|
|
+#endif /*_CAM_IFE_CSID_880_H_ */
|
Chandan Kumar Jha