qcacld-3.0: Add support for Kiwi flow search table in CMEM

For KIWI platform FST reside in CMEM. CMEM address is known at the
init time from platform driver. Use 16K of CMEM address for FST.
Increase MAX FISA FST entry size to 256, which is allowed max size with
16K of CMEM allocation for FISA FST.

Change-Id: I395ab884b9cc761ed3c4438434475d6f9908a62b
CRs-Fixed: 3199251

core/dp/txrx3.0/dp_fisa_rx.c

@@ -789,6 +789,7 @@ static void dp_fisa_rx_fst_update(struct dp_rx_fst *fisa_hdl,
 	struct cdp_rx_flow_tuple_info *rx_flow_tuple_info;
 	uint32_t skid_count = 0, max_skid_length;
 	struct dp_fisa_rx_sw_ft *sw_ft_entry;
+	struct wlan_cfg_dp_soc_ctxt *cfg_ctx = fisa_hdl->soc_hdl->wlan_cfg_ctx;
 	bool is_fst_updated = false;
 	uint32_t hashed_flow_idx;
 	uint32_t flow_hash;
@@ -865,7 +866,8 @@ static void dp_fisa_rx_fst_update(struct dp_rx_fst *fisa_hdl,
 	 * Remove LRU flow from HW FT
 	 * Remove LRU flow from SW FT
 	 */
-	if (skid_count > max_skid_length) {
+	if ((skid_count > max_skid_length) &&
+	    wlan_cfg_is_rx_fisa_lru_del_enabled(cfg_ctx)) {
 		dp_fisa_debug("Max skid length reached flow cannot be added, evict exiting flow");
 		dp_fisa_rx_delete_flow(fisa_hdl, elem, lru_ft_entry_idx);
 		is_fst_updated = true;

core/dp/txrx3.0/dp_rx_fst.c

@@ -299,6 +299,7 @@ QDF_STATUS dp_rx_fst_attach(struct dp_soc *soc, struct dp_pdev *pdev)
 	dp_err("FST setup params FT size %d, hash_mask 0x%x, skid_length %d",
 	       fst->max_entries, fst->hash_mask, fst->max_skid_length);
 
+	/* Allocate the software flowtable */
 	fst->base = (uint8_t *)dp_context_alloc_mem(soc, DP_FISA_RX_FT_TYPE,
 				DP_RX_GET_SW_FT_ENTRY_SIZE * fst->max_entries);
 
@@ -319,7 +320,8 @@ QDF_STATUS dp_rx_fst_attach(struct dp_soc *soc, struct dp_pdev *pdev)
 					    soc->osdev,
 					    &fst->hal_rx_fst_base_paddr,
 					    fst->max_entries,
-					    fst->max_skid_length, hash_key);
+					    fst->max_skid_length, hash_key,
+					    soc->fst_cmem_base);
 
 	if (qdf_unlikely(!fst->hal_rx_fst)) {
 		QDF_TRACE(QDF_MODULE_ID_ANY, QDF_TRACE_LEVEL_ERROR,
@@ -357,7 +359,8 @@ QDF_STATUS dp_rx_fst_attach(struct dp_soc *soc, struct dp_pdev *pdev)
 
 timer_init_fail:
 	qdf_spinlock_destroy(&fst->dp_rx_fst_lock);
-	hal_rx_fst_detach(soc->hal_soc, fst->hal_rx_fst, soc->osdev);
+	hal_rx_fst_detach(soc->hal_soc, fst->hal_rx_fst, soc->osdev,
+			  soc->fst_cmem_base);
 free_hist:
 	dp_rx_sw_ft_hist_deinit((struct dp_fisa_rx_sw_ft *)fst->base,
 				fst->max_entries);
@@ -379,15 +382,19 @@ static void dp_rx_fst_check_cmem_support(struct dp_soc *soc)
 	struct dp_rx_fst *fst = soc->rx_fst;
 	QDF_STATUS status;
 
-	/* FW doesn't support CMEM FSE, keep it in DDR */
-	if (!soc->fst_in_cmem)
+	/**
+	 * FW doesn't support CMEM FSE, keep it in DDR
+	 * soc->fst_cmem_base is non-NULL then CMEM support is already present
+	 */
+	if (!soc->fst_in_cmem && (soc->fst_cmem_base == 0))
 		return;
 
 	status = dp_rx_fst_cmem_init(fst);
 	if (status != QDF_STATUS_SUCCESS)
 		return;
 
-	hal_rx_fst_detach(soc->hal_soc, fst->hal_rx_fst, soc->osdev);
+	hal_rx_fst_detach(soc->hal_soc, fst->hal_rx_fst, soc->osdev,
+			  soc->fst_cmem_base);
 	fst->hal_rx_fst = NULL;
 	fst->hal_rx_fst_base_paddr = 0;
 	fst->flow_deletion_supported = true;
@@ -416,17 +423,33 @@ QDF_STATUS dp_rx_flow_send_fst_fw_setup(struct dp_soc *soc,
 	fisa_hw_fst_setup_cmd.pdev_id = 0;
 	fisa_hw_fst_setup_cmd.max_entries = fst->max_entries;
 	fisa_hw_fst_setup_cmd.max_search = fst->max_skid_length;
-	fisa_hw_fst_setup_cmd.base_addr_lo = fst->hal_rx_fst_base_paddr &
-							0xffffffff;
-	fisa_hw_fst_setup_cmd.base_addr_hi = (fst->hal_rx_fst_base_paddr >> 32);
+	if (soc->fst_cmem_base) {
+		fisa_hw_fst_setup_cmd.base_addr_lo =
+			soc->fst_cmem_base & 0xffffffff;
+		/* Higher order bits are mostly 0, Always use 0x10 */
+		fisa_hw_fst_setup_cmd.base_addr_hi =
+			(soc->fst_cmem_base >> 32) | 0x10;
+		dp_info("cmem base address 0x%llx\n", soc->fst_cmem_base);
+	} else {
+		fisa_hw_fst_setup_cmd.base_addr_lo =
+			fst->hal_rx_fst_base_paddr & 0xffffffff;
+		fisa_hw_fst_setup_cmd.base_addr_hi =
+			(fst->hal_rx_fst_base_paddr >> 32);
+	}
+
 	fisa_hw_fst_setup_cmd.ip_da_sa_prefix =	HTT_RX_IPV4_COMPATIBLE_IPV6;
 	fisa_hw_fst_setup_cmd.hash_key_len = HAL_FST_HASH_KEY_SIZE_BYTES;
 	fisa_hw_fst_setup_cmd.hash_key = wlan_cfg_rx_fst_get_hash_key(cfg);
 
-	status  = dp_htt_rx_flow_fst_setup(pdev, &fisa_hw_fst_setup_cmd);
+	status = dp_htt_rx_flow_fst_setup(pdev, &fisa_hw_fst_setup_cmd);
 
-	if (!fst->fst_in_cmem)
+	if (!fst->fst_in_cmem || soc->fst_cmem_base) {
+		/**
+		 * Return from here if fst_cmem is not enabled or cmem address
+		 * is known at init time
+		 */
 		return status;
+	}
 
 	status = qdf_wait_single_event(&fst->cmem_resp_event,
 				       DP_RX_FST_CMEM_RESP_TIMEOUT);
@@ -455,7 +478,7 @@ void dp_rx_fst_detach(struct dp_soc *soc, struct dp_pdev *pdev)
 			dp_rx_fst_cmem_deinit(dp_fst);
 		else
 			hal_rx_fst_detach(soc->hal_soc, dp_fst->hal_rx_fst,
-					  soc->osdev);
+					  soc->osdev, soc->fst_cmem_base);
 
 		dp_rx_sw_ft_hist_deinit((struct dp_fisa_rx_sw_ft *)dp_fst->base,
 					dp_fst->max_entries);
@@ -486,7 +509,9 @@ void dp_rx_fst_update_cmem_params(struct dp_soc *soc, uint16_t num_entries,
 	fst->hash_mask = fst->max_entries - 1;
 	fst->cmem_ba = cmem_ba_lo;
 
-	qdf_event_set(&fst->cmem_resp_event);
+	/* Address is not NULL then address is already known during init */
+	if (soc->fst_cmem_base == 0)
+		qdf_event_set(&fst->cmem_resp_event);
 }
 
 void dp_rx_fst_update_pm_suspend_status(struct dp_soc *soc, bool suspended)

core/dp/txrx3.0/dp_txrx.c

@@ -206,7 +206,7 @@ int dp_rx_tm_get_pending(ol_txrx_soc_handle soc)
 #ifdef DP_MEM_PRE_ALLOC
 
 /* Max entries in FISA Flow table */
-#define FISA_RX_FT_SIZE 128
+#define FISA_RX_FT_SIZE 256
 
 /* Num elements in REO ring */
 #define REO_DST_RING_SIZE 1024