video: driver: Add HFI changes for AV1 Decoder
Add the required codec properties and HFI definitions to enable AV1D. Change-Id: Ib098ed17f8b8e1fe9403f966a2dab97a3c9f96de Signed-off-by: Mihir Ganu <quic_mganu@quicinc.com>
这个提交包含在：
Mihir Ganu
@@ -876,6 +876,276 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
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#define HFI_BUFFER_PERSIST_MP2D(_size) \
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_size = QMATRIX_SIZE + MP2D_QPDUMP_SIZE;
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#define AV1D_LCU_MAX_SIZE_PELS 128
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#define AV1D_LCU_MIN_SIZE_PELS 64
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#define AV1D_MAX_TILE_COLS 64
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#define SIZE_AV1D_LB_FE_TOP_DATA(frame_width, frame_height) \
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(HFI_ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) * ((16 * 10) >> 3) + \
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HFI_ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) / 2 * ((16 * 6) >> 3) * 2)
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#define SIZE_AV1D_LB_FE_LEFT_DATA(frame_width, frame_height) \
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(32 * (HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + \
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HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / \
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AV1D_LCU_MIN_SIZE_PELS * 16) + \
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16 * (HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 + \
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HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / \
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AV1D_LCU_MIN_SIZE_PELS * 8) * 2 + \
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24 * (HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + \
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HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / \
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AV1D_LCU_MIN_SIZE_PELS * 16) + \
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24 * (HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 + \
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HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / \
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AV1D_LCU_MIN_SIZE_PELS * 12) * 2 + \
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24 * (HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + \
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HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / \
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AV1D_LCU_MIN_SIZE_PELS * 16) + \
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16 * (HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + \
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HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / \
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AV1D_LCU_MIN_SIZE_PELS * 16) + \
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16 * (HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 + \
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HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / \
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AV1D_LCU_MIN_SIZE_PELS * 12) * 2)
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#define SIZE_AV1D_LB_FE_TOP_CTRL(frame_width, frame_height) \
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(10 * ((frame_width + AV1D_LCU_MIN_SIZE_PELS - 1) / \
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AV1D_LCU_MIN_SIZE_PELS) * 128 / 8)
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#define SIZE_AV1D_LB_FE_LEFT_CTRL(frame_width, frame_height) \
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(16 * ((HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 16) + \
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(HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / \
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AV1D_LCU_MIN_SIZE_PELS)) + \
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3 * 16 * (HFI_ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / \
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AV1D_LCU_MIN_SIZE_PELS))
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#define SIZE_AV1D_LB_SE_TOP_CTRL(frame_width, frame_height) \
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(((frame_width + 7) / 8) * 16)
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#define SIZE_AV1D_LB_SE_LEFT_CTRL(frame_width, frame_height) \
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(MAX(((frame_height + 15) / 16) * MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, \
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MAX(((frame_height + 31) / 32) * MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, \
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((frame_height + 63) / 64) * MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)))
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#define SIZE_AV1D_LB_PE_TOP_DATA(frame_width, frame_height) \
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(MAX(((frame_width + 15) / 16) * MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE, \
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MAX(((frame_width + 31) / 32) * MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE, \
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((frame_width + 63) / 64) * MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE)))
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#define SIZE_AV1D_LB_VSP_TOP(frame_width, frame_height) \
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(MAX(((frame_width + 63) / 64) * 1280, ((frame_width + 127) / 128) * 2304))
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#define SIZE_AV1D_LB_RECON_DMA_METADATA_WR(frame_width, frame_height) \
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((HFI_ALIGN(frame_height, 8) / (4 / 2)) * 64)
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#define SIZE_AV1D_QP(frame_width, frame_height) \
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SIZE_H264D_QP(frame_width, frame_height)
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#define SIZE_AV1D_LB_OPB_WR1_NV12_UBWC(_size, frame_width, frame_height) \
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do \
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{ \
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HFI_U32 y_width, y_width_a = 128; \
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HFI_NV12_IL_CALC_Y_STRIDE(y_width, frame_width, y_width_a); \
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_size = (256 * ((y_width + 31) / 32 + (AV1D_MAX_TILE_COLS - 1))); \
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} while (0)
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#define SIZE_AV1D_LB_OPB_WR1_TP10_UBWC(_size, frame_width, frame_height) \
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do \
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{ \
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HFI_U32 y_width, y_width_a = 256; \
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HFI_YUV420_TP10_CALC_Y_STRIDE(y_width, frame_width, y_width_a); \
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_size = (256 * ((y_width + 47) / 48 + (AV1D_MAX_TILE_COLS - 1))); \
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} while (0)
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#define SIZE_AV1D_IBC_NV12_UBWC(_size, frame_width, frame_height) \
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do \
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{ \
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HFI_U32 y_width_a = 128, y_height_a = 32; \
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HFI_U32 uv_width_a = 128, uv_height_a = 32; \
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HFI_U32 yBufSize, uvBufSize, y_width, y_height, uv_width, uv_height; \
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HFI_NV12_IL_CALC_Y_STRIDE(y_width, frame_width, y_width_a); \
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HFI_NV12_IL_CALC_Y_BUFHEIGHT(y_height, frame_height, y_height_a); \
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HFI_NV12_IL_CALC_UV_STRIDE(uv_width, frame_width, uv_width_a); \
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HFI_NV12_IL_CALC_UV_BUFHEIGHT(uv_height, frame_height, uv_height_a); \
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HFI_NV12_UBWC_IL_CALC_Y_BUF_SIZE(yBufSize, y_width, y_height); \
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HFI_NV12_UBWC_IL_CALC_UV_BUF_SIZE(uvBufSize, uv_width, uv_height); \
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_size = yBufSize + uvBufSize; \
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HFI_U32 y_meta_width_a = 64, y_meta_height_a = 16; \
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HFI_U32 uv_meta_width_a = 64, uv_meta_height_a = 16; \
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HFI_U32 meta_height, meta_stride, meta_size; \
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HFI_U32 tile_width_y = HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_WIDTH; \
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HFI_U32 tile_height_y = HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_HEIGHT; \
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HFI_U32 tile_width_uv = HFI_COLOR_FORMAT_YUV420_NV12_UBWC_UV_TILE_WIDTH; \
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HFI_U32 tile_height_uv = \
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HFI_COLOR_FORMAT_YUV420_NV12_UBWC_UV_TILE_HEIGHT; \
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HFI_UBWC_CALC_METADATA_PLANE_STRIDE(meta_stride, frame_width, \
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y_meta_width_a, tile_width_y); \
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HFI_UBWC_METADATA_PLANE_BUFHEIGHT(meta_height, frame_height, \
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y_meta_height_a, tile_height_y); \
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HFI_UBWC_METADATA_PLANE_BUFFER_SIZE(meta_size, \
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meta_stride, meta_height); \
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_size += meta_size; \
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HFI_UBWC_UV_METADATA_PLANE_STRIDE(meta_stride, frame_width, \
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uv_meta_width_a, tile_width_uv); \
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HFI_UBWC_UV_METADATA_PLANE_BUFHEIGHT(meta_height, frame_height, \
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uv_meta_height_a, tile_height_uv); \
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HFI_UBWC_METADATA_PLANE_BUFFER_SIZE(meta_size, \
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meta_stride, meta_height); \
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_size += meta_size; \
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} while (0)
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#define SIZE_AV1D_IBC_TP10_UBWC(_size, frame_width, frame_height) \
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do \
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{ \
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HFI_U32 y_width_a = 256, y_height_a = 16, \
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uv_width_a = 256, uv_height_a = 16; \
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HFI_U32 yBufSize, uvBufSize, y_width, y_height, uv_width, uv_height; \
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HFI_YUV420_TP10_CALC_Y_STRIDE(y_width, frame_width, y_width_a); \
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HFI_YUV420_TP10_CALC_Y_BUFHEIGHT(y_height, frame_height, y_height_a); \
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HFI_YUV420_TP10_CALC_UV_STRIDE(uv_width, frame_width, uv_width_a); \
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HFI_YUV420_TP10_CALC_UV_BUFHEIGHT(uv_height, frame_height, \
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uv_height_a); \
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HFI_YUV420_TP10_UBWC_CALC_Y_BUF_SIZE(yBufSize, y_width, y_height); \
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HFI_YUV420_TP10_UBWC_CALC_UV_BUF_SIZE(uvBufSize, uv_width, uv_height); \
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_size = yBufSize + uvBufSize; \
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HFI_U32 y_meta_width_a = 64, y_meta_height_a = 16, \
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uv_meta_width_a = 64, uv_meta_height_a = 16; \
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HFI_U32 meta_height, meta_stride, meta_size; \
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HFI_U32 tile_width_y = HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_WIDTH; \
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HFI_U32 tile_height_y = HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_HEIGHT; \
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HFI_U32 tile_width_uv = HFI_COLOR_FORMAT_YUV420_TP10_UBWC_UV_TILE_WIDTH; \
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HFI_U32 tile_height_uv = \
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HFI_COLOR_FORMAT_YUV420_TP10_UBWC_UV_TILE_HEIGHT; \
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HFI_UBWC_CALC_METADATA_PLANE_STRIDE(meta_stride, frame_width, \
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y_meta_width_a, tile_width_y); \
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HFI_UBWC_METADATA_PLANE_BUFHEIGHT(meta_height, frame_height, \
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y_meta_height_a, tile_height_y); \
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HFI_UBWC_METADATA_PLANE_BUFFER_SIZE(meta_size, \
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meta_stride, meta_height); \
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_size += meta_size; \
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HFI_UBWC_UV_METADATA_PLANE_STRIDE(meta_stride, frame_width, \
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uv_meta_width_a, tile_width_uv); \
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HFI_UBWC_UV_METADATA_PLANE_BUFHEIGHT(meta_height, frame_height, \
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uv_meta_height_a, tile_height_uv); \
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HFI_UBWC_METADATA_PLANE_BUFFER_SIZE(meta_size, \
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meta_stride, meta_height); \
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_size += meta_size; \
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} while (0)
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#define HFI_BUFFER_LINE_AV1D(_size, frame_width, frame_height, isOPB, \
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num_vpp_pipes) \
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do \
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{ \
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HFI_U32 vpssLBSize, ibcBufSize, opbwr1BufSize, \
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opbwr8, opbwr10, ibc8, ibc10; \
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_size = HFI_ALIGN(SIZE_AV1D_LB_FE_TOP_DATA(frame_width, frame_height), \
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VENUS_DMA_ALIGNMENT) + \
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HFI_ALIGN(SIZE_AV1D_LB_FE_TOP_CTRL(frame_width, frame_height), \
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VENUS_DMA_ALIGNMENT) + \
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HFI_ALIGN(SIZE_AV1D_LB_FE_LEFT_DATA(frame_width, frame_height), \
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VENUS_DMA_ALIGNMENT) * num_vpp_pipes + \
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HFI_ALIGN(SIZE_AV1D_LB_FE_LEFT_CTRL(frame_width, frame_height), \
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VENUS_DMA_ALIGNMENT) * num_vpp_pipes + \
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HFI_ALIGN(SIZE_AV1D_LB_SE_LEFT_CTRL(frame_width, frame_height), \
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VENUS_DMA_ALIGNMENT) * num_vpp_pipes + \
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HFI_ALIGN(SIZE_AV1D_LB_SE_TOP_CTRL(frame_width, frame_height), \
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VENUS_DMA_ALIGNMENT) + \
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HFI_ALIGN(SIZE_AV1D_LB_PE_TOP_DATA(frame_width, frame_height), \
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VENUS_DMA_ALIGNMENT) + \
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HFI_ALIGN(SIZE_AV1D_LB_VSP_TOP(frame_width, frame_height), \
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VENUS_DMA_ALIGNMENT) + \
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HFI_ALIGN(SIZE_AV1D_LB_RECON_DMA_METADATA_WR(frame_width, \
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frame_height), \
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VENUS_DMA_ALIGNMENT) * 2 + \
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HFI_ALIGN(SIZE_AV1D_QP(frame_width, frame_height), \
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VENUS_DMA_ALIGNMENT); \
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SIZE_AV1D_LB_OPB_WR1_NV12_UBWC(opbwr8, frame_width, frame_height); \
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SIZE_AV1D_LB_OPB_WR1_TP10_UBWC(opbwr10, frame_width, frame_height); \
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opbwr1BufSize = MAX(opbwr8, opbwr10); \
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_size = HFI_ALIGN((_size + opbwr1BufSize), VENUS_DMA_ALIGNMENT); \
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if (isOPB) \
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{ \
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SIZE_VPSS_LB(vpssLBSize, frame_width, frame_height, num_vpp_pipes); \
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_size = HFI_ALIGN((_size + vpssLBSize), VENUS_DMA_ALIGNMENT); \
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} \
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else \
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{ \
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SIZE_AV1D_IBC_NV12_UBWC(ibc8, frame_width, frame_height); \
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SIZE_AV1D_IBC_TP10_UBWC(ibc10, frame_width, frame_height); \
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ibcBufSize = MAX(ibc8, ibc10); \
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_size = HFI_ALIGN((_size + ibcBufSize), VENUS_DMA_ALIGNMENT); \
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} \
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} while (0)
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#define AV1_CABAC_HDR_RATIO_HD_TOT 2
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#define AV1_CABAC_RES_RATIO_HD_TOT 2
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/* some content need more bin buffer,
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* but limit buffer size for high resolution */
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#define SIZE_AV1D_HW_BIN_BUFFER(_size, frame_width, frame_height, delay, \
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num_vpp_pipes) \
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do \
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{ \
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HFI_U32 size_yuv, size_bin_hdr, size_bin_res; \
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size_yuv = ((frame_width * frame_height) <= BIN_BUFFER_THRESHOLD) ? \
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((BIN_BUFFER_THRESHOLD * 3) >> 1) : \
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((frame_width * frame_height * 3) >> 1); \
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size_bin_hdr = size_yuv * AV1_CABAC_HDR_RATIO_HD_TOT; \
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size_bin_res = size_yuv * AV1_CABAC_RES_RATIO_HD_TOT; \
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size_bin_hdr = size_bin_hdr * \
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(((((HFI_U32)(delay)) & 31) / 10) + 2) / 2; \
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size_bin_res = size_bin_res * \
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(((((HFI_U32)(delay)) & 31) / 10) + 2) / 2; \
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size_bin_hdr = HFI_ALIGN(size_bin_hdr / num_vpp_pipes, \
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VENUS_DMA_ALIGNMENT) * num_vpp_pipes; \
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size_bin_res = HFI_ALIGN(size_bin_res / num_vpp_pipes, \
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VENUS_DMA_ALIGNMENT) * num_vpp_pipes; \
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_size = size_bin_hdr + size_bin_res; \
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} while (0)
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#define HFI_BUFFER_BIN_AV1D(_size, frame_width, frame_height, isInterlaced, \
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delay, num_vpp_pipes) \
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do \
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{ \
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HFI_U32 nAlignedW = HFI_ALIGN(frame_width, BUFFER_ALIGNMENT_16_BYTES); \
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HFI_U32 nAlignedH = HFI_ALIGN(frame_height, BUFFER_ALIGNMENT_16_BYTES); \
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if (!isInterlaced) \
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{ \
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SIZE_AV1D_HW_BIN_BUFFER(_size, nAlignedW, nAlignedH, \
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delay, num_vpp_pipes); \
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} \
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else \
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{ \
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_size = 0; \
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} \
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} while (0)
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#define AV1D_NUM_HW_PIC_BUF 16
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#define AV1D_NUM_FRAME_HEADERS 16
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#define SIZE_AV1D_SEQUENCE_HEADER 768
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#define SIZE_AV1D_METADATA 512
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#define SIZE_AV1D_FRAME_HEADER 1280
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#define SIZE_AV1D_TILE_OFFSET 65536
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#define SIZE_AV1D_QM 3328
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#define SIZE_AV1D_PROB_TABLE 22784
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#define AV1D_SIZE_BSE_COL_MV_64x64 512
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#define AV1D_SIZE_BSE_COL_MV_128x128 2816
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#define SIZE_AV1D_COL_MV MAX((((8192 + 63) / 64) * ((4352 + 63) / 64) * \
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AV1D_SIZE_BSE_COL_MV_64x64), \
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(((8192 + 127) / 128) * ((4352 + 127) / 128) * \
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AV1D_SIZE_BSE_COL_MV_128x128))
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#define HFI_BUFFER_PERSIST_AV1D(_size) \
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do \
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{ \
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_size = HFI_ALIGN(SIZE_AV1D_SEQUENCE_HEADER * 2 + \
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SIZE_AV1D_METADATA + \
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AV1D_NUM_HW_PIC_BUF * (SIZE_AV1D_TILE_OFFSET + SIZE_AV1D_QM) + \
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AV1D_NUM_FRAME_HEADERS * (SIZE_AV1D_FRAME_HEADER + \
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2 * SIZE_AV1D_PROB_TABLE) + \
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AV1D_NUM_HW_PIC_BUF * 2 * SIZE_AV1D_COL_MV, VENUS_DMA_ALIGNMENT); \
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} while (0)
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#define HFI_BUFFER_BITSTREAM_ENC(size, frame_width, frame_height, \
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rc_type, is_ten_bit) \
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do \
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