diff --git a/msm/sde/sde_hw_catalog.c b/msm/sde/sde_hw_catalog.c
index 2ccb72fcc4..0c6bc6b354 100644
--- a/msm/sde/sde_hw_catalog.c
+++ b/msm/sde/sde_hw_catalog.c
@@ -426,6 +426,7 @@ enum {
 	MIXER_BLOCKS,
 	MIXER_DISP,
 	MIXER_CWB,
+	MIXER_DCWB,
 	MIXER_PROP_MAX,
 };
 
@@ -711,6 +712,8 @@ static struct sde_prop_type mixer_prop[] = {
 		PROP_TYPE_STRING_ARRAY},
 	{MIXER_CWB, "qcom,sde-mixer-cwb-pref", false,
 		PROP_TYPE_STRING_ARRAY},
+	{MIXER_DCWB, "qcom,sde-mixer-dcwb-pref", false,
+		PROP_TYPE_STRING_ARRAY},
 };
 
 static struct sde_prop_type mixer_blocks_prop[] = {
@@ -2061,6 +2064,8 @@ static int sde_mixer_parse_dt(struct device_node *np,
 			ds_idx = 0; i < off_count; i++) {
 		const char *disp_pref = NULL;
 		const char *cwb_pref = NULL;
+		const char *dcwb_pref = NULL;
+		u32 dummy_mixer_base = 0x0f0f;
 
 		mixer_base = PROP_VALUE_ACCESS(props->values, MIXER_OFF, i);
 		if (!mixer_base)
@@ -2114,6 +2119,16 @@ static int sde_mixer_parse_dt(struct device_node *np,
 		if (cwb_pref && !strcmp(cwb_pref, "cwb"))
 			set_bit(SDE_DISP_CWB_PREF, &mixer->features);
 
+		of_property_read_string_index(np,
+			mixer_prop[MIXER_DCWB].prop_name, i, &dcwb_pref);
+		if (dcwb_pref && !strcmp(dcwb_pref, "dcwb")) {
+			set_bit(SDE_DISP_DCWB_PREF, &mixer->features);
+			if (mixer->base == dummy_mixer_base) {
+				mixer->base = 0x0;
+				mixer->len = 0;
+			}
+		}
+
 		mixer->pingpong = pp_count > 0 ? pp_idx + PINGPONG_0
 							: PINGPONG_MAX;
 		mixer->dspp = dspp_count > 0 ? dspp_idx + DSPP_0
diff --git a/msm/sde/sde_hw_catalog.h b/msm/sde/sde_hw_catalog.h
index 21e97ed6e0..5ddd7c669c 100644
--- a/msm/sde/sde_hw_catalog.h
+++ b/msm/sde/sde_hw_catalog.h
@@ -320,6 +320,7 @@ enum {
  * @SDE_MIXER_GC              Gamma correction block
  * @SDE_DIM_LAYER             Layer mixer supports dim layer
  * @SDE_DISP_CWB_PREF         Layer mixer preferred for CWB
+ * @SDE_DISP_DCWB_PREF        Layer mixer preferred for Dedicated CWB
  * @SDE_DISP_PRIMARY_PREF     Layer mixer preferred for primary display
  * @SDE_DISP_SECONDARY_PREF   Layer mixer preferred for secondary display
  * @SDE_MIXER_COMBINED_ALPHA  Layer mixer bg and fg alpha in single register
@@ -333,6 +334,7 @@ enum {
 	SDE_DISP_PRIMARY_PREF,
 	SDE_DISP_SECONDARY_PREF,
 	SDE_DISP_CWB_PREF,
+	SDE_DISP_DCWB_PREF,
 	SDE_MIXER_COMBINED_ALPHA,
 	SDE_MIXER_MAX
 };
diff --git a/msm/sde/sde_hw_mdss.h b/msm/sde/sde_hw_mdss.h
index 0a1260c051..b6c7daabc0 100644
--- a/msm/sde/sde_hw_mdss.h
+++ b/msm/sde/sde_hw_mdss.h
@@ -153,6 +153,8 @@ enum sde_lm {
 	LM_3,
 	LM_4,
 	LM_5,
+	LM_DCWB_DUMMY_0,
+	LM_DCWB_DUMMY_1,
 	LM_6,
 	LM_MAX
 };
diff --git a/msm/sde/sde_rm.c b/msm/sde/sde_rm.c
index 36e48dcb65..0ddd15402c 100644
--- a/msm/sde/sde_rm.c
+++ b/msm/sde/sde_rm.c
@@ -29,6 +29,7 @@
 #define RM_RQ_DSPP(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DSPP))
 #define RM_RQ_DS(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DS))
 #define RM_RQ_CWB(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_CWB))
+#define RM_RQ_DCWB(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DCWB))
 #define RM_IS_TOPOLOGY_MATCH(t, r) ((t).num_lm == (r).num_lm && \
 				(t).num_comp_enc == (r).num_enc && \
 				(t).num_intf == (r).num_intf && \
@@ -984,7 +985,7 @@ static bool _sde_rm_check_lm_and_get_connected_blks(
 	const struct sde_lm_cfg *lm_cfg = to_sde_hw_mixer(lm->hw)->cap;
 	const struct sde_pingpong_cfg *pp_cfg;
 	bool ret, is_conn_primary, is_conn_secondary;
-	u32 lm_primary_pref, lm_secondary_pref, cwb_pref;
+	u32 lm_primary_pref, lm_secondary_pref, cwb_pref, dcwb_pref;
 
 	*dspp = NULL;
 	*ds = NULL;
@@ -993,6 +994,7 @@ static bool _sde_rm_check_lm_and_get_connected_blks(
 	lm_primary_pref = lm_cfg->features & BIT(SDE_DISP_PRIMARY_PREF);
 	lm_secondary_pref = lm_cfg->features & BIT(SDE_DISP_SECONDARY_PREF);
 	cwb_pref = lm_cfg->features & BIT(SDE_DISP_CWB_PREF);
+	dcwb_pref = lm_cfg->features & BIT(SDE_DISP_DCWB_PREF);
 	is_conn_primary = (reqs->hw_res.display_type ==
 				 SDE_CONNECTOR_PRIMARY) ? true : false;
 	is_conn_secondary = (reqs->hw_res.display_type ==
@@ -1026,8 +1028,9 @@ static bool _sde_rm_check_lm_and_get_connected_blks(
 		 * If CWB is enabled and LM is not CWB supported
 		 * then return false.
 		 */
-		if (RM_RQ_CWB(reqs) && !cwb_pref) {
-			SDE_DEBUG("fail: cwb supported lm not allocated\n");
+		if ((RM_RQ_CWB(reqs) && !cwb_pref) ||
+		    (RM_RQ_DCWB(reqs) && !dcwb_pref)) {
+			SDE_DEBUG("fail: cwb/dcwb supported lm not allocated\n");
 			return false;
 		}
 	} else if ((!is_conn_primary && lm_primary_pref) ||
@@ -1992,6 +1995,7 @@ static int _sde_rm_populate_requirements(
 		struct drm_encoder *enc,
 		struct drm_crtc_state *crtc_state,
 		struct drm_connector_state *conn_state,
+		struct sde_mdss_cfg *cfg,
 		struct sde_rm_requirements *reqs)
 {
 	const struct drm_display_mode *mode = &crtc_state->mode;
@@ -2031,8 +2035,12 @@ static int _sde_rm_populate_requirements(
 	 * Set the requirement for LM which has CWB support if CWB is
 	 * found enabled.
 	 */
-	if (!RM_RQ_CWB(reqs) && sde_encoder_in_clone_mode(enc)) {
-		reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_CWB);
+	if ((!RM_RQ_CWB(reqs) || !RM_RQ_DCWB(reqs))
+				&& sde_encoder_in_clone_mode(enc)) {
+		if (cfg->has_dedicated_cwb_support)
+			reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DCWB);
+		else
+			reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_CWB);
 
 		/*
 		 * topology selection based on conn mode is not valid for CWB
@@ -2476,7 +2484,7 @@ int sde_rm_reserve(
 
 	reqs.hw_res.comp_info = comp_info;
 	ret = _sde_rm_populate_requirements(rm, enc, crtc_state,
-			conn_state, &reqs);
+			conn_state, sde_kms->catalog, &reqs);
 	if (ret) {
 		SDE_ERROR("failed to populate hw requirements\n");
 		goto end;
diff --git a/msm/sde/sde_rm.h b/msm/sde/sde_rm.h
index 9592b5c762..d0cdf77fdd 100644
--- a/msm/sde/sde_rm.h
+++ b/msm/sde/sde_rm.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef __SDE_RM_H__
@@ -104,6 +104,7 @@ enum sde_rm_topology_group {
  * @SDE_RM_TOPCTL_DSPP: Require layer mixers with DSPP capabilities
  * @SDE_RM_TOPCTL_DS  : Require layer mixers with DS capabilities
  * @SDE_RM_TOPCTL_CWB  : Require layer mixers with CWB capabilities
+ * @SDE_RM_TOPCTL_DCWB : Require layer mixers with DCWB capabilities
  */
 enum sde_rm_topology_control {
 	SDE_RM_TOPCTL_RESERVE_LOCK,
@@ -111,6 +112,7 @@ enum sde_rm_topology_control {
 	SDE_RM_TOPCTL_DSPP,
 	SDE_RM_TOPCTL_DS,
 	SDE_RM_TOPCTL_CWB,
+	SDE_RM_TOPCTL_DCWB,
 };
 
 /**