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disp: msm: dsi: enable xlog in critical paths

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Enable xlog in critical paths to increase debug coverage.

Change-Id: I177acd3f2c2ab349f533bb9fbd8a8122539d524b
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
This commit is contained in:
Rajeev Nandan
2020-05-04 22:40:45 +05:30
parent 1c5beba30c
commit 19a54c5650
4 changed files with 55 additions and 13 deletions
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15
msm/dsi/dsi_ctrl.c
View File

@@ -380,6 +380,7 @@ static void dsi_ctrl_flush_cmd_dma_queue(struct dsi_ctrl *dsi_ctrl)
cancel_work_sync(&dsi_ctrl->dma_cmd_wait);
} else {
flush_workqueue(dsi_ctrl->dma_cmd_workq);
SDE_EVT32(SDE_EVTLOG_FUNC_CASE2);
}
}
@@ -432,7 +433,7 @@ static int dsi_ctrl_check_state(struct dsi_ctrl *dsi_ctrl,
int rc = 0;
struct dsi_ctrl_state_info *state = &dsi_ctrl->current_state;
SDE_EVT32(dsi_ctrl->cell_index, op);
SDE_EVT32(dsi_ctrl->cell_index, op, op_state);
switch (op) {
case DSI_CTRL_OP_POWER_STATE_CHANGE:
@@ -1020,6 +1021,7 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
DSI_CTRL_DEBUG(dsi_ctrl, "byte_clk_rate = %llu, byte_intf_clk = %llu\n",
byte_clk_rate, byte_intf_clk_rate);
DSI_CTRL_DEBUG(dsi_ctrl, "pclk_rate = %llu\n", pclk_rate);
SDE_EVT32(dsi_ctrl->cell_index, bit_rate, byte_clk_rate, pclk_rate);
dsi_ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
dsi_ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
@@ -1211,6 +1213,7 @@ void dsi_message_setup_tx_mode(struct dsi_ctrl *dsi_ctrl,
* override cmd fetch mode during secure session
*/
if (dsi_ctrl->secure_mode) {
SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_CASE1);
*flags &= ~DSI_CTRL_CMD_FETCH_MEMORY;
*flags |= DSI_CTRL_CMD_FIFO_STORE;
DSI_CTRL_DEBUG(dsi_ctrl,
@@ -1333,7 +1336,8 @@ static void dsi_kickoff_msg_tx(struct dsi_ctrl *dsi_ctrl,
u32 hw_flags = 0;
struct dsi_ctrl_hw_ops dsi_hw_ops = dsi_ctrl->hw.ops;
SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, flags);
SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, flags,
msg->flags);
if (dsi_ctrl->hw.reset_trig_ctrl)
dsi_hw_ops.reset_trig_ctrl(&dsi_ctrl->hw,
@@ -2859,7 +2863,7 @@ void dsi_ctrl_enable_status_interrupt(struct dsi_ctrl *dsi_ctrl,
intr_idx >= DSI_STATUS_INTERRUPT_COUNT)
return;
SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY);
SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, intr_idx);
spin_lock_irqsave(&dsi_ctrl->irq_info.irq_lock, flags);
if (dsi_ctrl->irq_info.irq_stat_refcount[intr_idx] == 0) {
@@ -2892,7 +2896,7 @@ void dsi_ctrl_disable_status_interrupt(struct dsi_ctrl *dsi_ctrl,
if (!dsi_ctrl || intr_idx >= DSI_STATUS_INTERRUPT_COUNT)
return;
SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY);
SDE_EVT32_IRQ(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, intr_idx);
spin_lock_irqsave(&dsi_ctrl->irq_info.irq_lock, flags);
if (dsi_ctrl->irq_info.irq_stat_refcount[intr_idx])
@@ -3610,6 +3614,7 @@ int dsi_ctrl_set_host_engine_state(struct dsi_ctrl *dsi_ctrl,
dsi_ctrl->hw.ops.ctrl_en(&dsi_ctrl->hw, false);
}
SDE_EVT32(dsi_ctrl->cell_index, state, skip_op);
DSI_CTRL_DEBUG(dsi_ctrl, "Set host engine state = %d\n", state);
dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_HOST_ENGINE, state);
error:
@@ -3653,6 +3658,7 @@ int dsi_ctrl_set_cmd_engine_state(struct dsi_ctrl *dsi_ctrl,
dsi_ctrl->hw.ops.cmd_engine_en(&dsi_ctrl->hw, false);
}
SDE_EVT32(dsi_ctrl->cell_index, state, skip_op);
DSI_CTRL_DEBUG(dsi_ctrl, "Set cmd engine state:%d, skip_op:%d\n",
state, skip_op);
dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_CMD_ENGINE, state);
@@ -3702,6 +3708,7 @@ int dsi_ctrl_set_vid_engine_state(struct dsi_ctrl *dsi_ctrl,
dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw);
}
SDE_EVT32(dsi_ctrl->cell_index, state, skip_op);
DSI_CTRL_DEBUG(dsi_ctrl, "Set video engine state:%d, skip_op:%d\n",
state, skip_op);
dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_VID_ENGINE, state);

28
msm/dsi/dsi_display.c
View File

@@ -849,7 +849,7 @@ int dsi_display_check_status(struct drm_connector *connector, void *display,
rc = -EINVAL;
goto release_panel_lock;
}
SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, status_mode, te_check_override);
if (te_check_override)
te_rechecks = MAX_TE_RECHECKS;
@@ -897,7 +897,7 @@ int dsi_display_check_status(struct drm_connector *connector, void *display,
release_panel_lock:
dsi_panel_release_panel_lock(panel);
SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, rc);
return rc;
}
@@ -1193,6 +1193,7 @@ int dsi_display_set_power(struct drm_connector *connector,
return rc;
}
SDE_EVT32(display->panel->power_mode, power_mode, rc);
DSI_DEBUG("Power mode transition from %d to %d %s",
display->panel->power_mode, power_mode,
rc ? "failed" : "successful");
@@ -4331,6 +4332,7 @@ static int dsi_display_update_dsi_bitrate(struct dsi_display *display,
DSI_DEBUG("byte_clk_rate = %llu, byte_intf_clk_rate = %llu\n",
byte_clk_rate, byte_intf_clk_rate);
DSI_DEBUG("pclk_rate = %llu\n", pclk_rate);
SDE_EVT32(i, bit_rate, byte_clk_rate, pclk_rate);
ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
@@ -4834,6 +4836,9 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display,
DSI_V_TOTAL(timing),
timing->v_front_porch,
&adj_mode->timing.v_front_porch);
SDE_EVT32(SDE_EVTLOG_FUNC_CASE1, DSI_DFPS_IMMEDIATE_VFP,
curr_refresh_rate, timing->refresh_rate,
timing->v_front_porch, adj_mode->timing.v_front_porch);
break;
case DSI_DFPS_IMMEDIATE_HFP:
@@ -4844,6 +4849,9 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display,
dsi_h_total_dce(timing),
timing->h_front_porch,
&adj_mode->timing.h_front_porch);
SDE_EVT32(SDE_EVTLOG_FUNC_CASE2, DSI_DFPS_IMMEDIATE_HFP,
curr_refresh_rate, timing->refresh_rate,
timing->h_front_porch, adj_mode->timing.h_front_porch);
if (!rc)
adj_mode->timing.h_front_porch *= display->ctrl_count;
break;
@@ -4922,7 +4930,7 @@ static int dsi_display_set_mode_sub(struct dsi_display *display,
return -EINVAL;
}
SDE_EVT32(mode->dsi_mode_flags);
SDE_EVT32(mode->dsi_mode_flags, mode->panel_mode);
if (mode->dsi_mode_flags & DSI_MODE_FLAG_POMS) {
display->config.panel_mode = mode->panel_mode;
display->panel->panel_mode = mode->panel_mode;
@@ -5173,6 +5181,7 @@ int dsi_display_cont_splash_config(void *dsi_display)
/* Update splash status for clock manager */
dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
display->is_cont_splash_enabled);
SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, display->is_cont_splash_enabled);
/* Set up ctrl isr before enabling core clk */
dsi_display_ctrl_isr_configure(display, true);
@@ -5231,6 +5240,7 @@ int dsi_display_splash_res_cleanup(struct dsi_display *display)
dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
display->is_cont_splash_enabled);
SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, display->is_cont_splash_enabled);
return rc;
}
@@ -6989,10 +6999,13 @@ int dsi_display_validate_mode_change(struct dsi_display *display,
dyn_clk_caps->maintain_const_fps) {
DSI_DEBUG("Mode switch is seamless variable refresh\n");
adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
SDE_EVT32(cur_mode->timing.refresh_rate,
SDE_EVT32(SDE_EVTLOG_FUNC_CASE1,
cur_mode->timing.refresh_rate,
adj_mode->timing.refresh_rate,
cur_mode->timing.h_front_porch,
adj_mode->timing.h_front_porch);
adj_mode->timing.h_front_porch,
cur_mode->timing.v_front_porch,
adj_mode->timing.v_front_porch);
}
}
@@ -7010,8 +7023,9 @@ int dsi_display_validate_mode_change(struct dsi_display *display,
adj_mode->dsi_mode_flags |=
DSI_MODE_FLAG_DYN_CLK;
SDE_EVT32(cur_mode->pixel_clk_khz,
adj_mode->pixel_clk_khz);
SDE_EVT32(SDE_EVTLOG_FUNC_CASE2,
cur_mode->pixel_clk_khz,
adj_mode->pixel_clk_khz);
}
}
}

21
msm/dsi/dsi_drm.c
View File

@@ -11,6 +11,7 @@
#include "sde_connector.h"
#include "dsi_drm.h"
#include "sde_trace.h"
#include "sde_dbg.h"
#define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base)
#define to_dsi_state(x) container_of((x), struct dsi_connector_state, base)
@@ -411,16 +412,32 @@ static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge,
if ((dsi_mode.panel_mode != cur_dsi_mode.panel_mode) &&
(!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
(crtc_state->enable ==
crtc_state->crtc->state->enable))
crtc_state->crtc->state->enable)) {
dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_POMS;
SDE_EVT32(SDE_EVTLOG_FUNC_CASE1,
dsi_mode.timing.h_active,
dsi_mode.timing.v_active,
dsi_mode.timing.refresh_rate,
dsi_mode.pixel_clk_khz,
dsi_mode.panel_mode);
}
/* No DMS/VRR when drm pipeline is changing */
if (!drm_mode_equal(cur_mode, adjusted_mode) &&
(!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
(!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS)) &&
(!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) &&
(!crtc_state->active_changed ||
display->is_cont_splash_enabled))
display->is_cont_splash_enabled)) {
dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_DMS;
SDE_EVT32(SDE_EVTLOG_FUNC_CASE2,
dsi_mode.timing.h_active,
dsi_mode.timing.v_active,
dsi_mode.timing.refresh_rate,
dsi_mode.pixel_clk_khz,
dsi_mode.panel_mode);
}
}
/* Reject seamless transition when active changed */

4
msm/dsi/dsi_panel.c
View File

@@ -13,6 +13,7 @@
#include "dsi_panel.h"
#include "dsi_ctrl_hw.h"
#include "dsi_parser.h"
#include "sde_dbg.h"
#include "sde_dsc_helper.h"
#include "sde_vdc_helper.h"
@@ -207,6 +208,7 @@ int dsi_panel_trigger_esd_attack(struct dsi_panel *panel)
if (gpio_is_valid(r_config->reset_gpio)) {
gpio_set_value(r_config->reset_gpio, 0);
SDE_EVT32(SDE_EVTLOG_FUNC_CASE1);
DSI_INFO("GPIO pulled low to simulate ESD\n");
return 0;
}
@@ -402,6 +404,7 @@ static int dsi_panel_tx_cmd_set(struct dsi_panel *panel,
cmds = mode->priv_info->cmd_sets[type].cmds;
count = mode->priv_info->cmd_sets[type].count;
state = mode->priv_info->cmd_sets[type].state;
SDE_EVT32(type, state, count);
if (count == 0) {
DSI_DEBUG("[%s] No commands to be sent for state(%d)\n",
@@ -4376,6 +4379,7 @@ int dsi_panel_send_roi_dcs(struct dsi_panel *panel, int ctrl_idx,
}
DSI_DEBUG("[%s] send roi x %d y %d w %d h %d\n", panel->name,
roi->x, roi->y, roi->w, roi->h);
SDE_EVT32(roi->x, roi->y, roi->w, roi->h);
mutex_lock(&panel->panel_lock);