From 19979de0afd9ec3a706bc3ce3b800cff56ab2c6f Mon Sep 17 00:00:00 2001 From: Samantha Tran Date: Tue, 24 Aug 2021 15:07:12 -0700 Subject: [PATCH] disp: msm: sde: update IB vote to include AB factor With this change, the IB vote will be based on the following: IB = AB_aggregated / number of DDR Channels / DRAM efficiency factor Number of DDR Channels and DRAM efficiency factor are now device tree properties which can be modified and parsed at boot up. Change-Id: I298043807150faec1cbc0d74eefcdd1a534b460a Signed-off-by: Samantha Tran --- msm/sde/sde_core_perf.c | 6 ++++++ msm/sde/sde_hw_catalog.c | 12 ++++++++++++ msm/sde/sde_hw_catalog.h | 4 ++++ 3 files changed, 22 insertions(+) diff --git a/msm/sde/sde_core_perf.c b/msm/sde/sde_core_perf.c index 4f83d5fcb4..07351819e8 100644 --- a/msm/sde/sde_core_perf.c +++ b/msm/sde/sde_core_perf.c @@ -713,6 +713,12 @@ static void _sde_core_perf_crtc_update_bus(struct sde_kms *kms, bus_ab_quota = min(bus_ab_quota, kms->catalog->perf.max_bw_high*1000ULL); + if (kms->catalog->perf.num_ddr_channels && kms->catalog->perf.dram_efficiency) { + bus_ib_quota = div_u64(div_u64(bus_ab_quota, + kms->catalog->perf.num_ddr_channels) * 100, + kms->catalog->perf.dram_efficiency); + } + if (kms->perf.perf_tune.mode == SDE_PERF_MODE_FIXED) { bus_ab_quota = max(kms->perf.fix_core_ab_vote, bus_ab_quota); diff --git a/msm/sde/sde_hw_catalog.c b/msm/sde/sde_hw_catalog.c index 9dfabe8155..cb28119c19 100644 --- a/msm/sde/sde_hw_catalog.c +++ b/msm/sde/sde_hw_catalog.c @@ -139,6 +139,8 @@ "NV12/5/1/1.25 AB24/5/1/1.25 XB24/5/1/1.25" #define DEFAULT_MAX_PER_PIPE_BW 2400000 #define DEFAULT_AMORTIZABLE_THRESHOLD 25 +#define DEFAULT_NUM_DDR_CHANNELS 4 +#define DEFAULT_DRAM_EFFICIENCY 64 #define DEFAULT_MNOC_PORTS 2 #define DEFAULT_AXI_BUS_WIDTH 32 #define DEFAULT_CPU_MASK 0 @@ -236,6 +238,8 @@ enum { PERF_LINEAR_PREFILL_LINES, PERF_DOWNSCALING_PREFILL_LINES, PERF_XTRA_PREFILL_LINES, + PERF_NUM_DDR_CHANNELS, + PERF_DRAM_EFFICIENCY, PERF_AMORTIZABLE_THRESHOLD, PERF_NUM_MNOC_PORTS, PERF_AXI_BUS_WIDTH, @@ -633,6 +637,8 @@ static struct sde_prop_type sde_perf_prop[] = { false, PROP_TYPE_U32}, {PERF_XTRA_PREFILL_LINES, "qcom,sde-xtra-prefill-lines", false, PROP_TYPE_U32}, + {PERF_NUM_DDR_CHANNELS, "qcom,sde-num-ddr-channels", false, PROP_TYPE_U32}, + {PERF_DRAM_EFFICIENCY, "qcom,sde-dram-efficiency", false, PROP_TYPE_U32}, {PERF_AMORTIZABLE_THRESHOLD, "qcom,sde-amortizable-threshold", false, PROP_TYPE_U32}, {PERF_NUM_MNOC_PORTS, "qcom,sde-num-mnoc-ports", @@ -4342,6 +4348,12 @@ static void _sde_perf_parse_dt_cfg_populate(struct sde_mdss_cfg *cfg, PROP_VALUE_ACCESS(prop_value, PERF_AMORTIZABLE_THRESHOLD, 0) : DEFAULT_AMORTIZABLE_THRESHOLD; + cfg->perf.num_ddr_channels = prop_exists[PERF_NUM_DDR_CHANNELS] ? + PROP_VALUE_ACCESS(prop_value, PERF_NUM_DDR_CHANNELS, 0) : + DEFAULT_NUM_DDR_CHANNELS; + cfg->perf.dram_efficiency = prop_exists[PERF_DRAM_EFFICIENCY] ? + PROP_VALUE_ACCESS(prop_value, PERF_DRAM_EFFICIENCY, 0) : + DEFAULT_DRAM_EFFICIENCY; cfg->perf.num_mnoc_ports = prop_exists[PERF_NUM_MNOC_PORTS] ? PROP_VALUE_ACCESS(prop_value, diff --git a/msm/sde/sde_hw_catalog.h b/msm/sde/sde_hw_catalog.h index 5e2974796f..f6ac278383 100644 --- a/msm/sde/sde_hw_catalog.h +++ b/msm/sde/sde_hw_catalog.h @@ -1431,6 +1431,8 @@ struct sde_sc_cfg { * @cpu_mask_perf: pm_qos cpu silver core mask value * @cpu_dma_latency: pm_qos cpu dma latency value * @cpu_irq_latency: pm_qos cpu irq latency value + * @num_ddr_channels: number of DDR channels + * @dram_efficiency: DRAM efficiency factor * @axi_bus_width: axi bus width value in bytes * @num_mnoc_ports: number of mnoc ports */ @@ -1463,6 +1465,8 @@ struct sde_perf_cfg { unsigned long cpu_mask_perf; u32 cpu_dma_latency; u32 cpu_irq_latency; + u32 num_ddr_channels; + u32 dram_efficiency; u32 axi_bus_width; u32 num_mnoc_ports; };