Merge "msm: camera: cre: Enable CRE module" into camera-kernel.lnx.7.0

Kconfig

@@ -21,7 +21,13 @@ config SPECTRA_JPEG
 	  camera jpeg module will be functional.
 	  This module interact with jpeg HW for
 	  snapshot processing.
-
+config SPECTRA_CRE
+	bool "enable camera jpeg module"
+	help
+	  This is enabling camera CRE module.
+	  camera cre module will be functional.
+	  This module interact with cre HW for
+	  format conversion.
 config SPECTRA_SENSOR
 	bool "enable camera sensor module"
 	help

camera_modules.bzl

@@ -148,6 +148,19 @@ def _define_module(target, variant):
                     "drivers/cam_jpeg/cam_jpeg_context.c",
                 ],
             },
+            "CONFIG_SPECTRA_CRE": {
+                True: [
+                    "drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_core.c",
+                    "drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_soc.c",
+                    "drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_dev.c",
+                    "drivers/cam_cre/cam_cre_hw_mgr/cre_hw/top/cre_top.c",
+                    "drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_rd/cre_bus_rd.c",
+                    "drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_wr/cre_bus_wr.c",
+                    "drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.c",
+                    "drivers/cam_cre/cam_cre_dev.c",
+                    "drivers/cam_cre/cam_cre_context.c",
+                ],
+            },
             "CONFIG_SPECTRA_SENSOR": {
                 True: [
                     "drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.c",

config/pineapple.mk

@@ -4,6 +4,7 @@
 CONFIG_SPECTRA_ISP := y
 CONFIG_SPECTRA_ICP := y
 CONFIG_SPECTRA_JPEG := y
+CONFIG_SPECTRA_CRE := y
 CONFIG_SPECTRA_SENSOR := y
 CONFIG_SPECTRA_LLCC_STALING := y
 CONFIG_SPECTRA_USE_RPMH_DRV_API := y
@@ -15,6 +16,7 @@ CONFIG_DYNAMIC_FD_PORT_CONFIG := y
 ccflags-y += -DCONFIG_SPECTRA_ISP=1
 ccflags-y += -DCONFIG_SPECTRA_ICP=1
 ccflags-y += -DCONFIG_SPECTRA_JPEG=1
+ccflags-y += -DCONFIG_SPECTRA_CRE=1
 ccflags-y += -DCONFIG_SPECTRA_SENSOR=1
 ccflags-y += -DCONFIG_SPECTRA_LLCC_STALING=1
 ccflags-y += -DCONFIG_SPECTRA_USE_RPMH_DRV_API=1

drivers/cam_cre/cam_cre_context.c

@@ -43,7 +43,7 @@ static int __cam_cre_ctx_flush_dev_in_ready(struct cam_context *ctx,
 	flush_args.cmd = cmd;
 	flush_args.flush_active_req = false;
 
-	rc = cam_context_flush_dev_to_hw(ctx, cmd, &flush_args);
+	rc = cam_context_flush_dev_to_hw(ctx, &flush_args);
 	if (rc)
 		CAM_ERR(CAM_CRE, "Failed to flush device");
 

drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.c

@@ -210,9 +210,17 @@ static int cam_cre_mgr_process_cmd_io_buf_req(struct cam_cre_hw_mgr *hw_mgr,
 
 				/* Width for WE has to be updated in number of pixels */
 				if (acq_io_buf->direction == CAM_BUF_OUTPUT) {
-					/* PLAIN 128/8 = 16 Bytes per pixel */
-					plane_info->width =
-						io_cfg_ptr[j].planes[k].plane_stride/16;
+					if (plane_info->format == CAM_FORMAT_PLAIN16_10) {
+						plane_info->width =
+							io_cfg_ptr[j].planes[k].plane_stride/2;
+					} else if (plane_info->format == CAM_FORMAT_PLAIN128) {
+						/* PLAIN 128/8 = 16 Bytes per pixel */
+						plane_info->width =
+							io_cfg_ptr[j].planes[k].plane_stride/16;
+					} else {
+						plane_info->width =
+							io_cfg_ptr[j].planes[k].width;
+					}
 				} else {
 					/* FE width should be in bytes */
 					plane_info->width     =
@@ -402,10 +410,6 @@ static int cam_cre_mgr_remove_bw(struct cam_cre_hw_mgr *hw_mgr, int ctx_id)
 			ctx_data->clk_info.axi_path[i].mnoc_ab_bw;
 		hw_mgr_clk_info->axi_path[path_index].mnoc_ib_bw -=
 			ctx_data->clk_info.axi_path[i].mnoc_ib_bw;
-		hw_mgr_clk_info->axi_path[path_index].ddr_ab_bw -=
-			ctx_data->clk_info.axi_path[i].ddr_ab_bw;
-		hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw -=
-			ctx_data->clk_info.axi_path[i].ddr_ib_bw;
 	}
 
 	rc = cam_cre_update_cpas_vote(hw_mgr, ctx_data);
@@ -474,10 +478,6 @@ static bool cam_cre_update_bw_v2(struct cam_cre_hw_mgr *hw_mgr,
 			ctx_data->clk_info.axi_path[i].mnoc_ab_bw;
 		hw_mgr_clk_info->axi_path[path_index].mnoc_ib_bw -=
 			ctx_data->clk_info.axi_path[i].mnoc_ib_bw;
-		hw_mgr_clk_info->axi_path[path_index].ddr_ab_bw -=
-			ctx_data->clk_info.axi_path[i].ddr_ab_bw;
-		hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw -=
-			ctx_data->clk_info.axi_path[i].ddr_ib_bw;
 	}
 
 	ctx_data->clk_info.num_paths =
@@ -515,10 +515,6 @@ static bool cam_cre_update_bw_v2(struct cam_cre_hw_mgr *hw_mgr,
 			ctx_data->clk_info.axi_path[i].mnoc_ab_bw;
 		hw_mgr_clk_info->axi_path[path_index].mnoc_ib_bw +=
 			ctx_data->clk_info.axi_path[i].mnoc_ib_bw;
-		hw_mgr_clk_info->axi_path[path_index].ddr_ab_bw +=
-			ctx_data->clk_info.axi_path[i].ddr_ab_bw;
-		hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw +=
-			ctx_data->clk_info.axi_path[i].ddr_ib_bw;
 		CAM_DBG(CAM_CRE,
 			"Consolidate Path Vote : Dev[%s] i[%d] path_idx[%d] : [%s %s] [%lld %lld]",
 			ctx_data->cre_acquire.dev_name,
@@ -1550,6 +1546,12 @@ static int cam_cre_validate_acquire_res_info(
 					cre_acquire->in_res[i].format);
 				return -EINVAL;
 		}
+
+		if (!cre_acquire->in_res[i].width || !cre_acquire->in_res[i].height) {
+			CAM_ERR(CAM_CRE, "Invalid width %d height %d for in res %d",
+				cre_acquire->in_res[i].width, cre_acquire->in_res[i].height, i);
+			return -EINVAL;
+		}
 	}
 
 	for (i = 0; i < cre_acquire->num_out_res; i++) {
@@ -1794,8 +1796,6 @@ static int cam_cre_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args)
 			hw_mgr->clk_info.axi_path[i].camnoc_bw = 0;
 			hw_mgr->clk_info.axi_path[i].mnoc_ab_bw = 0;
 			hw_mgr->clk_info.axi_path[i].mnoc_ib_bw = 0;
-			hw_mgr->clk_info.axi_path[i].ddr_ab_bw = 0;
-			hw_mgr->clk_info.axi_path[i].ddr_ib_bw = 0;
 		}
 	}
 
@@ -1843,8 +1843,6 @@ static int cam_cre_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args)
 		bw_update->axi_vote.axi_path[0].camnoc_bw = 600000000;
 		bw_update->axi_vote.axi_path[0].mnoc_ab_bw = 600000000;
 		bw_update->axi_vote.axi_path[0].mnoc_ib_bw = 600000000;
-		bw_update->axi_vote.axi_path[0].ddr_ab_bw = 600000000;
-		bw_update->axi_vote.axi_path[0].ddr_ib_bw = 600000000;
 		bw_update->axi_vote.axi_path[0].transac_type =
 			CAM_AXI_TRANSACTION_WRITE;
 		bw_update->axi_vote.axi_path[0].path_data_type =
@@ -2106,20 +2104,20 @@ static int cam_cre_packet_generic_blob_handler(void *user_data,
 
 		clk_info = &ctx_data->req_list[index]->clk_info;
 		clk_info_v2 = &ctx_data->req_list[index]->clk_info_v2;
-		clk_info_v2.budget_ns = soc_req->budget_ns;
-		clk_info_v2.frame_cycles = soc_req->frame_cycles;
-		clk_info_v2.rt_flag = soc_req->rt_flag;
-		clk_info_v2.num_paths = soc_req->num_paths;
+		clk_info_v2->budget_ns = soc_req->budget_ns;
+		clk_info_v2->frame_cycles = soc_req->frame_cycles;
+		clk_info_v2->rt_flag = soc_req->rt_flag;
+		clk_info_v2->num_paths = soc_req->num_paths;
 
 		for (i = 0; i < soc_req->num_paths; i++) {
-			clk_info_v2.axi_path[i].usage_data = soc_req->axi_path[i].usage_data;
-			clk_info_v2.axi_path[i].transac_type = soc_req->axi_path[i].transac_type;
-			clk_info_v2.axi_path[i].path_data_type =
+			clk_info_v2->axi_path[i].usage_data = soc_req->axi_path[i].usage_data;
+			clk_info_v2->axi_path[i].transac_type = soc_req->axi_path[i].transac_type;
+			clk_info_v2->axi_path[i].path_data_type =
 				soc_req->axi_path[i].path_data_type;
-			clk_info_v2.axi_path[i].vote_level = 0;
-			clk_info_v2.axi_path[i].camnoc_bw = soc_req->axi_path[i].camnoc_bw;
-			clk_info_v2.axi_path[i].mnoc_ab_bw = soc_req->axi_path[i].mnoc_ab_bw;
-			clk_info_v2.axi_path[i].mnoc_ib_bw = soc_req->axi_path[i].mnoc_ib_bw;
+			clk_info_v2->axi_path[i].vote_level = 0;
+			clk_info_v2->axi_path[i].camnoc_bw = soc_req->axi_path[i].camnoc_bw;
+			clk_info_v2->axi_path[i].mnoc_ab_bw = soc_req->axi_path[i].mnoc_ab_bw;
+			clk_info_v2->axi_path[i].mnoc_ib_bw = soc_req->axi_path[i].mnoc_ib_bw;
 		}
 
 		/* Use v1 structure for clk fields */
@@ -2288,7 +2286,6 @@ static int cam_cre_mgr_prepare_hw_update(void *hw_priv,
 
 	prepare_args->num_hw_update_entries = 1;
 	prepare_args->priv = ctx_data->req_list[request_idx];
-	cre_req->hang_data.packet = packet;
 	ktime_get_boottime_ts64(&ts);
 	ctx_data->last_req_time = (uint64_t)((ts.tv_sec * 1000000000) +
 		ts.tv_nsec);
@@ -2413,6 +2410,7 @@ config_err:
 static void cam_cre_mgr_dump_pf_data(struct cam_cre_hw_mgr  *hw_mgr,
 	struct cam_hw_cmd_pf_args *pf_cmd_args)
 {
+	int rc = 0;
 	struct cam_packet          *packet;
 	struct cam_hw_dump_pf_args *pf_args;
 	size_t                      len;

drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_rd/cre_bus_rd.c

@@ -1,7 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
+
 #include <linux/delay.h>
 #include "cam_hw.h"
 #include "cam_hw_intf.h"
@@ -66,7 +68,7 @@ static void cam_cre_update_read_reg_val(struct plane_info p_info,
 		p_info.alignment);
 
 	/* Fetch engine width has to be updated in number of bytes */
-	rd_client_reg_val->img_width  = p_info.stride;
+	rd_client_reg_val->img_width  = p_info.width;
 	rd_client_reg_val->stride     = p_info.stride;
 	rd_client_reg_val->img_height = p_info.height;
 	rd_client_reg_val->alignment  = p_info.alignment;
@@ -179,7 +181,7 @@ static int cam_cre_bus_rd_update(struct cam_cre_hw *cam_cre_hw_info,
 		/* Buffer size */
 		update_cre_reg_set(cre_reg_buf,
 			rd_reg->offset + rd_reg_client->rd_width,
-			rd_client_reg_val->img_width);
+			ctx_data->cre_acquire.in_res[in_port_idx].width);
 		update_cre_reg_set(cre_reg_buf,
 			rd_reg->offset + rd_reg_client->rd_height,
 			rd_client_reg_val->img_height);
@@ -441,7 +443,8 @@ static int cam_cre_bus_rd_isr(struct cam_cre_hw *cam_cre_hw_info,
 	int32_t ctx_id, void *data)
 {
 	uint32_t irq_status;
-	uint32_t violation_status;
+	uint32_t const_violation_status;
+	uint32_t ccif_violation_status;
 	uint32_t debug_status_0;
 	uint32_t debug_status_1;
 	struct cam_cre_bus_rd_reg *bus_rd_reg;
@@ -464,24 +467,30 @@ static int cam_cre_bus_rd_isr(struct cam_cre_hw *cam_cre_hw_info,
 	cam_io_w_mb(bus_rd_reg_val->irq_cmd_clear,
 		bus_rd_reg->base + bus_rd_reg->irq_cmd);
 
+	CAM_DBG(CAM_CRE, "BUS irq_status 0x%x", irq_status);
+
 	if (irq_status & bus_rd_reg_val->rup_done)
 		CAM_DBG(CAM_CRE, "CRE Read Bus RUP done");
 
 	if (irq_status & bus_rd_reg_val->rd_buf_done)
 		CAM_DBG(CAM_CRE, "CRE Read Bus Buff done");
 
-	if (irq_status & bus_rd_reg_val->cons_violation) {
+	if ((irq_status & bus_rd_reg_val->cons_violation) ||
+		(irq_status & bus_rd_reg_val->ccif_violation)) {
 		irq_data->error = 1;
-		violation_status = cam_io_r_mb(bus_rd_reg->base +
-			bus_rd_reg->rd_clients[0].cons_violation_status);
+		const_violation_status = cam_io_r_mb(bus_rd_reg->base +
+			bus_rd_reg->cons_violation);
+		ccif_violation_status = cam_io_r_mb(bus_rd_reg->base +
+			bus_rd_reg->ccif_violation);
 		debug_status_0 = cam_io_r_mb(bus_rd_reg->base +
 			bus_rd_reg->rd_clients[0].debug_status_0);
 		debug_status_1 = cam_io_r_mb(bus_rd_reg->base +
 			bus_rd_reg->rd_clients[0].debug_status_1);
 		CAM_DBG(CAM_CRE, "CRE Read Bus Violation");
 		CAM_DBG(CAM_CRE,
-			"violation status 0x%x debug status 0/1 0x%x/0x%x",
-			violation_status, debug_status_0, debug_status_1);
+			"violation status 0x%x 0x%x debug status 0/1 0x%x/0x%x",
+			const_violation_status, ccif_violation_status,
+			debug_status_0, debug_status_1);
 	}
 
 	return 0;

drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_wr/cre_bus_wr.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 #include <linux/delay.h>
 #include "cam_io_util.h"
@@ -22,6 +23,70 @@ static struct cre_bus_wr *wr_info;
 		cre_reg_buf->num_wr_reg_set++; \
 	} while (0)
 
+static uint32_t cam_cre_bus_wr_format_idx(uint32_t format)
+{
+	uint32_t format_idx = 0;
+
+	switch(format) {
+	case CAM_FORMAT_PLAIN128:
+		format_idx = 0x0;
+		break;
+	case CAM_FORMAT_PLAIN8:
+		format_idx = 0x1;
+		break;
+	case CAM_FORMAT_PLAIN8_SWAP:
+		format_idx = 0x2;
+		break;
+	case CAM_FORMAT_PLAIN8_10:
+		format_idx = 0x3;
+		break;
+	case CAM_FORMAT_PLAIN8_10_SWAP:
+		format_idx = 0x4;
+		break;
+	case CAM_FORMAT_PLAIN16_10:
+		format_idx = 0x5;
+		break;
+	case CAM_FORMAT_PLAIN16_12:
+		format_idx = 0x6;
+		break;
+	case CAM_FORMAT_PLAIN16_14:
+		format_idx = 0x7;
+		break;
+	case CAM_FORMAT_PLAIN16_16:
+		format_idx = 0x8;
+		break;
+	case CAM_FORMAT_PLAIN32:
+		format_idx = 0x9;
+		break;
+	case CAM_FORMAT_PLAIN64:
+		format_idx = 0xA;
+		break;
+	case CAM_FORMAT_PD10:
+		format_idx = 0xB;
+		break;
+	case CAM_FORMAT_MIPI_RAW_10:
+		format_idx = 0xC;
+		break;
+	case CAM_FORMAT_MIPI_RAW_12:
+		format_idx = 0xD;
+		break;
+	case CAM_FORMAT_MIPI_RAW_14:
+		format_idx = 0xE;
+		break;
+	case CAM_FORMAT_MIPI_RAW_20:
+		format_idx = 0xF;
+		break;
+	case CAM_FORMAT_PLAIN32_20:
+		format_idx = 0x10;
+		break;
+	default:
+		CAM_WARN(CAM_CRE, "Invalid format %d", format);
+		break;
+	}
+
+	return format_idx;
+}
+
 static int cam_cre_translate_write_format(struct plane_info p_info,
 	struct cam_cre_bus_wr_client_reg_val *wr_client_reg_val)
 {
@@ -36,12 +101,7 @@ static int cam_cre_translate_write_format(struct plane_info p_info,
 	wr_client_reg_val->height    = p_info.height;
 	wr_client_reg_val->alignment = p_info.alignment;
 
-	/*
-	 * Update packer format to zero irrespective of output format
-	 * This is as per the recomendation from CRE HW team for CRE 1.0
-	 * This logic has to be updated for CRE 1.1
-	 */
-	wr_client_reg_val->format = 0;
+	wr_client_reg_val->format = p_info.format;
 
 	return 0;
 }
@@ -101,6 +161,7 @@ static int cam_cre_bus_wr_update(struct cam_cre_hw *cam_cre_hw_info,
 	int rc, k, out_port_idx;
 	uint32_t req_idx;
 	uint32_t val = 0;
+	uint32_t format_idx = 0;
 	uint32_t iova_base, iova_offset;
 	struct cam_hw_prepare_update_args *prepare_args;
 	struct cam_cre_ctx *ctx_data;
@@ -204,12 +265,13 @@ static int cam_cre_bus_wr_update(struct cam_cre_hw *cam_cre_hw_info,
 			wr_client_reg_val->stride);
 
 		val = 0;
-		val |= ((wr_client_reg_val->format &
-			wr_client_reg_val->format_mask) <<
+		format_idx = cam_cre_bus_wr_format_idx(wr_client_reg_val->format);
+		val |= ((format_idx & wr_client_reg_val->format_mask) <<
 			wr_client_reg_val->format_shift);
-		val |= ((wr_client_reg_val->alignment &
-			wr_client_reg_val->alignment_mask) <<
-			wr_client_reg_val->alignment_shift);
+
+		/* Update alignment as LSB by default*/
+		val |= (0x1 << wr_client_reg_val->alignment_shift);
+
 		/* pack cfg : Format and alignment */
 		update_cre_reg_set(cre_reg_buf,
 			wr_reg->offset + wr_reg_client->packer_cfg,

drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_core.c

@@ -168,10 +168,6 @@ int cam_cre_init_hw(void *device_priv,
 		CAM_CPAS_DEFAULT_AXI_BW;
 	cpas_vote->axi_vote.axi_path[0].mnoc_ib_bw =
 		CAM_CPAS_DEFAULT_AXI_BW;
-	cpas_vote->axi_vote.axi_path[0].ddr_ab_bw =
-		CAM_CPAS_DEFAULT_AXI_BW;
-	cpas_vote->axi_vote.axi_path[0].ddr_ib_bw =
-		CAM_CPAS_DEFAULT_AXI_BW;
 
 	rc = cam_cpas_start(core_info->cpas_handle,
 		&cpas_vote->ahb_vote, &cpas_vote->axi_vote);

drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_dev.c

@@ -18,6 +18,7 @@
 #include "cam_cpas_api.h"
 #include "cam_debug_util.h"
 #include "cre_hw_100.h"
+#include "cre_hw_110.h"
 #include "cre_dev_intf.h"
 #include "cam_smmu_api.h"
 #include "camera_main.h"
@@ -58,6 +59,17 @@ static int cam_cre_init_hw_version(struct cam_hw_soc_info *soc_info,
 	switch (core_info->hw_version) {
 	case CRE_HW_VER_1_0_0:
 		core_info->cre_hw_info->cre_hw = &cre_hw_100;
+
+		cre_hw_100.top_reg_offset->base = core_info->cre_hw_info->cre_top_base;
+		cre_hw_100.bus_rd_reg_offset->base = core_info->cre_hw_info->cre_bus_rd_base;
+		cre_hw_100.bus_wr_reg_offset->base = core_info->cre_hw_info->cre_bus_wr_base;
+		break;
+	case CRE_HW_VER_1_1_0:
+		core_info->cre_hw_info->cre_hw = &cre_hw_110;
+
+		cre_hw_110.top_reg_offset->base = core_info->cre_hw_info->cre_top_base;
+		cre_hw_110.bus_rd_reg_offset->base = core_info->cre_hw_info->cre_bus_rd_base;
+		cre_hw_110.bus_wr_reg_offset->base = core_info->cre_hw_info->cre_bus_wr_base;
 		break;
 	default:
 		CAM_ERR(CAM_CRE, "Unsupported version : %u",
@@ -66,9 +78,6 @@ static int cam_cre_init_hw_version(struct cam_hw_soc_info *soc_info,
 		break;
 	}
 
-	cre_hw_100.top_reg_offset->base = core_info->cre_hw_info->cre_top_base;
-	cre_hw_100.bus_rd_reg_offset->base = core_info->cre_hw_info->cre_bus_rd_base;
-	cre_hw_100.bus_wr_reg_offset->base = core_info->cre_hw_info->cre_bus_wr_base;
 
 	return rc;
 }
@@ -200,10 +209,6 @@ static int cam_cre_component_bind(struct device *dev,
 		CAM_CPAS_DEFAULT_AXI_BW;
 	cpas_vote.axi_vote.axi_path[0].mnoc_ib_bw =
 		CAM_CPAS_DEFAULT_AXI_BW;
-	cpas_vote.axi_vote.axi_path[0].ddr_ab_bw =
-		CAM_CPAS_DEFAULT_AXI_BW;
-	cpas_vote.axi_vote.axi_path[0].ddr_ib_bw =
-		CAM_CPAS_DEFAULT_AXI_BW;
 
 	rc = cam_cpas_start(core_info->cpas_handle,
 		&cpas_vote.ahb_vote, &cpas_vote.axi_vote);

drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw.h

@@ -1,12 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef CAM_CRE_HW_H
 #define CAM_CRE_HW_H
 
 #define CRE_HW_VER_1_0_0 0x10000000
+#define CRE_HW_VER_1_1_0 0x10010000
 
 #define CRE_DEV_CRE  0
 #define CRE_DEV_MAX  1
@@ -87,6 +89,7 @@ struct cam_cre_bus_rd_client_reg {
 	uint32_t misr_cfg_0;
 	uint32_t misr_cfg_1;
 	uint32_t misr_rd_val;
+	uint32_t system_cache_cfg;
 	uint32_t debug_status_cfg;
 	uint32_t debug_status_0;
 	uint32_t debug_status_1;
@@ -109,6 +112,8 @@ struct cam_cre_bus_rd_reg {
 	uint32_t iso_cfg;
 	uint32_t iso_seed;
 	uint32_t test_bus_ctrl;
+	uint32_t cons_violation;
+	uint32_t ccif_violation;
 
 	uint32_t num_clients;
 	struct   cam_cre_bus_rd_client_reg rd_clients[MAX_CRE_RD_CLIENTS];
@@ -161,6 +166,7 @@ struct cam_cre_bus_rd_reg_val {
 	uint32_t rup_done;
 	uint32_t rd_buf_done;
 	uint32_t cons_violation;
+	uint32_t ccif_violation;
 	uint32_t static_prg;
 	uint32_t static_prg_mask;
 	uint32_t ica_en;
@@ -190,8 +196,9 @@ struct cam_cre_bus_wr_client_reg {
 	uint32_t img_cfg_0;
 	uint32_t img_cfg_1;
 	uint32_t img_cfg_2;
-	uint32_t bw_limit;
 	uint32_t packer_cfg;
+	uint32_t bw_limit;
+	uint32_t system_cache_cfg;
 	uint32_t addr_cfg;
 	uint32_t debug_status_cfg;
 	uint32_t debug_status_0;

drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw_100.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef CAM_CRE_HW_100_H
@@ -11,7 +12,7 @@
 #define CRE_BUS_RD_TYPE            0x1
 #define CRE_BUS_WR_TYPE            0x2
 
-static struct cam_cre_top_reg top_reg = {
+static struct cam_cre_top_reg cre100_top_reg = {
 	.hw_version            =  0x000,
 	.hw_cap                =  0x004,
 	.debug_0               =  0x080,
@@ -30,7 +31,7 @@ static struct cam_cre_top_reg top_reg = {
 	.top_spare             =  0x1FC,
 };
 
-struct cam_cre_top_reg_val top_reg_value = {
+struct cam_cre_top_reg_val cre100_top_reg_value = {
 	.hw_version = 0x10000000,
 	.hw_cap = 0x4000,
 	.irq_mask = 0xf,
@@ -46,7 +47,7 @@ struct cam_cre_top_reg_val top_reg_value = {
 	.hw_reset_cmd = 0x1,
 };
 
-struct cam_cre_bus_rd_reg bus_rd_reg = {
+struct cam_cre_bus_rd_reg cre100_bus_rd_reg = {
 	.hw_version     = 0x00,
 	.irq_mask       = 0x04,
 	.irq_clear      = 0x08,
@@ -82,7 +83,7 @@ struct cam_cre_bus_rd_reg bus_rd_reg = {
 	},
 };
 
-struct cam_cre_bus_wr_reg_val bus_wr_reg_value = {
+struct cam_cre_bus_wr_reg_val cre100_bus_wr_reg_value = {
 	.hw_version                   = 0x30000000,
 	.cgc_override                 = 0x1,
 	.irq_mask_0                   = 0xd0000101,
@@ -137,7 +138,7 @@ struct cam_cre_bus_wr_reg_val bus_wr_reg_value = {
 	},
 };
 
-struct cam_cre_bus_rd_reg_val bus_rd_reg_value = {
+struct cam_cre_bus_rd_reg_val cre100_bus_rd_reg_value = {
 	.hw_version              = 0x30000000,
 	.irq_mask                = 0x1, /* INFO_CONS_VIOLATION */
 	.rd_buf_done             = 0x4,
@@ -183,7 +184,7 @@ struct cam_cre_bus_rd_reg_val bus_rd_reg_value = {
 	},
 };
 
-struct cam_cre_bus_wr_reg bus_wr_reg = {
+struct cam_cre_bus_wr_reg cre100_bus_wr_reg = {
 	.hw_version                   = 0x00,
 	.cgc_override                 = 0x08,
 	.irq_mask_0                   = 0x18,
@@ -230,11 +231,11 @@ struct cam_cre_bus_wr_reg bus_wr_reg = {
 };
 
 static struct cam_cre_hw cre_hw_100 = {
-	.top_reg_offset    = &top_reg,
-	.top_reg_val       = &top_reg_value,
-	.bus_wr_reg_offset = &bus_wr_reg,
-	.bus_wr_reg_val    = &bus_wr_reg_value,
-	.bus_rd_reg_offset = &bus_rd_reg,
-	.bus_rd_reg_val    = &bus_rd_reg_value,
+	.top_reg_offset    = &cre100_top_reg,
+	.top_reg_val       = &cre100_top_reg_value,
+	.bus_wr_reg_offset = &cre100_bus_wr_reg,
+	.bus_wr_reg_val    = &cre100_bus_wr_reg_value,
+	.bus_rd_reg_offset = &cre100_bus_rd_reg,
+	.bus_rd_reg_val    = &cre100_bus_rd_reg_value,
 };
 #endif // CAM_CRE_HW_100_H

drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_hw_110.h

@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef CAM_CRE_HW_110_H
+#define CAM_CRE_HW_110_H
+
+#include "cre_hw.h"
+
+#define CRE_BUS_RD_TYPE            0x1
+#define CRE_BUS_WR_TYPE            0x2
+
+static struct cam_cre_top_reg cre110_top_reg = {
+	.hw_version            =  0x000,
+	.hw_cap                =  0x004,
+	.debug_0               =  0x080,
+	.debug_1               =  0x084,
+	.debug_cfg             =  0x0DC,
+	.testbus_ctrl          =  0x1F4,
+	.scratch_0             =  0x1F8,
+	.irq_status            =  0x00C,
+	.irq_mask              =  0x010,
+	.irq_clear             =  0x014,
+	.irq_set               =  0x018,
+	.irq_cmd               =  0x01C,
+	.reset_cmd             =  0x008,
+	.core_clk_cfg_ctrl_0   =  0x020,
+	.core_clk_cfg_ctrl_1   =  0x024,
+	.top_spare             =  0x1FC,
+};
+
+struct cam_cre_top_reg_val cre110_top_reg_value = {
+	.hw_version = 0x10010000,
+	.hw_cap = 0x4000,
+	.irq_mask = 0xf,
+	.irq_clear = 0xf,
+	.irq_set = 0xf,
+	.irq_cmd_set = 0xf,
+	.irq_cmd_clear = 0xf,
+	.idle = 0x8,
+	.fe_done = 0x4,
+	.we_done = 0x2,
+	.rst_done = 0x1,
+	.sw_reset_cmd = 0x2,
+	.hw_reset_cmd = 0x1,
+};
+
+struct cam_cre_bus_rd_reg cre110_bus_rd_reg = {
+	.hw_version     = 0x00,
+	.irq_mask       = 0x04,
+	.irq_clear      = 0x08,
+	.irq_cmd        = 0x0C,
+	.irq_status     = 0x10,
+	.input_if_cmd   = 0x14,
+	.irq_set        = 0x18,
+	.misr_reset     = 0x1C,
+	.security_cfg   = 0x20,
+	.iso_cfg        = 0x24,
+	.iso_seed       = 0x28,
+	.test_bus_ctrl  = 0x2C,
+	.cons_violation = 0x30,
+	.ccif_violation = 0x34,
+	.num_clients    = 1,
+	.rd_clients[0]  = {
+		.core_cfg               = 0x50,
+		.ccif_meta_data         = 0x54,
+		.img_addr               = 0x58,
+		.rd_width               = 0x5C,
+		.rd_height              = 0x60,
+		.rd_stride              = 0x64,
+		.unpacker_cfg           = 0x68,
+		.latency_buf_allocation = 0x7C,
+		.misr_cfg_0             = 0x84,
+		.misr_cfg_1             = 0x88,
+		.misr_rd_val            = 0x8C,
+		.system_cache_cfg       = 0x90,
+		.read_buff_cfg          = 0x94,
+		.addr_cfg               = 0x98,
+		.debug_status_cfg       = 0xA4,
+		.debug_status_0         = 0xA8,
+		.debug_status_1         = 0xAC,
+		.spare                  = 0x38,
+	},
+};
+
+struct cam_cre_bus_wr_reg_val cre110_bus_wr_reg_value = {
+	.hw_version                   = 0x40000000,
+	.cgc_override                 = 0x1,
+	.irq_mask_0                   = 0xd0000101,
+	.irq_set_0                    = 0xd0000101,
+	.irq_clear_0                  = 0xd0000101,
+	.img_size_violation           = 0x80000000,
+	.violation                    = 0x40000000,
+	.cons_violation               = 0x10000000,
+	.comp_buf_done                = 0x100,
+	.comp_rup_done                = 0x1,
+	.irq_mask_1                   = 0x1,
+	.irq_set_1                    = 0x1,
+	.irq_clear_1                  = 0x1,
+	.irq_status_1                 = 0x1,
+	.irq_cmd_set                  = 0x10,
+	.irq_cmd_clear                = 0x1,
+	.iso_en                       = 0x1,
+	.iso_en_mask                  = 0x1,
+	.misr_0_en                    = 0x1,
+	.misr_0_en_mask               = 0x1,
+	.misr_0_samp_mode             = 0x1,
+	.misr_0_samp_mode_mask        = 0x10000,
+	.misr_0_id_mask               = 0xff,
+	.misr_rd_misr_sel_mask        = 0xf,
+	.misr_rd_word_sel_mask        = 0x70,
+	.num_clients = 1,
+	.wr_clients[0] = {
+		.client_en                = 0x1,
+		.client_en_mask           = 0x1,
+		.client_en_shift          = 0x0,
+		.auto_recovery_en         = 0x1,
+		.auto_recovery_en_mask    = 0x1,
+		.auto_recovery_en_shift   = 0x4,
+		.mode_mask                = 0x3,
+		.mode_shift               = 0x10,
+		.width_mask               = 0xffff,
+		.width_shift              = 0x0,
+		.height_mask              = 0xffff,
+		.height_shift             = 0x10,
+		.x_init_mask              = 0xff,
+		.stride_mask              = 0xffffff,
+		.format_mask              = 0xf,
+		.format_shift             = 0x0,
+		.alignment_mask           = 0x1,
+		.alignment_shift          = 0x5,
+		.bw_limit_en              = 0x1,
+		.bw_limit_en_mask         = 0x1,
+		.bw_limit_counter_mask    = 0x1fe,
+		.client_buf_done          = 0x1,
+		.output_port_id           = CAM_CRE_OUTPUT_IMAGE,
+		.wm_port_id               = 0,
+	},
+};
+
+struct cam_cre_bus_rd_reg_val cre110_bus_rd_reg_value = {
+	.hw_version              = 0x40000000,
+	.irq_mask                = 0x80000001,
+	.rd_buf_done             = 0x4,
+	.rup_done                = 0x2,
+	.cons_violation          = 0x1,
+	.ccif_violation          = 0x80000000,
+	.irq_cmd_set             = 0x10,
+	.irq_cmd_clear           = 0x1,
+	.static_prg              = 0x8,
+	.static_prg_mask         = 0x8,
+	.ica_en                  = 0x1,
+	.ica_en_mask             = 0x2,
+	.go_cmd                  = 0x1,
+	.go_cmd_mask             = 0x1,
+	.irq_set                 = 0x7,
+	.irq_clear               = 0x7,
+	.misr_reset              = 0x1,
+	.security_cfg            = 0x1,
+	.iso_bpp_select_mask     = 0x60,
+	.iso_pattern_select_mask = 0x6,
+	.iso_en                  = 0x1,
+	.iso_en_mask             = 0x1,
+	.num_clients = 1,
+	.rd_clients[0] = {
+		.client_en               = 0x1,
+		.ai_en                   = 0x1,
+		.ai_en_mask              = 0x1000,
+		.ai_en_shift             = 0xc,
+		.pix_pattern_mask        = 0xfc,
+		.pix_pattern_shift       = 0x2,
+		.stripe_location_mask    = 0x3,
+		.stripe_location_shift   = 0x0,
+		.alignment_mask          = 0x1,
+		.alignment_shift         = 0x5,
+		.format_mask             = 0x1f,
+		.format_shift            = 0x0,
+		.latency_buf_size_mask   = 0xffff,
+		.misr_cfg_en_mask        = 0x4,
+		.misr_cfg_samp_mode_mask = 0x3,
+		.x_int_mask              = 0xffff,
+		.byte_offset_mask        = 0xff,
+		.input_port_id           = CAM_CRE_INPUT_IMAGE,
+		.rm_port_id              = 0x0,
+	},
+};
+
+struct cam_cre_bus_wr_reg cre110_bus_wr_reg = {
+	.hw_version                   = 0x00,
+	.cgc_override                 = 0x08,
+	.irq_mask_0                   = 0x18,
+	.irq_mask_1                   = 0x1C,
+	.irq_clear_0                  = 0x20,
+	.irq_clear_1                  = 0x24,
+	.irq_status_0                 = 0x28,
+	.irq_status_1                 = 0x2C,
+	.irq_cmd                      = 0x30,
+	.local_frame_header_cfg_0     = 0x4C,
+	.irq_set_0                    = 0x50,
+	.irq_set_1                    = 0x54,
+	.iso_cfg                      = 0x5C,
+	.violation_status             = 0x64,
+	.image_size_violation_status  = 0x70,
+	.perf_count_cfg_0             = 0x74,
+	.perf_count_cfg_1             = 0x78,
+	.perf_count_cfg_2             = 0x7C,
+	.perf_count_cfg_3             = 0x80,
+	.perf_count_val_0             = 0x94,
+	.perf_count_val_1             = 0x98,
+	.perf_count_val_2             = 0x9C,
+	.perf_count_val_3             = 0xA0,
+	.perf_count_status            = 0xB4,
+	.misr_cfg_0                   = 0xB8,
+	.misr_cfg_1                   = 0xBC,
+	.misr_rd_sel                  = 0xC8,
+	.misr_reset                   = 0xCC,
+	.misr_val                     = 0xD0,
+	.wr_clients[0]             = {
+		.client_cfg           = 0x200,
+		.img_addr             = 0x204,
+		.img_cfg_0            = 0x20C,
+		.img_cfg_1            = 0x210,
+		.img_cfg_2            = 0x214,
+		.packer_cfg           = 0x218,
+		.bw_limit             = 0x21C,
+		.system_cache_cfg     = 0x268,
+		.addr_cfg             = 0x270,
+		.debug_status_cfg     = 0x288,
+		.debug_status_0       = 0x28c,
+		.debug_status_1       = 0x290,
+	},
+};
+
+static struct cam_cre_hw cre_hw_110 = {
+	.top_reg_offset    = &cre110_top_reg,
+	.top_reg_val       = &cre110_top_reg_value,
+	.bus_wr_reg_offset = &cre110_bus_wr_reg,
+	.bus_wr_reg_val    = &cre110_bus_wr_reg_value,
+	.bus_rd_reg_offset = &cre110_bus_rd_reg,
+	.bus_rd_reg_val    = &cre110_bus_rd_reg_value,
+};
+#endif // CAM_CRE_HW_110_H

pineapple_consolidate_defconfig

@@ -1,6 +1,7 @@
 CONFIG_SPECTRA_ISP=y
 CONFIG_SPECTRA_ICP=y
 CONFIG_SPECTRA_JPEG=y
+CONFIG_SPECTRA_CRE=y
 CONFIG_SPECTRA_SENSOR=y
 CONFIG_SPECTRA_USE_CLK_CRM_API=y
 CONFIG_SPECTRA_USE_RPMH_DRV_API=y

pineapple_gki_defconfig

@@ -1,6 +1,7 @@
 CONFIG_SPECTRA_ISP=y
 CONFIG_SPECTRA_ICP=y
 CONFIG_SPECTRA_JPEG=y
+CONFIG_SPECTRA_CRE=y
 CONFIG_SPECTRA_SENSOR=y
 CONFIG_SPECTRA_USE_CLK_CRM_API=y
 CONFIG_SPECTRA_USE_RPMH_DRV_API=y