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@@ -4091,6 +4091,14 @@ static int dsi_display_res_init(struct dsi_display *display)
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display->panel->host_config.force_hs_clk_lane;
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display->panel->host_config.force_hs_clk_lane;
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phy->cfg.phy_type =
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phy->cfg.phy_type =
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display->panel->host_config.phy_type;
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display->panel->host_config.phy_type;
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+
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+ /*
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+ * Parse the dynamic clock trim codes for PLL, for video mode panels that have
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+ * dynamic clock property set.
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+ */
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+ if ((display->panel->dyn_clk_caps.dyn_clk_support) &&
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+ (display->panel->panel_mode == DSI_OP_VIDEO_MODE))
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+ dsi_phy_pll_parse_dfps_data(phy);
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}
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}
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rc = dsi_display_parse_lane_map(display);
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rc = dsi_display_parse_lane_map(display);
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