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qcacmn: Add qcn9224defs for wkk v2

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Added new file specific to qcn9224 v1 defs. Use qcn9224defs.c for v2.
Added changes specific to soc version check.

Change-Id: I5b6aedbb8aba2de847e0f4d47212a25b36bfa7c8
CRs-Fixed: 3243676
This commit is contained in:
Nidhi Jain
2022-07-26 12:36:17 +05:30
committed by Madan Koyyalamudi
parent 9e4b30c842
commit 18377a6679
7 changed files with 265 additions and 0 deletions
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8
hif/inc/hif.h
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@@ -1922,6 +1922,14 @@ void hif_allow_link_low_power_states(struct hif_opaque_softc *hif)
void *hif_get_dev_ba(struct hif_opaque_softc *hif_handle);
void *hif_get_dev_ba_ce(struct hif_opaque_softc *hif_handle);
/**
* hif_get_soc_version() - get soc major version from target info
* @hif_ctx - the HIF context
*
* Return: version number
*/
uint32_t hif_get_soc_version(struct hif_opaque_softc *hif_handle);
/**
* hif_set_initial_wakeup_cb() - set the initial wakeup event handler function
* @hif_ctx - the HIF context to assign the callback to

1
hif/inc/hostdef.h
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@@ -46,6 +46,7 @@ extern struct hostdef_s *QCA6018_HOSTDEF;
extern struct hostdef_s *QCA5018_HOSTDEF;
extern struct hostdef_s *QCN9000_HOSTDEF;
extern struct hostdef_s *QCN6122_HOSTDEF;
extern struct hostdef_s *QCN9224v1_HOSTDEF;
extern struct hostdef_s *QCN9224_HOSTDEF;
extern struct hostdef_s *QCA9574_HOSTDEF;
#endif

2
hif/inc/targetdef.h
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@@ -46,6 +46,7 @@ extern struct targetdef_s *QCA5018_TARGETDEF;
extern struct targetdef_s *QCN9000_TARGETDEF;
extern struct targetdef_s *QCN6122_TARGETDEF;
extern struct targetdef_s *KIWI_TARGETdef;
extern struct targetdef_s *QCN9224v1_TARGETDEF;
extern struct targetdef_s *QCN9224_TARGETDEF;
extern struct targetdef_s *QCA9574_TARGETDEF;
@@ -69,6 +70,7 @@ extern struct ce_reg_def *QCA5018_CE_TARGETDEF;
extern struct ce_reg_def *QCN9000_CE_TARGETDEF;
extern struct ce_reg_def *QCN6122_CE_TARGETDEF;
extern struct ce_reg_def *KIWI_CE_TARGETdef;
extern struct ce_reg_def *QCN9224v1_CE_TARGETDEF;
extern struct ce_reg_def *QCN9224_CE_TARGETDEF;
extern struct ce_reg_def *QCA9574_CE_TARGETDEF;

9
hif/src/hif_main.c
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@@ -455,6 +455,15 @@ void *hif_get_dev_ba_ce(struct hif_opaque_softc *hif_handle)
qdf_export_symbol(hif_get_dev_ba_ce);
uint32_t hif_get_soc_version(struct hif_opaque_softc *hif_handle)
{
struct hif_softc *scn = (struct hif_softc *)hif_handle;
return scn->target_info.soc_version;
}
qdf_export_symbol(hif_get_soc_version);
#ifdef FEATURE_RUNTIME_PM
void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get)
{

1
hif/src/pcie/if_pci.c
View File

@@ -3657,6 +3657,7 @@ static void hif_pci_get_soc_info_pld(struct hif_pci_softc *sc,
scn->cmem_size = info.dev_mem_info[0].size;
scn->target_info.target_version = info.soc_id;
scn->target_info.target_revision = 0;
scn->target_info.soc_version = info.device_version.major_version;
}
static void hif_pci_get_soc_info_nopld(struct hif_pci_softc *sc,

234
hif/src/qcn9224v1def.c Normal file
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@@ -0,0 +1,234 @@
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "qdf_module.h"
#if defined(QCN9224_HEADERS_DEF)
#undef UMAC
#define WLAN_HEADERS 1
#include "wcss_version.h"
#include "wcss_seq_hwiobase.h"
#include "wfss_ce_reg_seq_hwioreg.h"
#define MISSING 0
#define SOC_RESET_CONTROL_OFFSET MISSING
#define GPIO_PIN0_OFFSET MISSING
#define GPIO_PIN1_OFFSET MISSING
#define GPIO_PIN0_CONFIG_MASK MISSING
#define GPIO_PIN1_CONFIG_MASK MISSING
#define LOCAL_SCRATCH_OFFSET 0x18
#define GPIO_PIN10_OFFSET MISSING
#define GPIO_PIN11_OFFSET MISSING
#define GPIO_PIN12_OFFSET MISSING
#define GPIO_PIN13_OFFSET MISSING
#define MBOX_BASE_ADDRESS MISSING
#define INT_STATUS_ENABLE_ERROR_LSB MISSING
#define INT_STATUS_ENABLE_ERROR_MASK MISSING
#define INT_STATUS_ENABLE_CPU_LSB MISSING
#define INT_STATUS_ENABLE_CPU_MASK MISSING
#define INT_STATUS_ENABLE_COUNTER_LSB MISSING
#define INT_STATUS_ENABLE_COUNTER_MASK MISSING
#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
#define INT_STATUS_ENABLE_ADDRESS MISSING
#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
#define HOST_INT_STATUS_ADDRESS MISSING
#define CPU_INT_STATUS_ADDRESS MISSING
#define ERROR_INT_STATUS_ADDRESS MISSING
#define ERROR_INT_STATUS_WAKEUP_MASK MISSING
#define ERROR_INT_STATUS_WAKEUP_LSB MISSING
#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
#define COUNT_DEC_ADDRESS MISSING
#define HOST_INT_STATUS_CPU_MASK MISSING
#define HOST_INT_STATUS_CPU_LSB MISSING
#define HOST_INT_STATUS_ERROR_MASK MISSING
#define HOST_INT_STATUS_ERROR_LSB MISSING
#define HOST_INT_STATUS_COUNTER_MASK MISSING
#define HOST_INT_STATUS_COUNTER_LSB MISSING
#define RX_LOOKAHEAD_VALID_ADDRESS MISSING
#define WINDOW_DATA_ADDRESS MISSING
#define WINDOW_READ_ADDR_ADDRESS MISSING
#define WINDOW_WRITE_ADDR_ADDRESS MISSING
/* GPIO Register */
#define GPIO_ENABLE_W1TS_LOW_ADDRESS MISSING
#define GPIO_PIN0_CONFIG_LSB MISSING
#define GPIO_PIN0_PAD_PULL_LSB MISSING
#define GPIO_PIN0_PAD_PULL_MASK MISSING
/* SI reg */
#define SI_CONFIG_ERR_INT_MASK MISSING
#define SI_CONFIG_ERR_INT_LSB MISSING
#define RTC_SOC_BASE_ADDRESS MISSING
#define RTC_WMAC_BASE_ADDRESS MISSING
#define SOC_CORE_BASE_ADDRESS MISSING
#define WLAN_MAC_BASE_ADDRESS MISSING
#define GPIO_BASE_ADDRESS MISSING
#define ANALOG_INTF_BASE_ADDRESS MISSING
#define CE0_BASE_ADDRESS MISSING
#define CE1_BASE_ADDRESS MISSING
#define CE_COUNT 16
#define CE_WRAPPER_BASE_ADDRESS MISSING
#define SI_BASE_ADDRESS MISSING
#define DRAM_BASE_ADDRESS MISSING
#define WLAN_SYSTEM_SLEEP_DISABLE_LSB MISSING
#define WLAN_SYSTEM_SLEEP_DISABLE_MASK MISSING
#define CLOCK_CONTROL_OFFSET MISSING
#define CLOCK_CONTROL_SI0_CLK_MASK MISSING
#define RESET_CONTROL_SI0_RST_MASK MISSING
#define WLAN_RESET_CONTROL_OFFSET MISSING
#define WLAN_RESET_CONTROL_COLD_RST_MASK MISSING
#define WLAN_RESET_CONTROL_WARM_RST_MASK MISSING
#define CPU_CLOCK_OFFSET MISSING
#define CPU_CLOCK_STANDARD_LSB MISSING
#define CPU_CLOCK_STANDARD_MASK MISSING
#define LPO_CAL_ENABLE_LSB MISSING
#define LPO_CAL_ENABLE_MASK MISSING
#define WLAN_SYSTEM_SLEEP_OFFSET MISSING
#define SOC_CHIP_ID_ADDRESS MISSING
#define SOC_CHIP_ID_REVISION_MASK MISSING
#define SOC_CHIP_ID_REVISION_LSB MISSING
#define SOC_CHIP_ID_REVISION_MSB MISSING
#define FW_IND_EVENT_PENDING MISSING
#define FW_IND_INITIALIZED MISSING
#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
#define SR_WR_INDEX_ADDRESS MISSING
#define DST_WATERMARK_ADDRESS MISSING
#define DST_WR_INDEX_ADDRESS MISSING
#define SRC_WATERMARK_ADDRESS MISSING
#define SRC_WATERMARK_LOW_MASK MISSING
#define SRC_WATERMARK_HIGH_MASK MISSING
#define DST_WATERMARK_LOW_MASK MISSING
#define DST_WATERMARK_HIGH_MASK MISSING
#define CURRENT_SRRI_ADDRESS MISSING
#define CURRENT_DRRI_ADDRESS MISSING
#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK MISSING
#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK MISSING
#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK MISSING
#define HOST_IS_DST_RING_LOW_WATERMARK_MASK MISSING
#define HOST_IS_ADDRESS MISSING
#define MISC_IS_ADDRESS MISSING
#define HOST_IS_COPY_COMPLETE_MASK MISSING
#define CE_WRAPPER_BASE_ADDRESS MISSING
#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS MISSING
#define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING
#define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING
#define HOST_IE_ADDRESS \
HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
WFSS_CE_COMMON_REG_REG_BASE)
#define HOST_IE_REG1_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT
#define HOST_IE_ADDRESS_2 \
HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(\
WFSS_CE_COMMON_REG_REG_BASE)
#define HOST_IE_REG2_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT
#define HOST_IE_ADDRESS_3 \
HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
WFSS_CE_COMMON_REG_REG_BASE)
#define HOST_IE_REG3_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT
#define HOST_IE_COPY_COMPLETE_MASK MISSING
#define SR_BA_ADDRESS MISSING
#define SR_BA_ADDRESS_HIGH MISSING
#define SR_SIZE_ADDRESS MISSING
#define CE_CTRL1_ADDRESS MISSING
#define CE_CTRL1_DMAX_LENGTH_MASK MISSING
#define DR_BA_ADDRESS MISSING
#define DR_BA_ADDRESS_HIGH MISSING
#define DR_SIZE_ADDRESS MISSING
#define CE_CMD_REGISTER MISSING
#define CE_MSI_ADDRESS MISSING
#define CE_MSI_ADDRESS_HIGH MISSING
#define CE_MSI_DATA MISSING
#define CE_MSI_ENABLE_BIT MISSING
#define MISC_IE_ADDRESS MISSING
#define MISC_IS_AXI_ERR_MASK MISSING
#define MISC_IS_DST_ADDR_ERR_MASK MISSING
#define MISC_IS_SRC_LEN_ERR_MASK MISSING
#define MISC_IS_DST_MAX_LEN_VIO_MASK MISSING
#define MISC_IS_DST_RING_OVERFLOW_MASK MISSING
#define MISC_IS_SRC_RING_OVERFLOW_MASK MISSING
#define SRC_WATERMARK_LOW_LSB MISSING
#define SRC_WATERMARK_HIGH_LSB MISSING
#define DST_WATERMARK_LOW_LSB MISSING
#define DST_WATERMARK_HIGH_LSB MISSING
#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK MISSING
#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB MISSING
#define CE_CTRL1_DMAX_LENGTH_LSB MISSING
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK MISSING
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK MISSING
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB MISSING
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB MISSING
#define CE_CTRL1_IDX_UPD_EN_MASK MISSING
#define CE_WRAPPER_DEBUG_OFFSET MISSING
#define CE_WRAPPER_DEBUG_SEL_MSB MISSING
#define CE_WRAPPER_DEBUG_SEL_LSB MISSING
#define CE_WRAPPER_DEBUG_SEL_MASK MISSING
#define CE_DEBUG_OFFSET MISSING
#define CE_DEBUG_SEL_MSB MISSING
#define CE_DEBUG_SEL_LSB MISSING
#define CE_DEBUG_SEL_MASK MISSING
#define CE0_BASE_ADDRESS MISSING
#define CE1_BASE_ADDRESS MISSING
#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES MISSING
#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS MISSING
#define QCN9224v1_BOARD_DATA_SZ MISSING
#define QCN9224v1_BOARD_EXT_DATA_SZ MISSING
#define MY_TARGET_DEF QCN9224v1_TARGETDEF
#define MY_HOST_DEF QCN9224v1_HOSTDEF
#define MY_CEREG_DEF QCN9224v1_CE_TARGETDEF
#define MY_TARGET_BOARD_DATA_SZ QCN9224v1_BOARD_DATA_SZ
#define MY_TARGET_BOARD_EXT_DATA_SZ QCN9224v1_BOARD_EXT_DATA_SZ
#include "targetdef.h"
#include "hostdef.h"
qdf_export_symbol(QCN9224v1_CE_TARGETDEF);
#else
#include "common_drv.h"
#include "targetdef.h"
#include "hostdef.h"
struct targetdef_s *QCN9224v1_TARGETDEF;
struct hostdef_s *QCN9224v1_HOSTDEF;
#endif /*QCN9224_HEADERS_DEF */
qdf_export_symbol(QCN9224v1_TARGETDEF);
qdf_export_symbol(QCN9224v1_HOSTDEF);

10
hif/src/regtable.c
View File

@@ -136,6 +136,12 @@ void hif_target_register_tbl_attach(struct hif_softc *scn, u32 target_type)
#if defined(QCN9224_HEADERS_DEF)
case TARGET_TYPE_QCN9224:
if (scn->target_info.soc_version == 1) {
scn->targetdef = QCN9224v1_TARGETDEF;
scn->target_ce_def = QCN9224v1_CE_TARGETDEF;
hif_info("TARGET_TYPE_QCN9224v1");
break;
}
scn->targetdef = QCN9224_TARGETDEF;
scn->target_ce_def = QCN9224_CE_TARGETDEF;
hif_info("TARGET_TYPE_QCN9224");
@@ -283,6 +289,10 @@ void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type)
#endif
#if defined(QCN9224_HEADERS_DEF)
case HIF_TYPE_QCN9224:
if (scn->target_info.soc_version == 1) {
scn->hostdef = QCN9224v1_HOSTDEF;
break;
}
scn->hostdef = QCN9224_HOSTDEF;
break;
#endif