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asoc: Add support for 11P2896MHz RX clk config

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1. Update RX CLK config for 11P2896MHz.
2. Add condition to update Droop sel coeffs for 11P28MHz
   and 9P6MHz RX CLK.
3. Upate SWR port config for 44.1Khz sample rate usecase.
4. Unselect RX_TOP.SWR_CTRL(0x6AC0008) for RX CLK 11P28MHz.
5. Update HD2_CTL L/R registers as per latest seq version.

Change-Id: Ifac2c03e3d1bf522fe2a4d942341d9071a1e6239
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
This commit is contained in:
Prasad Kumpatla
2023-01-10 18:25:44 +05:30
parent dff100e61b
commit 17a7fb3f4d
7 changed files with 91 additions and 16 deletions
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32
asoc/codecs/lpass-cdc/lpass-cdc.c
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/of_platform.h>
@@ -740,6 +740,36 @@ void lpass_cdc_unregister_macro(struct device *dev, u16 macro_id)
}
EXPORT_SYMBOL(lpass_cdc_unregister_macro);
void lpass_cdc_notify_wcd_rx_clk(struct device *dev, bool is_native_on)
{
struct lpass_cdc_priv *priv;
u32 val;
if (!dev) {
pr_err_ratelimited("%s: dev is null\n", __func__);
return;
}
if (!lpass_cdc_is_valid_child_dev(dev)) {
dev_err_ratelimited(dev, "%s: not a valid child dev\n",
__func__);
return;
}
priv = dev_get_drvdata(dev->parent);
if (!priv) {
dev_err_ratelimited(dev, "%s: priv is null\n", __func__);
return;
}
if (is_native_on)
val = 0x2; /* 11.2896M */
else
val = 0x0; /* 9.6M */
lpass_cdc_notifier_call(priv,
((val << 16) | LPASS_CDC_WCD_EVT_CLK_NOTIFY));
}
EXPORT_SYMBOL(lpass_cdc_notify_wcd_rx_clk);
void lpass_cdc_wsa_pa_on(struct device *dev, bool adie_lb)
{
struct lpass_cdc_priv *priv;