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asoc: Add support for 11P2896MHz RX clk config

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1. Update RX CLK config for 11P2896MHz.
2. Add condition to update Droop sel coeffs for 11P28MHz
   and 9P6MHz RX CLK.
3. Upate SWR port config for 44.1Khz sample rate usecase.
4. Unselect RX_TOP.SWR_CTRL(0x6AC0008) for RX CLK 11P28MHz.
5. Update HD2_CTL L/R registers as per latest seq version.

Change-Id: Ifac2c03e3d1bf522fe2a4d942341d9071a1e6239
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
This commit is contained in:
Prasad Kumpatla
2023-01-10 18:25:44 +05:30
parent dff100e61b
commit 17a7fb3f4d
7 changed files with 91 additions and 16 deletions
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5
asoc/codecs/lpass-cdc/lpass-cdc-rx-macro.c
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@@ -2794,12 +2794,13 @@ static int lpass_cdc_rx_macro_enable_interp_clk(struct snd_soc_component *compon
lpass_cdc_rx_macro_config_classh(component, rx_priv,
interp_idx, event);
/*select PCM path and swr clk is 9.6MHz*/
if (rx_priv->is_pcm_enabled) {
if (rx_priv->is_pcm_enabled && !rx_priv->is_native_on) {
if (rx_priv->pcm_select_users == 0)
snd_soc_component_update_bits(component,
LPASS_CDC_RX_TOP_SWR_CTRL, 0x02, 0x02);
++rx_priv->pcm_select_users;
}
lpass_cdc_notify_wcd_rx_clk(rx_dev, rx_priv->is_native_on);
}
rx_priv->main_clk_users[interp_idx]++;
}
@@ -2812,7 +2813,7 @@ static int lpass_cdc_rx_macro_enable_interp_clk(struct snd_soc_component *compon
snd_soc_component_update_bits(component, main_reg,
0x10, 0x10);
/*Unselect PCM path*/
if (rx_priv->is_pcm_enabled) {
if (rx_priv->is_pcm_enabled && !rx_priv->is_native_on) {
if (rx_priv->pcm_select_users == 1)
snd_soc_component_update_bits(component,
LPASS_CDC_RX_TOP_SWR_CTRL, 0x02, 0x00);